Abstract: A new semiconductor material or compound and method for its manufacture is disclosed. The material or compound has the Formula III-V or IV which includes as part of the compound, a transition element or a rare earth element present in an amount sufficient to change the material or compound from a paramagnetic state to a locally ordered magnetic state. The material or compound is made by depositing III, and V or IV and a transition element or a rare earth element onto a substrate at conditions such that the transition element or rare earth element that is deposited on the substrate is not in equilibrium with the material or compound. By employing this technique new semiconductor materials or compounds can be made including Ga.sub.1-x Mn.sub.x As and In.sub.1-x Mn As where Mn is present in an amount greater than about 5.4.times.10.sup.20 cm.sup.-3.

Abstract: An apparatus and method for the nonplanar treatment of a volumetric workpiece or substrate utilizing exposure beam lithography are disclosed. The method includes supplying one or more layers of one or more semiconductor materials to surfaces of the substrate, applying a resist over the semiconductor layers, setting the resist, and then directing an exposure beam, such as an electron beam, toward the substrate. The substrate is then moved in at least two degrees freedom of movement, relative to the beam, with one degree of freedom of movement being the rotating of the substrate about an axis generally perpendicular to the beam. The other degree of freedom of movement could be moving the substrate linearly in a direction generally parallel to the axis. By such movement, the resist is exposed to the beam in a predetermined pattern. The exposed resist is then developed and a layer or layers under the exposed resist are etched. The remaining resist is then removed yielding the desired semiconductor device.

Abstract: A pre-processed substrate structure for a semiconductor device. A subcollector layer is spaced apart from a substrate by a dielectric. A relatively small, lightly-doped epitaxial feed-through layer extends through the dielectric between the substrate and the subcollector. A transistor constructed over the subcollector has very low collector-to-substrate capacitance. A plurality of devices on a common substrate are electrically isolated from each other by channel stops formed in the substrate around each device.

Abstract: The invention is a method for growing homoepitaxial films of SiC on low-tilt-angle vicinal (0001) SiC wafers. The invention proposes and teaches a new theoretical model for the homoepitaxial growth of SiC films on (0001) SiC substrates. The inventive method consists of (1) preparing the growth surface of SiC wafers slightly off-axis (from less than 0.1.degree. to 6.degree.) from the (0001) plane, (2) subjecting the growth surface to a suitable etch, and then (3) growing the homoepitaxial film using conventional SiC growth techniques.

Abstract: A semiconductor fabrication process improves the crystal structure of a polycrystalline semiconductor. Adding impurities in large quantities causes an acceleration of the crystallization without noticeably increasing the number of spontaneous nucleations in the material. The result is a region of relatively larger crystalline grains within the doped region which extend approximately 1 .mu.m into the undoped region by the time the entire material has crystallized. Junction devices can be created with better electrical characteristics than ordinary polycrystalline semiconductor devices due to fewer grain boundaries at the electrical junctions. One fabrication technique can result in single crystal devices. Another implementation shows a method for fabricating improved polycrystalline vertical diodes such as solar cells.

Abstract: A process and structure involving a silicon substrate utilizes an ultra high vacuum and molecular beam epitaxy (MBE) methods to grow an epitaxial oxide film upon a surface of the substrate. As the film is grown, the lattice of the compound formed at the silicon interface becomes stabilized, and a base layer comprised of an oxide having a sodium chloride-type lattice structure grows epitaxially upon the compound so as to cover the substrate surface. A perovskite may then be grown epitaxially upon the base layer to render a product which incorporates silicon, with its electronic capabilities, with a perovskite having technologically-significant properties of its own.

Abstract: Heterostructures having a large lattice mismatch between an upper epilayer and a substrate and a method of forming such structures having a thin intermediate layer are disclosed. The strain due to a lattice mismatch between the intermediate layer and the substrate is partially relieved by the formation of edge type dislocations which are localized and photoelectrically inactive. Growth of the intermediate layer is interrupted before it reaches the thickness at which the left over strain is relieved by 60 degree type threading dislocations. The upper epilayer is then grown in an unstrained and defect-free condition upon the intermediate layer where the unstrained lattice constant of the epilayer is about the same as the partially relieved strain lattice constant or the intermediate layer. An unstrained defect-free epilayer of InGaAs has been grown on a GaAs substrate with an intermediate layer 3-10 nm in thickness of InAs.

Abstract: Disclosed is a method of making a semiconductor device that comprises MBE at substrate temperatures substantially lower than conventionally used temperatures. A significant aspect of the method is the ability to produce highly doped (e.g., 10.sup.19 cm.sup.-3) epitaxial single crystal Si layers. The deposition can be carried out such that substantially all (at least 90%) dopant atoms are electrically active at 20.degree. C. However, the method is not limited to Si MBE. Exemplarily, the method can be used to produce epitaxial single crystal GaAs having very short (e.g., <100ps) carrier lifetime. Such material can be useful for, e.g., high speed photodetectors. Incorporation into the method of a relatively low temperature rapid thermal anneal makes possible low temperature MBE growth of relatively thick semiconductor layers.

Abstract: `Unintentionally` doped P type GaAs is grown on silicon by a metal organic chemical vapor deposition process in which the molecular ratio of arsenic to gallium in the growth ambient is reduced to a value that is sufficiently low to cause the creation of donor (As) site vacancies in the grown GaAs layer, which become occupied by acceptor (carbon) atoms in the metal organic compound, thereby resulting in the formation of a buffer GaAs layer having a P type majority carrier characteristic. Preferably, the silicon substrate has its growth surface inclined from the [100] plane toward the [011] direction is initially subjected to an MOCVD process (e.g. trimethyl gallium, arsine chemical vapor deposition) at a reduced temperature (e.g. 425.degree. C.) and at atmospheric pressure, to form a thin (400 Angstroms) nucleation layer. During this growth step the Group V/Group III mole ratio (of arsenic to gallium) is maintained at an intermediate value. The temperature is then ramped to 630.degree. C.

Abstract: A II-VI group compound crystal article comprises a substrate having a non-nucleation surface with smaller nucleation density (S.sub.NDS) and a nucleation surface (S.sub.NDL) which is arranged adjacent to said non-nucleation surface (S.sub.NDS), has a sufficiently small area for a crystal to grow only from a single nucleus and a larger nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said non-nucleation surface (S.sub.NDS) and is comprised of an amorphous material, and a II-VI group compound monocrystal grown from said single nucleus on said substrate and spread on said non-nucleation surface (S.sub.NDS) beyond said nucleation surface (S.sub.NDL).

Abstract: Silicon ingots, in particular, with diameters of approximately 75 mm and greater, can be produced by zone pulling with an oxygen content comparable to crucible-pulled material if a flat quartz element is brought into contact with the molten cap during the pulling operation. A quartz ring which is arranged concentrically beneath the induction heating coil and can be lowered from a rest position into its working position on the molten cap is suitable as a flat element. The ingot material obtained in this manner and also the silicon wafers produced therefrom combine the purity advantages of zone-pulled silicon with the beneficial gettering and hardening action of the incorporated oxygen which otherwise distinguishes only crucible-pulled silicon.

Abstract: An ion implantation process for producing a buried insulating layer of silicon dioxide in a silicon substrate which takes advantage of the effects of surface erosion and sputtering inherent to the ion implantation process. The process allows the production of an insulating layer buried within a silicon semiconductor wherein the width of the insulating layer can be contoured by controlling the beam energy during implantation.

Abstract: This invention relates to an improvement in a reduced gaseous phase growing method for compound semiconductor monocrystal formed from a plurality of elements such as GaAs.A gas of compound containing each of constitutional elements is introduced into a reduced reaction pipe of which temperature distribution is controlled, without use of H.sub.2 or He as a carrier gas. Thereby it is possible to control the amount of introduction of each of the elements of the compound semiconductor subjected to epitaxial growth.In addition, the temperature distribution within the reaction pipe is controlled and the temperature of the crystal substrate is maintained at a relatively low temperature to improve the quality of the growing crystal.

Abstract: Single crystal silicon for a substrate of semiconductor integrated circuits is disclosed. Cu, Fe, Ni and Cr are contained as impurities in a concentration smaller than 0.1 ppta, respectively, and the total content of the impurities is less than 0.4 ppta. Oxygen-induced stacking faults are reduced to an absolute minimum.

Abstract: A high density of bulk defects suitable for gettering fast diffusing impurities is provided in heavily doped N-type semiconductor (e.g., Si) wafers by forming a surface damage layer of predetermined thickness (e.g., by lapping and etching), then heating first to a temperature to facilitate precipitate nucleation (e.g., SiO.sub.x) and second to a higher temperature to facilitate nuclei growth, and thereafter etching away the remaining surface damage. The correct amount of surface damage, accelerates the formation of bulk precipitate complexes for pinning heavy metals, beyond what would be obtained for the same temperature and time without the surface damage, and without inducing undesirable crystal defects.

Abstract: A vapor-phase epitaxial growth method for producing a Groups III-V compound semiconductor containing arsenic by vapor-phase epitaxial growth using arsenic trihydride as an arsenic source is disclosed, wherein said arsenic trihydride has a volatile impurity concentration of not more than 1.5 molppb on a germanium tetrahydride conversion. The resulting epitaxial crystal has a low residual carrier concentration and is applicable to a field effect transistor.

Abstract: A method of making group I-III-VI compound semiconductors such as copper indium diselenide for use in thin film heterojunction photovoltaic devices. A composite film of copper, indium, and possibly other group IIIA elements, is deposited upon a substrate. A separate film of selenium is deposited on the composite film. The substrate is then heated in a chamber in the presence of a gas containing hydrogen to form the compound semiconductor material.

Abstract: A microcrystalline silicon-containing silicon carbide semiconductor film has an optical energy gap of not less than 2.0 eV, and a dark electric conductivity of less than 10.sup.-6 Scm.sup.-1. The Raman scattering light of the microcrystalline silicon-containing silicon carbide semiconductor film, which shows the presence of silicon crystal phase, has a peak in the vicinity of 530 cm.sup.-1. This microcrystalline silicon-containing silicon carbide semiconductor film is formed on a substrate by preparing a mixture gas having a hydrogen dilution rate .gamma., which is the ratio of the partial pressure of hydrogen gas to the sum of the partial pressure of a silicon-containing gas and the partial pressure of a carbon-containing gas, of 30, transmitting microwave of a frequency of not less than 100 MHz into the mixture gas near a substrate with an electric power density of not less than 4.4.times.10.sup.-2, and generating plasma at a temperature of the substrate of not less than 200.degree. C.

Abstract: Device quality monocrystalline Alpha-SiC thin films are epitaxially grown by chemical vapor deposition on Alpha-SiC [0001] substrates prepared off axis.

Abstract: A semiconductor substrate is provided with alignment marks for recognizing and deciding positions of registration of a wafer and a mask in a photolithographic step that is included in a process of manufacturing a semiconductor device. The alignment marks, X alignment marks and Y alignment marks in a preferred embodiment are arranged only on straight lines which are parallel to corresponding X and Y axes of a Cartesian Coordinate system for registration of the substrate the alignment marks which extend to avoid obstructions, such as steps defined along dicing lines that prevent flow of resist to be coated onto the semiconductor substrate.

Abstract: This invention relates to ultra-thin semiconductor films which can be in the submicron range formed from semiconductor materials such as silicon, germanium and gallium arsenide. The films are formed by creating a thin slightly damaged surface on the polished reverse side of a film (e.g., a wafer) of the semiconductor by low dose ion implantation and then etching the semiconductor material on the front side of the film to remove the semiconductor material down to the ion implanted damaged layer. While the implanted ions can be chosen from functionally desirable ions which upon annealing remain in the film to alter the original electrical characteristics, the implanted ions can also be chosen so that upon annealing, the resultant ultra-thin semiconductor film has the same electrical characteristics as the original semiconductor material.The ion implantation changes the etching characteristics of the ion implanted layer.

Abstract: This invention relates to ultra-thin semiconductor films which can be in the submicron range formed from semiconductor materials such as silicon, germanium and gallium aresenide. The films are formed by creating a thin slightly damaged surface on the polished reverse side of a film (e.g., a wafer) of the semiconductor by low dose ion implantation and then etching the semiconductor material on the front side of the film to remove the semiconductor material down to the ion implanted damaged layer. While the implanted ions can be chosen from functionally desirable ions which upon annealing remain in the film to alter the original electrical characteristics, the implanted ions can also be chosen so that upon annealing, the resultant ultra-thin semiconductor film has the same electrical characteristics as the original semiconductor material.The ion implantation changes the etching characteristics of the ion implanted layer.

Abstract: A material for a light emitting element most suited for a light emitting diode or laser diode which emits visible light of 550 to 650 nm band wavelength. The material provides an at least two-layered structure composed of a GaAs substrate and a Sn doped InGaP layer developed on the substrate without forming a gradient layer therebetween. The mixed crystal composition of the Sn doped InGaP layer as expressed by the molar fraction of GaP is 0.50 to 0.75.According to the method for developing mixed crystals of InGaP, GaP and InP are dissolved in Sn to make a solution. The solution is allowed to come in contact with a GaAs substrate so that InGaP crystals are developed directly on the GaAs substrate without a gradient layer for coordinating the lattice constant formed on the GaAs substrate.

Abstract: A semiconductor structure is provided comprising a bulk substrate of semiconductor material having a first-type doping conductivity in a first dopant concentration. A first layer of semiconductor material is epitaxially formed on the substrate, such first layer having the first-type doping conductivity in a second dopant concentration lower than the first concentration. A second layer of semiconductor material is epitaxially formed on the first layer, the second layer having a second-type doping conductivity opposite to the first-type doping conductvity and thereby forming a P-N junction with the first layer. A plurality of regions, comprising semiconductor material having the first-type doping conductivity and extending through the second layer and a predetermined distance into the first layer, are further included for providing electrical isolation between active devices formed in different regions of the second layer.

Abstract: Polycrystalline silicon rod capable of providing within no more than two floating zoning passes, unicrystalline silicon exhibiting a resistivity of at least 10,000 ohm-cm (donor) and a lifetime of at least about 10,000 milliseconds, exhibits a copper X-ray diffraction pattern having a peak at 26.85.degree..+-.0.25.degree. (2 theta) and has less than 15 ppta boron and less than 20 ppta phosphorus.

Abstract: In a method of performing a solution growth of a ZnSe crystal using Se as a solvent and relying on the temperature difference technique, the growth is performed under the conditions that the vapor pressure of Zn which is lower than the vapor pressure of Se is applied, under controlled manner, to the solvent during the growth process, in which the value of the Zn vapor pressure is held constant at 7.2 atm. .+-.30%, whereby a ZnSe crystal having a good crystal perfection is obtained.

Abstract: The invention relates to a process and an apparatus for the manufacture of monocrystal reflectors of copper, silver or gold for laser applications according to . . . patent application No. P 32 29 697.5-51 as well as reflectors manufactured according to this process.

Abstract: A conductive substrate for the deposition of material thereon which comprises an insulating layer upon said substrate, and a pluralitry of aperatures in said insulating layer containing conductive material formed from said substrate forming a plurality of metallic nucleating centers for the adherence of said material to said substrate.

Abstract: An intermetallic compound semiconductor thin film comprises a single crystalline deposition thin film made of a III-V group intermetallic compound having a stoichiometry composition ratio of 1:1. When forming the III-V group semiconductor thin film by an evaporation method, a substrate temperature is initially maintained at a high level while the evaporation source temperature is gradually raised, and when the intermetallic composition of the III-V group begins to deposit on the substrate, the substrate temperature is lowered while the evaporation source temperature is maintained at the same level as existed at the time when the intermetallic compound is deposited, and the deposition time is controlled.

Abstract: An epitaxial wafer for producing arrays of GaAsP-LEDs comprises, in the GaAs.sub.1-x P.sub.x layer with varying X, a layer region(s) with a discontinuous variance of x along the thickness of the GaAs.sub.1-x P.sub.x layer. This layer region(s) contribute to a uniformity in the brightness of the light emission of LEDs formed in the epitaxial wafer.

Abstract: A heteroepitaxial growth method comprising growing a semiconductor single-crystal film on a semiconductor single-crystal substrate with a lattice constant different from that of the semiconductor single-crystal film by chemical vapor deposition, the epitaxial orientation of the semiconductor single-crystal film being inclined at a certain angle with respect to the semiconductor single-crystal substrate.

Abstract: A doping composition having a high rate of P.sub.2 O.sub.5 evolution as indicated by a thick deposited glassy film of about 1500-2000 angstroms at a doping temperature of only 900.degree. C. for one hour, the composition comprising a gadolinium oxide/P.sub.2 O.sub.5 compound.

Abstract: A semiconductor substrate includes: a first monocrystalline semiconductive layer formed on the surface of a crystalline silicon substrate with the intervension of a first insulation film; a second insulation film set to the upper surface of the first monocrystalline semiconductive layer and provided with a plurality of apertures each having a specific pattern; and a second monocrystalline semiconductive layer which is epitaxially grown by the seed crystallization process and provided with the same crystalline characteristics as that of the first monocrystalline semiconductive layer.Accordingly, the preferred embodiment of the present invention provides an extremely useful semiconductor substrate which easily isolates the elements of semiconductor devices between layers of insulating film described above.

Abstract: A boron-containing heterocyclic compound prepared by reacting a primary amine of ammonia with an alkylene oxide or epoxide and then reacting concurrently or subsequently this reaction intermediate with a boric acid. This boron-containing heterocyclic compound may further be reacted with a metal metalloid or other metal compound and even further contain sulfur, such as a sulfide group.

Abstract: A wear resistance rail which comprises 0.50 to 0.85 wt. % of C, 0.10 to 1.0 wt. % of Si, 0.50 to 1.50 wt. % of Mn, less than 0.035 wt. % of P, less than 0.035 wt. % of S, less than 0.050 wt. % of Al, and the balance of iron and impurities. The web has a high toughness tempered bainite structure, tempered martensite structure or a tempered mixed structure of bainite and martensite and the head rail has high wear resistance which prevents unstable destructive cracks from propagating. The rail can further contain one or more of 0.05 to 1.50 wt. % of Cr, 0.05 to 0.20 wt. % of Mo, 0.03 to 0.10 wt. % of V, 0.10 to 1.00 wt. % of Ni, and 0.005 to 0.050 wt. % of Nb.

Abstract: A layer of HgCdTe (15) is epitaxially grown on a crystalline support (10). A single crystal CdTe substrate (5) is first epitaxially grown to a thickness of between 1 micron and 5 microns onto the support (10). Then a HgTe source (3) is spaced from the CdTe substrate (5) a distance of between 0.1 mm and 10 mm. The substrate (5) and source (3) are heated together in a thermally insulating, reusable ampoule (17) within a growth temperature range of between 500.degree. C. and 625.degree. C. for a growth time of between 5 minutes and 13 hours. In a first growth step embodiment, the source (3) and substrate (5) are non-isothermal. In a second growth step embodiment, the source (3) and substrate (5) are isothermal. Then an optional interdiffusion step is performed, in which the source (3) and substrate (5) are cooled within a temperature range of between 400.degree. C. and 500.degree. C. for a time of between 1 hour and 16 hours.

Abstract: A solid body formed by the chemical vapor-phase deposition of, for example, boron nitride is used as a solid dopant source for diffusion doping of semiconductor substrates in place of conventional sintered bodies of boron nitride. By virtue of the extremely low impurity content of the vapor-deposited dopant source in comparison with conventional sintered bodies, which unavoidably contain impurities originating in the powder of the dopant compound for sintering and the binder to facilitate sintering, the semiconductor substrate doped using the inventive dopant source has outstandingly low densities of lattice defects and dislocations in addition to the absence of troubles in the diffusion process due to melting of the binder contained in the sintered dopant sources.

Abstract: A semiconductor body with an improved passivating layer is disclosed. In one embodiment, the body is a device comprising a semiconductor material having regions of opposite conductivity types which form a semiconductor junction therebetween which extends to a surface of the device. The passivating layer, comprising silicon oxynitride having a refractive index between about 1.55 and 1.75 and a substantial hydrogen content, overlies the surface at the junction.Also disclosed is a method for fabricating such a device wherein the vapor deposition of the passivating layer is carried out at low temperatures from an ambient having a ratio of silicon-containing to oxygen- and nitrogen-containing precursors of between about 1:1.67 and 1:5.

Abstract: High phosphorus polyphosphides, namely MP.sub.x, where M is an alkali metal (Li, Na, K, Rb, and Cs) or metals mimicking the bonding behavior of an alkali metal, and where x=7 to 15 or very much greater than 15 (new forms of phosphorus) are useful semiconductors in their crystalline, polycrystalline and amorphous forms (boules and films). MP.sub.15 appears to have the best properties and KP.sub.15 is the easier to synthesize. P may include other pnictides as well as other trivalent atomic species. Resistance lowering may be accomplished by doping with Ni, Fe, Cr, and other metals having occupied d or f outer electronic levels; or by incorporation of As and other pnictides. Rectifying Schottky junction devices doped with Ni and employing Ni as a back contact comprise Cu, Al, Mg, Ni, Au, Ag, and Ti as junction forming top contacts. Photovoltaic, photoresistive, and photoluminescent devices are also disclosed. All semiconductor applications appear feasible.

Abstract: A method of making an integrated electrooptic solid state device array comprising forming a structure having a multiplicity of active, solid state electrooptic component bodies in a solid state device material, including arranging the component bodies in a geometrical pattern and forming the component bodies to a prespecified size of less than 15 microns each and to an accuracy to within a fraction of a micron, and providing at least one electronic rectifying barrier at each of the component bodies for the operation of each component body as an active solid state electrooptic component.

Abstract: An InP wafer, comprising a S.I. InP substrate, a n-type InP active layer disposed on the substrate and oxygen implanted isolation regions disposed in the active layer.

Abstract: More than two impurities are doped in a host crystal of compound semiconductors. One of the impurities is an anisoelectronic impurity. One or more than one impurities are isoelectronic impurities. The anisoelectronic impurity determines the electronic property and the carrier density of the semiconductor. Isoelectronic impurity does not change the electronic property. But isoelectronic impurity has an effect of impurity hardening.The impurity atom forms a covalent bond with a host atom. The bond length between an impurity and a host atom differs from the standard bond between host atoms. Although the real bond lengths between an impurity atom and a host atom cannot be measured, the Inventors think the difference of bond lengths generate dislocation or other lattice defects of crystal.

Abstract: A copper alloy lead material for leads of a semiconductor device, which consists essentially of from 2 to 2.4 percent by weight iron, from 0.001 to 0.1 percent by weight phosphorus, from 0.01 to 1 percent by weight zinc, from 0.001 to 0.1 percent by weight magnesium, and the balance of copper and inevitable impurities. The copper alloy lead material possesses satisfactory properties such as elongation and electrical conductivity required of a material for leads in a semiconductor device, and further exhibits excellent strength and heat resistance enough to be used as leads in semiconductor devices having high wiring densities, and at the same time possesses improved soldering reliability to the substrate of the semiconductor device as compared to a conventional copper alloy lead material.

Abstract: The invention described herein describes certain test wafers to be used in diagnosing heavy metal contamination in furnaces used in the manufacture of electronic devices and the method of referencing such wafers to a common wafer source for establishing an accurate baseline for a furnace to determine if it is functioning adequately or if an impurity or contaminant problem exists.

Abstract: An integrated complementary transistor circuit at an intermediate stage of manufacturing comprises a semiconductor substrate having dopant atoms of a first conductivity type and having a substantially flat major surface; a patterned layer of material that is essentially impervious to oxygen diffusion covering first and second spaced apart areas on the surface and having openings which expose the surface between the areas; a channel stop region having dopant atoms of the first conductivity type with a larger doping concentration than the substrate throughout that portion of the surface which is exposed by the openings; and a well region having dopant atoms of a second conductivity type opposite to the first type in the substrate under all of the second area and extending under an adjacent portion of the channel stop region but terminating before reaching the first area; the well region also having a depth and doping concentration at the center of the second area which is substantially smaller than the depth an

Abstract: Disclosed is a silicon semiconductor substrate for a semiconductor integrated circuit such as LSI or VLSI. The silicon semiconductor substrate has an oxygen concentration ranging from 3.times.10.sup.17 cm.sup.-3 to 7.times.10.sup.17 cm.sup.-3 and a gettering layer on its backside. This gettering layer may comprise a nonsingle crystalline silicon layer such as polycrystalline silicon layer or amorphous silicon layer, or a layer having stacking fault density of more than 3.times.10.sup.4 cm.sup.-2.

Abstract: N+ type semiconductor substrates containing oxygen are thermally treated to enhance internal gettering capabilities by heating at 1050.degree. to 1200.degree. C., then at 500.degree. to 900.degree. C. and finally at 950.degree. to 1250.degree. C.

Abstract: A GaAs single crystal containing at least one impurity selected from the group consisting of B, Si, S, Te and In in a concentration of at least 10.sup.15 /cm.sup.3, fluctuation of which is not larger than 20% in a plane perpendicular to a growth direction of the single crystal, which is prepared by pulling up the GaAs single crystal from a GaAs raw material melt contained in a crucible which is encapsulated with a liquid encapsulating layer in an inactive gas atmosphere at a high pressure with applying a magnetic field to the raw material melt.

Abstract: Semiconductor substrate materials, such as silicon, useful in the manufacture of electronic devices, such as integrated circuits, employing low temperature, i.e., below 1025.degree. C. processing cycles are provided with a 0.05 to 2.0 micron thick layer of polysilicon on the backside to improve gettering capabilities of defects, contaminants and impurities away from the active device region of the substrate.

Abstract: Semiconductor substrate materials, such as silicon, useful in the manufacture of electronic devices, such as integrated circuits, employing low temperature, i.e., below 1025.degree. C. processing cycles are provided with a 0.05 to 2.0 micron thick layer of polysilicon on the backside to improve gettering capabilities of defects, contaminants and impurities away from the active device region of the substrate.