Preformed Panel Circuit Arrangement (e.g., Printed Circuit) Patents (Class 174/250)
  • Patent number: 11240915
    Abstract: A method for manufacturing a multilayer wiring board is disclosed. The method includes steps of preparing printed wiring boards having both electrical connection pads for establishing an electrical connection between the boards and non-connection pads for not establishing an electrical connection between the boards on the same plane, overlaying the boards so that the electrical connection pads face each other, and laminating the boards so that the boards are bonded to each other through a conductive paste provided between the facing electrical connection pads. To prepare the printed wiring boards, attach an insulating film to at least one of surfaces faced when the boards are overlaid in the overlaying, bore holes in the insulating film so that the electrical connection pads are exposed, and provide a conductive paste in the holes.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: February 1, 2022
    Assignee: Lincstech Co., Ltd.
    Inventors: Masahiro Kato, Eiichi Shinada, Yuto Tanabe
  • Patent number: 11231626
    Abstract: A film type package includes: a base film having first and second sides; a driver integrated circuit mounted on the base film; first connection pads disposed on a first area of the base film that is adjacent to the first side of the base film, and configured to be connected to a first external circuit; second connection pads disposed on a second area of the base film that is adjacent to the second side of the base film, and configured to be connected to a second external circuit; first signal lines disposed on the base film, and connecting the driver integrated circuit and the first connection pads; second signal lines disposed on the base film, and connecting the driver integrated circuit and the second connection pads; and a plurality of test lines extending from the driver integrated circuit to the first side of the base film.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung Hun Han, Jung Eun Koo, So Young Lim
  • Patent number: 11234082
    Abstract: A carrier substrate and a method for making a carrier substrate are disclosed. In an embodiment a carrier substrate includes a substrate body having a multilayer structure, electrical connection pads on a top surface of the substrate body, an organic cushion layer on the top surface of the substrate body, electrically conductive elongated parts arranged on top of the cushion layer, wherein each conductive elongated part is contacted to a respective electric connection pad and a solder pad located at an end of each elongated part distant from the respective connection pad.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: January 25, 2022
    Assignee: TDK CORPORATION
    Inventor: Wolfgang Pahl
  • Patent number: 11229118
    Abstract: A printed circuit board, comprising a flexible insulating layer, a rigid insulating layer laminated on a portion of the flexible insulating layer, and a coverlay disposed on an upper surface of the rigid insulating layer, an upper surface of the flexible insulating layer, and a side surface of the rigid insulating layer positioned between the upper surface of the rigid insulating layer and the upper surface of the flexible insulating layer.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 18, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Chang-Hwa Park
  • Patent number: 11227834
    Abstract: A system including an analog block and a digital block. The analog block and the digital block are arranged on a package. The package includes a first ground coupled to the analog block and a second ground coupled to the digital block. The second ground is physically separate from the first ground. The package also includes a noise-mitigation stitching connector that has a first end connected to the first ground and a second end connected to the second ground.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: January 18, 2022
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Karthik Chandrasekar, Ratnakar Dadi, Shawn Tzung-Sheng Lo, Emmanuel Atta, Alexander Tain, Subodh Yashwant Bhike
  • Patent number: 11191168
    Abstract: A composite circuit board includes a composite circuit board unit, a first solder mask formed on a first metal protection layer of the composite circuit board unit, and a second solder mask formed on a second metal protection layer of the composite circuit board unit. Two ends of a first outer conductive circuit are bent back toward each other and spaced apart a predetermined distance to form a first window. Two ends of a second outer conductive circuit are bent back toward each other and spaced apart a predetermined distance to form a second window.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 30, 2021
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Yang Li, Yan-Lu Li
  • Patent number: 11189980
    Abstract: An analysis method and an analysis system for optimization of a high-speed signal connector are provided. The method includes: setting an excess portion of each of a pin and a pad in the high-speed signal connector to be different lengths; equating the excess portion of each of the pin and the pad with an inductor and a capacitor; analyzing performance of connectors having different lengths of the excess portion of the pin and different lengths of the excess portion of the pad, and comparing performance parameters of the connectors; and obtaining a length of the excess portion of the pin and a length of the excess portion of the pad in a case of an optimal performance parameter, and cutting the pin and the pad based on the obtained lengths.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: November 30, 2021
    Assignee: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY CO., LTD.
    Inventor: Fazhi Liu
  • Patent number: 11186918
    Abstract: The present disclosure provides a micro-rough electrolytic copper foil and a copper clad laminate. The electrolytic copper foil has a micro-rough surface formed with mountain-shaped structures and recessed structures. A multiplication value of an arithmetic mean height (Sa) and a vertex density (Spd) of the mountain-shaped structures measured according to ISO 25178 is between 150000 ?m/mm2 and 400000 ?m/mm2. An arithmetic mean undulation (Wa) of the mountain-shaped structures measured according to JIS B0601:2001 is between 0.06 ?m and 1.5 ?m. Therefore, the electrolytic copper foil with good binding strength and electrical properties can be obtained.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 30, 2021
    Assignee: CO-TECH DEVELOPMENT CORP.
    Inventor: Yun-Hsing Sung
  • Patent number: 11179040
    Abstract: An attachable monitoring device includes a battery unit, a flexible printed circuit board and a physical condition sensor and an adhesive. The battery unit includes a top surface, a bottom surface and a plurality of side surfaces connecting the top surface and the bottom surface. The flexible printed circuit board is bent to cover the top surface, the bottom surface and one of the side surfaces and electrically connected to the battery unit. The flexible printed circuit board includes a printed antenna printed on a first outer surface of the flexible printed circuit board. The physical condition sensor is disposed on a second outer surface of the flexible printed circuit board opposite to the first outer surface. The physical condition sensor includes a sensing region for contacting a user to detecting a physical-condition signal of the user. The adhesive is disposed on the flexible printed circuit board for being attached to the user.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 23, 2021
    Assignee: iWEECARE Co., Ltd.
    Inventors: Chun-Hao Tseng, Shih-Chien Lin, Ho-Yi Chang, Kai-Chieh Chang
  • Patent number: 11181787
    Abstract: A touch apparatus includes a substrate, a plurality of pixel structures, a first touch electrode, a second touch electrode, a third touch electrode and a first conductive pattern. The first touch electrode and the second touch electrode are located at a first side of a transparent window. The third touch electrode is located at a second side of the transparent window. The first touch electrode, the second touch electrode and the third touch electrode are sequentially arranged in a first direction. A main portion of the first conductive pattern is electrically connected to the first touch electrode. The main portion of the first conductive pattern overlaps with the second touch electrode and is electrically isolated from the second touch electrode. A dummy portion of the first conductive pattern is electrically connected to the third touch electrode and structurally separated from the main portion of the first conductive pattern.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 23, 2021
    Assignee: Au Optronics Corporation
    Inventors: Hsun-Chen Chu, Pei-Ming Chen
  • Patent number: 11177200
    Abstract: A package includes a corner, a device die having a front side and a backside, and a molding material molding the device die therein. A plurality of redistribution lines is on the backside of the device die. The plurality of redistribution lines includes a plurality of metal pads. A polymer layer contacts the plurality of metal pads. A plurality of openings is formed in the polymer layer, with the plurality of metal pads aligned to and exposed to the plurality of openings. The plurality of openings includes a corner opening that is elongated and an additional opening farther away from the corner than the corner opening. The additional opening is non-elongated.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 11178752
    Abstract: A circuit board with an electrostatic discharge protection mechanism and an electronic apparatus having the same are provided. The circuit board includes a substrate, at least one signal trace, and a conductive element. The at least one signal trace is disposed on the substrate. The conductive element is electrically connected to a ground plane of the substrate and crosses over the at least one signal trace. The conductive element has at least one discharging portion. The position of the at least one discharging portion corresponds to the at least one signal trace. A gap exists between the at least one discharging portion and the at least one signal trace. A static electricity of the at least one signal trace is discharged to the at least one discharging portion.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 16, 2021
    Assignee: PEGATRON CORPORATION
    Inventors: Bo-Yu Lin, Ping-Chung Wu, Wei-Chun Tsao
  • Patent number: 11155494
    Abstract: A glass article (100) includes a core layer (102) formed from a core glass composition with a core coefficient of thermal expansion (CTE) and first (104) and second (106) cladding layers fused to first and second major surfaces of the core layer (102) and formed from a clad glass composition comprising a clad CTE. An aperture (120) extends through each of the core layer (102), the first cladding layer (104), and the second cladding layer (106). The clad CTE is less than the core CTE such that each of the first (104) and second (106) cladding layers is under a compressive stress and the core layer (102) is under a tensile stress. A flexural strength of the glass article (100) can be at least about 75 MPa. A peak load sustainable by the glass article (100) in a modified ring-on-ring test can be at most 96.5% less than a peak load sustainable by a reference glass article in the modified ring-on-ring test.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: October 26, 2021
    Assignee: CORNING INCORPORATED
    Inventors: David Aaron Burnett, Shai Negev Shafrir, Kevin Eugene Spring, Vijay Subramanian
  • Patent number: 11152293
    Abstract: A wiring board includes an insulating layer including a first insulating film provided with a first surface and a second surface that is opposite to the first surface, and composed of only resin, and a second insulating film provided with a first surface and a second surface that is opposite to the first surface, including a reinforcing member and resin, in which the reinforcing member is impregnated with the resin, and stacked on the first surface of the first insulating film such that the second surface of the second insulating film contacts the first surface of the first insulating film and the second surface of the first insulating film is exposed outside; and a first wiring layer embedded in the first insulating film, a predetermined surface of the first wiring layer being exposed from the second surface of the first insulating film.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: October 19, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kazuhiro Oshima, Hiroharu Yanagisawa, Kazuhiro Kobayashi, Katsuya Fukase, Ken Miyairi
  • Patent number: 11153973
    Abstract: An electronic module, such as a VRM, has a power inductor and power wave pins disposed on a bottom surface of a circuit board so as to reduce the size and increase the heat dissipation capability of the VRM.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: October 19, 2021
    Assignee: CYNTEC CO., LTD.
    Inventors: Kaipeng Chiang, Da-Jung Chen, Bau-Ru Lu, Chun Hsien Lu
  • Patent number: 11139517
    Abstract: The present disclosure provides a battery pack including a plurality of cylindrical battery cells forming a clamping part by coupling a cap assembly on one opened surface of a cylindrical can and forming a first electrode terminal and a second electrode terminal on a top surface of the clamping part and a top end central portion of the cap assembly, respectively, and a first electrode terminal connecting plate simultaneously coupled to upper end surfaces of the clamping parts of the battery cells in a state in which cylindrical battery cells are laterally arranged so that the cap assemblies of the cylindrical battery cells head in the same direction.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 5, 2021
    Assignee: LG CHEM, LTD.
    Inventors: Kun Joo Yang, Yong Jun Cho, Seog Jin Yoon
  • Patent number: 11139247
    Abstract: An interconnection structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer has a first surface and a second surface, both facing toward the first dielectric layer. The first surface of the second dielectric layer is recessed from the second surface of the second dielectric layer and defines a recess. A portion of the first dielectric layer is disposed within the recess.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11140784
    Abstract: A printed wiring board includes a base film having insulation properties and a conductive pattern including multiple wiring portions laminated so as to run on at least one surface of the base film, wherein each wiring portion includes a first conductive portion and a second conductive portion coating an outer surface of the first conductive portion, wherein an average width of each wiring portion is 10 ?m or greater to 50 ?m or smaller, and an average thickness of the second conductive portion is 1 ?m or greater to smaller than 8.5 ?m. A method for manufacturing a printed wiring board includes a first conductive portion forming step of forming a first conductive portion forming each wiring portion by plating an opening of the resist pattern on the conductive foundation layer, a conductive foundation layer removing step, and a second conductive portion coating step.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: October 5, 2021
    Assignees: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kohei Okamoto, Kousuke Miura, Hiroshi Ueda, Shoichiro Sakai, Maki Ikebe
  • Patent number: 11129313
    Abstract: The present disclosure pertains to an electromagnetic-wave shielding film and a preparation method thereof. The electromagnetic-wave shielding film includes a first metal layer, an insulating layer, and a second metal layer. The first metal layer has two opposite surfaces. The insulating layer is disposed on one of the surfaces of the first metal layer. The second metal layer is disposed on the other surface of the first metal layer and contains nano metal particles and an binder. The electromagnetic-wave shielding film can be used in a printed circuit board, and shows a satisfactory electromagnetic wave shielding effect.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: September 21, 2021
    Assignee: ETERNAL MATERIALS CO., LTD.
    Inventors: Shu-Hung Liu, Chih-Ching Chen, Chin-Yi Liao
  • Patent number: 11122689
    Abstract: A circuit assembly (200) is disclosed comprising a substrate (210) and conducting layers (250) on opposing sides of the substrate (210), there being at least one via (220) through the substrate (210), which via (220) forms a conductive path between the conducting layers, wherein the substrate (210) is a foam substrate, and wherein the via (220) is provided with a solid dielectric lining (270) plated with a conducting material (250).
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: September 14, 2021
    Assignee: MBDA UK LIMITED
    Inventors: Adam Armitage, Thomas James Heaton
  • Patent number: 11096277
    Abstract: A circuit board and method of manufacture therefor utilize voltage domain edge plating disposed on at least a portion of one or more edges of a circuit board to electrically couple voltage domain conductive shapes disposed in different conductive layers of the circuit board. By doing so, interconnection of multiple voltage domain conductive shapes in different conductive layers may be facilitated with improved power integrity, while also providing EMI shielding along the edge of the circuit board.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Edni Del Rosal, Anil Yuksel, David Green
  • Patent number: 11090858
    Abstract: A method of fabricating a cross-layer pattern in a layered object is disclosed. The method is executed by an additive manufacturing system and comprises: dispensing a patterning material onto a receiving medium to form a first pattern element; dispensing a first layer of modeling material onto the first pattern element while forming a first open cavity exposing at least a portion of the first pattern element beneath the first layer; and dispensing patterning material onto the exposed portion of the first pattern element and the first layer to form a second pattern element contacting the first pattern element.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: August 17, 2021
    Assignee: Stratasys Ltd.
    Inventors: Daniel Dikovsky, Ira Yudovin-Farber, Efraim Dvash
  • Patent number: 11073957
    Abstract: a touch panel and a display device are provided, the touch panel includes: a plurality of columns of touch units, each column of touch units includes a plurality of touch units arranged along a first direction, and at least one touch unit in a same column of touch units comprises a plurality of first electrode patterns and a plurality of second electrode patterns arranged in parallel, each of the first electrode patterns and the second electrode patterns has a ribbon shape and extends along the first direction, the plurality of first electrode patterns and the plurality of second electrode patterns are alternately arranged along the second direction, the second direction and the first direction intersect each other, and the first electrode patterns and the second electrode patterns are electrically insulated from each other.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: July 27, 2021
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guiyu Zhang, Hongqiang Luo, Yichen Jiang
  • Patent number: 11069540
    Abstract: A method for fabricating an interposer substrate is provided, including forming a wiring layer on a carrier, forming an insulating layer on the carrier, forming on the wiring layer a wiring build-up layer structure that is electrically connected to the wiring layer, forming on the wiring build-up layer structure external connection pillars that are electrically connected to the wiring build-up layer structure, and removing the carrier, with the wiring layer is exposed from a surface of the insulating layer. The fabrication process of the via can be bypassed in the fabrication process by forming coreless interposer substrate on the carrier, such that the overall cost of the fabrication process can be decreased, and the fabrication process is simple. This invention further provides the interposer substrate.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: July 20, 2021
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventor: Pao-Hung Chou
  • Patent number: 11062997
    Abstract: A method for forming a chip package structure is provided. The method includes forming a conductive pillar over a redistribution structure. The method includes bonding a chip to the redistribution structure. The method includes forming a molding layer over the redistribution structure. The molding layer surrounds the conductive pillar and the chip, and the conductive pillar passes through the molding layer. The method includes forming a cap layer over the molding layer and the conductive pillar. The cap layer has a through hole exposing the conductive pillar, and the cap layer includes fibers. The method includes forming a conductive via structure in the through hole. The conductive via structure is connected to the conductive pillar.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Techi Wong, Po-Yao Lin, Ming-Chih Yew, Po-Hao Tsai, Po-Yao Chuang
  • Patent number: 11063378
    Abstract: Technologies and implementations for a clip to connect coaxial cables onto a printed circuit board assembly (PCBA) is disclosed. The technologies and implementations facilitate improved signal integrity from the cable to various components of the PCBA. Additionally, the technologies and implementations help facilitate management of mechanical variations during connection of the coaxial cable.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: July 13, 2021
    Assignee: West Affum Holdings Corp.
    Inventors: Robert R. Buchanan, Douglas K. Medema, Daniel R. Piha, Dallas E. Meeker, Daniel J. Finney
  • Patent number: 11056279
    Abstract: Provided is a laminate of a sintered body produced by sintering a copper powder paste and a ceramic substrate, which has improved adhesion between the sintered body and the ceramic substrate. A laminate with a copper powder paste sintered body laminated on a ceramic layer, the laminate comprising portions where one or more elements selected from Si, Ti and Zr derived from a copper powder surface treatment agent are together present with a thickness in a range of from 5 to 15 nm in boundaries between the copper powder paste sintered body and the ceramic layer, when observing the boundaries by scanning the laminate with STEM over 100 nm across the boundaries in a thickness direction of the laminate.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: July 6, 2021
    Assignee: JX Nippon Mining & Metals Corporation
    Inventor: Hideki Furusawa
  • Patent number: 11034081
    Abstract: A method of fabricating a cross-layer pattern in a layered object is disclosed. The method is executed by an additive manufacturing system and comprises: dispensing a patterning material onto a receiving medium to form a first pattern element; dispensing a first layer of modeling material onto the first pattern element while forming a first open cavity exposing at least a portion of the first pattern element beneath the first layer; and dispensing patterning material onto the exposed portion of the first pattern element and the first layer to form a second pattern element contacting the first pattern element.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: June 15, 2021
    Assignee: Stratasys Ltd.
    Inventors: Daniel Dikovsky, Ira Yudovin-Farber, Efraim Dvash
  • Patent number: 11026334
    Abstract: A method for producing a wired circuit board including an insulating layer and a conductive pattern, including (1), providing the insulating layer having an inclination face; (2), providing a metal thin film at least on the surface of the insulating layer; (3), providing a photoresist on the surface of the metal thin film; (4), disposing a photomask so that a first portion, where the conductive pattern is provided in the photoresist, is shielded from light, and the photoresist is exposed to light through the photomask; (5), removing the first portion to expose the metal thin film corresponding to the first portion; and (6), providing the conductive pattern on the surface of the metal thin film exposed from the photoresist. The inclination face has a second portion that allows the light reflected at the metal thin film to reach the first portion.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: June 1, 2021
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuu Sugimoto, Hiroyuki Tanabe, Yoshito Fujimura
  • Patent number: 11026356
    Abstract: An electrical device comprises a printed circuit board, a first contact portion, a second contact portion, a first conductive wall and a second conductive wall. The printed circuit board has a first surface and a second surface, on which the first contact portion and the second contact portion are disposed, respectively. The first conductive wall and the second conductive wall are in electrical contact with the first contact portion and the second contact portion, respectively. The first contact portion and the second contact portion are offset from one another in a direction parallel to at least one of the first surface and the second surface.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 1, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Marc Soler, Javier Gonzalez, Jordi Oriol
  • Patent number: 11019729
    Abstract: The device intended to be thermoformed comprises a substrate capable of being thermoformed and an electrically conductive member integral with the said substrate. The electrically conductive member comprises: electrically conductive particles, an electrically conductive material, electrically conductive elements of elongated shape. The electrically conductive material has a melting point which is strictly less than the melting point of the electrically conductive particles and than the melting point of the elements of elongated shape.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 25, 2021
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Mohammed Benwadih
  • Patent number: 11015740
    Abstract: A support member-attached wire harness includes a wire harness including an electrical wire and a support member that includes a fitting portion formed in a partially cylindrical shape that is opened partially in a circumferential direction so as to be capable of being fitted to an outer peripheral portion of a bar-shaped member. On at least one of the wire harness and the support member, a support portion for supporting the wire harness disposed along an outer periphery of the fitting portion at a fixed position with respect to the fitting portion is formed.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: May 25, 2021
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Haruka Nakano, Shigeki Ikeda, Daisuke Fukai, Tetsuya Nishimura, Motohiro Yokoi, Housei Mizuno, Takashi Ide, Daiki Nagayasu, Daisuke Ebata
  • Patent number: 11016620
    Abstract: A touchscreen panel includes a substrate, a conductive layer disposed in a predetermined pattern on the substrate, and an insulating layer disposed on the conductive layer. The insulating layer includes grooves recessed in a surface of the insulating layer. The grooves include first grooves and the second grooves. The first grooves extend in a first direction. The second grooves are arranged in line in a second direction intersecting the first direction. The second grooves are recessed to the conductive layer. The first and the second grooves are filled with conductive materials. The conductive materials in the first grooves form first lines. The conductive materials in the second grooves form second lines. The first lines are configured for detection of a position of touch in the second direction. The second lines are configured for detection of a position of the touch in the first direction.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: May 25, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takatoshi Kira, Mikihiro Noma
  • Patent number: 11013160
    Abstract: There is provided a component mounting method for mounting an electronic component provided with a connecting pin on a board having a through-hole, including inserting the pin of the electronic component into an inner hole filled with solder paste at a first electrode provided in the through-hole to execute a component mounting operation of lowering the pin to a predetermined mounting height position and pulling up the pin once inserted and lowered into the inner hole in the component mounting operation to a preset intermediate height position.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 18, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tetsuya Tanaka, Masahiko Akasaka, Koji Sakurai, Toshihiko Nagaya
  • Patent number: 10991669
    Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: April 27, 2021
    Assignee: MediaTek Inc.
    Inventors: Che-Ya Chou, Wen-Sung Hsu, Nan-Cheng Chen
  • Patent number: 10959327
    Abstract: A plate-shaped multilayer wiring substrate includes at least two resin layers stacked on top of each other and each including an insulating base and a conductive pattern provided on the insulating base, and a front surface layer joined onto the resin layers stacked. The front surface layer has a higher elastic modulus than an elastic modulus of the insulating bases. A joint interface between the resin layers and the front surface layer includes projections and depressions. Also, a method for manufacturing the plate-shaped multilayer wiring substrate includes a step of stacking, on top of resin layers, a front surface layer having a higher elastic modulus than an elastic modulus of the resin layers, and a step of performing pressing under pressure from above the front surface layer by using a flat surface in a heated state to join the resin layers and the front surface layer.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: March 23, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shinichi Araki, Hideyuki Taguchi, Hayato Noma, Ryosuke Takada
  • Patent number: 10959337
    Abstract: A method for manufacturing connection structure, the method includes arranging a first composite on a first surface of a first member where a first electrode is located and arranging conductive particles on the first electrode, arranging a second composite on a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: March 23, 2021
    Assignee: MIKUNI ELECTRON CORPORATION
    Inventor: Sakae Tanaka
  • Patent number: 10950517
    Abstract: A printed circuit board (PCB) includes an insulating layer with an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Soo-Jae Park
  • Patent number: 10950668
    Abstract: The present application provides a display substrate, a manufacturing method thereof, and a display apparatus. The display substrate of the present invention includes a base substrate, a display unit provided on the base substrate, a color filter layer provided on the display unit, a planarization layer provided on a surface of the color filter layer distal to the display unit, and a plurality of first electrodes and a plurality of second electrodes provided in the planarization layer. The planarization layer includes a first planarization layer and a second planarization layer, the plurality of first electrode are embedded in the first planarization layer, and the plurality of second electrodes are embedded in the second planarization layer.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: March 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Huang
  • Patent number: 10949045
    Abstract: A flexible touch substrate and a touch device including the flexible touch substrate are provided. The flexible touch substrate includes a plurality of sides. Each of at least one of the plurality of sides has notches at its both ends. Each of the notches has two edges whose extension directions cross each other, and the two edges of each of the notches have a same length.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 16, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qingpu Wang, Dacheng Deng, Haitao Liu, Taofeng Xie
  • Patent number: 10943945
    Abstract: A flexible printed circuit board and method of fabrication are disclosed. The flexible printed circuit board has a flexible body with multiple segments. Each segment has multiple body contacts that are electrically isolated from body contacts of each other segment. The flexible printed circuit further has multiple flexible legs in which each leg extends from a different segment and contains multiple leg contacts disposed proximate to a distal end of the leg from the body. Each leg contact is connected with a different body contact of the leg. The flexible printed circuit board is formed from a multilayer structure that includes: a dielectric layer, a metal layer adjacent to the dielectric layer, and a solder mask layer adjacent to the metal layer, the solder mask layer exposing portions of the metal layer to form the body contacts.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: March 9, 2021
    Assignee: Lumileds LLC
    Inventors: Frederic Stephane Diana, Yifeng Qiu, Michael Wasilko, Nazila Soleimani, Jeroen Den Breejen, Alan Andrew McReynolds, Gregory Donald Guth
  • Patent number: 10945334
    Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate conductor layers, second conductor layers including second inner, outer and intermediate conductor layers, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including a metal foil layer and a plating film layer, the first and/or second outer conductor layers has the first laminated structure, the first and/or second intermediate conductor layers has a second laminated structure including a metal foil layer and a plating film layer, and the first and second laminated structures are formed such that a surface of the second laminated structure on a side away from the core layer has unevenness smaller than unevenness of a surface of the first laminated structure on a side away from the core layer.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 9, 2021
    Assignee: IBIDEN CO., LTD.
    Inventors: Takenobu Nakamura, Takahiro Yamazaki, Takashi Yamauchi, Toshihide Makino
  • Patent number: 10939543
    Abstract: An apparatus is provided including a transformer including a first printed circuit board having one or more conducting layers, the one or more conducting layers forming, at least in part, a transformer coil; at least one inductor; and at least one continuous piece of conducting material external to the printed circuit board, where the at least one continuous piece of conducting material forms a connection between the transformer and the at least one inductor. A method is also provided for assembling a switched-mode power supply.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Paul W Coteus, Andrew Ferencz, Todd Takken, Yuan Yao, Xin Zhang
  • Patent number: 10912201
    Abstract: Provided is an electronic device capable of supplying large current to a circuit pattern, without employing a thick film structure for the circuit pattern. The electronic device includes a substrate, a wiring layer placed on the upper surface of the substrate, an electronic component mounted above the wiring layer, and a bonding layer placed between the electronic component and the wiring layer. The wiring layer and the bonding layer are porous layers containing pores. The bonding layer has higher volume density than the wiring layer except underneath the electronic component.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: February 2, 2021
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Akihiko Hanya, Tsukasa Imura
  • Patent number: 10902974
    Abstract: A transparent conductive film is disclosed. The transparent conductive film includes a substrate and a first silver nanowire layer. The transparent conductive film has a first absorption peak at 340 nm to 400 nm and a second absorption peak at 500 nm-650 nm, and a ratio of a maximum peak intensity of the first absorption peak to a maximum peak intensity of the second absorption peak is in a range of 2 to 5.5.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: January 26, 2021
    Assignee: Cambrios Film Solutions Corporation
    Inventors: Yung-Cheng Chang, Min-Yu Chen, Yu-Wei Hou, Chung-Chin Hsiao
  • Patent number: 10891011
    Abstract: A touch sensor includes a substrate layer, sensing electrodes on the substrate layer, and optical compensation patterns. The sensing electrodes include electrode lines therein which extend in different directions to cross each other. The sensing electrodes are defined by separation regions at which portions of the electrode lines are cut. The optical compensation patterns are disposed at a different level or a different plane from that of the sensing electrodes. The optical compensation pattern at least partially fills the separation regions in a planar view. Optical properties of the touch sensor are improved by the optical compensation pattern, and visibility of electrodes is prevented.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: January 12, 2021
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Sang Jin Park, Do Hyoung Kwon, Sung Jin Noh, Han Tae Ryu, Jun Gu Lee
  • Patent number: 10879203
    Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Chih-Wei Lin, Cheng-Ting Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10879204
    Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: December 29, 2020
    Assignee: Sensors Unlimited, Inc.
    Inventors: Wei Zhang, Wei Huang, Joshua Lund, Namwoong Paik
  • Patent number: 10872864
    Abstract: In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 10872942
    Abstract: A display device includes a substrate having a first region in which an image is displayed, a second region in which an image is not displayed, and a bending region connecting the first region and the second region. The bending region is configured to bend along a bending axis which extends in a first direction. A plurality of pad terminals is disposed within the second region. A first width of the bending region, measured along the first direction, is narrower than a second width of the second region, measured along the first direction.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 22, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Tae Hoon Kwon, Won Kyu Kwak, Kwang-Min Kim, Hey Jin Shin, Seung-Kyu Lee