Abstract: A circuit board includes a rigid board including a first wiring layer formed on its upper surface side, and a flexible board including a base material having flexibility and disposed on an upper surface side of the first wiring layer, a second wiring layer formed on the base material, and a via wiring formed in a through-hole passing through the second wiring layer and the base material. The via wiring has a protrusion protruding from an upper surface of the second wiring layer, and extending on the upper surface of the second wiring layer positioned on an outer circumferential side of the through-hole.

Abstract: An object of the present invention is to provide a semiconductor module with high heat dissipation at a low cost. A semiconductor module according to the present invention includes: a case having a hollow portion; a base board made of an aluminum alloy having a first portion corresponding to the hollow portion of the case, and a second portion corresponding to a main body portion of the case, the base board being attached to a bottom face of the case via the second portion; a ceramic insulating substrate disposed on the first portion of the base board; a wiring pattern disposed on the ceramic insulating substrate; semiconductor elements disposed on the wiring pattern; metal wiring boards connected to the semiconductor elements; and a sealing resin that seals the hollow portion of the case.

Abstract: A gold-plating etching process for 5G high-frequency signal boards is carried out according to the following steps: the outer dry film, the plug gold-plating, the film removing, and the alkaline etching. The alkaline etching solution comprises 100 to 150 g/L of cupric chloride, 90 to 120 g/L of ammonium chloride, and ammonia. The pH value is 9.6 to 9.8. The ratio of the ammonia and the alkaline etching solution is (550-800):1000. The present invention provides a gold-plating etching process of 5G high-frequency signal boards. The alkaline etching procedure is performed right after gold-plating, eliminating the outer etching process after gold-plating. Costs of the outer film pressing, the exposure, and the development can be saved. The flow rate is improved. Requirements of 5G communication circuit boards are satisfied. That is, the transmission speed of 5G communication high-frequency signal boards of the present invention is fast.

Abstract: A ground conductor film is formed at an insulating substrate. A floating conductor film capacitively couples to the ground conductor film. A radiating element is connected to the floating conductor film. A shielding film shields an electromagnetic wave radiated from the radiating element. By applying such a configuration to a printed circuit board, noise reduction can be achieved.

Abstract: A flexure chain blank sheet includes frame units. Each frame unit includes a frame portion, and flexure elements. The flexure element includes a distal end portion, and an extending portion. The frame portion includes a pair of lengthwise frames and a pair of lateral frames. The first lateral frame connects between tail portions of the flexure elements. The second lateral frame is formed of a distal end linking portion which is constituted by connecting between respective adjacent extending portions. The distal end linking portion includes first cut-off portions to be cut along a longitudinal direction between the adjacent extending portions, and second cut-off portions to be cut along a width direction between the distal end portion and the extending portion.

Abstract: Integrated circuit interconnect structures having a metal oxide adhesive layer between conductive interconnects and dielectric material, as well as related apparatuses and methods are disclosed herein. For example, in some embodiments, an integrated circuit interconnect structure may include a dielectric layer having 60% or more filler, a conductive layer, and a metal oxide adhesive layer between the dielectric and conductive layers. In some embodiments, the metal oxide adhesive layer may include one or more of aluminum oxide, chromium oxide, and nickel oxide.

Abstract: Disclosed is a method of manufacturing an adhesive film including: preparing a transparent adhesion layer, disposing a film mask including a light-transmitting region and a light-shielding region on the transparent adhesion layer, applying ultraviolet (UV) light to the transparent adhesion layer through the film mask to precure an area of the transparent adhesion layer corresponding to the light-transmitting region of the film mask, and cutting the precured area of the transparent adhesion layer.

Abstract: A contactor having the top ends of its pogo pins contacting the leads of a semiconductor device package positioned in a handler at controlled temperature, and the bottom ends of the pogo pins contacting the pads of electrically conducting vias extending vertically through a heatable interposer. The heatable interposer has a first and a second surface and includes alternating horizontal layers of thermally conductive material and thermally insulating material, and further one or more heating layers operable to control a temperature profile from the first to the second surface, including a temperature control at the first surface. The via pads at the second interposer surface are in contact with the printed circuit board of a tester.

Abstract: A multilayer wiring board has a central wiring layer disposed in the center of an odd number of wiring layers, insulating layers and wiring layers disposed above and below the central wiring layer, respectively, an interlayer connections having cross-sectionally trapezoidal shapes and penetrating the insulating layers to establish interlayer connection between the wiring layers. The interlayer connection is disposed to connect to a portion below the central wiring layer. The interlayer connection is disposed to connect to a portion above the central wiring layer. The directions of tapers of the cross-sectionally trapezoidal shapes of the interlayer connections are identical.

Abstract: A multilayer substrate includes a component mounting electrode, an external mounting electrode, and a heat dissipating unit. The component mounting electrode is connected to an electronic component that is connected to an external structure. The heat dissipating unit is constituted by a plurality of via-conductors partially superposed each other in a stacking direction of the multilayer substrate and disposed continuously between the component mounting electrode and the external mounting electrode. The heat dissipating unit includes communicating portions, each in which one via-conductor is disposed per ceramic layer, and a branching portion in which a plurality of via-conductors are disposed continuously between the communicating portions per ceramic layer.

Abstract: The present disclosure presents techniques to facilitate improving operation of an electrical system, which includes a bus structure that cascades multiple electrical devices. The bus structure includes a first outer conductive layer implemented as a positive layer; a second outer conductive layer implemented as a negative layer; a first intermediate conductive layer neighboring the first outer conductive layer; a second intermediate conductive layer neighboring the second outer conductive layer; and a third intermediate conductive layer neighboring the second intermediate conductive layer, in which the third intermediate conductive layer is implemented as an inter-device layer that facilitates electrically coupling at least two of the electrical devices in series.

Abstract: A heat sink is mounted to a PCB for thermal heat removal. The PCB is configured with plated through hole vias within a footprint of the heat sink. The plated through hole vias can include thermal via types and signal carrying via types. The signal carrying via types are landless vias on the PCB back side configured to eliminate physical and electrical contact between the plated through hole via and the heat sink. The landless via is configured by removing a conductive annular ring on the back side of the PCB, and then covering this area with an insulating material such as soldermask. The insulating material forms an insulation cap between the via side wall plating and the attached heat sink.

Abstract: A semiconductor package structure includes a substrate, a first semiconductor device, a first encapsulant and a second encapsulant. The substrate has a first coefficient of thermal expansion CTE1. The first semiconductor device is disposed adjacent to a first surface of the substrate. The first encapsulant is disposed on the first surface of the substrate, and covers at least a portion of the first semiconductor device. The first encapsulant has a second coefficient of thermal expansion CTE2. The second encapsulant is disposed on a second surface of the substrate and has a third coefficient of thermal expansion CTE3. A difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3.

Abstract: A touch display panel, a manufacturing method, a display device and a touch substrate are provided. The touch display panel, comprising a display region and a non-display region surrounding the display region; the display region includes a base substrate and a touch function layer arranged on the base substrate; the non-display region includes the base substrate, and a white light-shielding layer and a reflection enhancing layer which are sequentially arranged on the base substrate, and the reflection enhancing layer is configured for increasing reflectivity of the touch display panel with respect to incident rays; the touch function layer, the white light-shielding layer and the reflection enhancing layer are located on a same side of the base substrate. The touch display panel can improve brightness of appearance of a white OGS touch screen.

Abstract: A wiring board includes: a first substrate that includes signal wiring; a second substrate that includes a conductor with an area larger than an area of the signal wiring, and projection formed on a face of the conductor and constituted of an insulator with a pattern corresponding to a pattern of the signal wiring, the second substrate being arranged so that the face of the conductor on which the projection is formed faces the signal wiring; and an intermediate layer that is arranged between the signal wiring and the conductor and includes a fibrous member.

Abstract: The method for producing a wired circuit board including an insulating layer and a conductive pattern provided on the insulating layer includes the steps of the following: a step (1), in which the insulating layer is provided; a step (2), in which a metal thin film is provided on an inclined face of the insulating layer; a step (3), in which a photoresist is provided on the metal thin film; a step (4), in which a photomask is disposed so that in the photoresist, a portion where the conductive pattern is to be provided is shielded from light, and the photoresist is exposed to light through the photomask; a step (5), in which the portion of the photoresist shielded from light by the photomask is removed to expose the metal thin film corresponding to the portion; and a step (6), in which the conductive pattern is provided on the metal thin film exposed from the photoresist.

Abstract: An integrated circuit chip and a method for protecting the integrated circuit chip against physical and/or electrical alterations are disclosed. The chip comprises at least one semiconductor layer including semiconductor components and conductive tracks, at least one layer formed by a first type of conductive tracks extending over all or part of a surface of the chip and at least one second type of conductive track connected to at least one detection circuit configured to detect an alteration of the at least one second type of conductive track. The chip is characterized in that the at least one first type of conductive track is mixed within the at least one second type of conductive track, the material and the layout of at least one second type of conductive track being indiscernible, by an observation device, from the material and the layout of the at least one first type of conductive track.

Abstract: A BGA 9 includes a wiring substrate 2, a semiconductor chip 1 fixed on the wiring substrate 2, a sealing body 4 that seals the semiconductor chip 1, and a plurality of solder balls 5 provided on a lower surface of the wiring substrate 2. A degree of flatness of an upper surface 2ia of a first wiring layer 2i of the wiring substrate 2 of the BGA 9 is lower than a degree of flatness of a lower surface 2ib, and a first pattern 2jc provided in a second wiring layer 2j is arranged at a position overlapping a first pattern 2ic provided in the first wiring layer 2i. Also, an area of the first pattern 2ic provided in the first wiring layer 2i is larger than an area of a plurality of (for example, two) second patterns 2jd provided in the second wiring layer 2j in a plan view, and a first opening portion 2jm through which a part of a second insulating layer 2h is exposed is formed in the first pattern 2jc provided in the second wiring layer 2j.

Abstract: A flexure chain blank sheet includes a plurality of frame units. Each of the frame units includes a frame portion, and a plurality of flexure elements arranged within the frame portion. The frame portion includes lengthwise frames extending in a longitudinal direction of the flexure elements, and lateral frames extending in a width direction of the flexure elements. A slit that extends along the lateral frames, a connection portion, and recesses are formed between adjacent frame units. An opening width of the recesses is greater than an opening width of the slit. The connection portion includes a portion-to-be-cut which is to be cut by a cutter. The recesses allow insertion of the cutter.

Abstract: A printed wiring board includes one or more substrates, the one or more substrates including at least a first substrate, the first substrate being formed with a pad and a ground layer at any one of main surfaces of the first substrate, the pad being to be electrically connected to a connector as another component, the ground layer being formed to surround the pad from a circumference of the pad and have an inner edge at a location separated from an outer edge of the pad with a predetermined distance, the ground layer being to be grounded to a ground contact.

Abstract: An impedance matching structure is disposed on a circuit board for matching an impedance of a transmission line for transmitting an electronic signal. The structure includes: at least two redundant conducting sections coupled to different points between an input terminal and an output terminal of the transmission line, wherein the redundant conducting sections are apart from one another, and a first terminal of each of the redundant conducting sections is coupled to the transmission line, while a second terminal of each of the redundant conducting sections is apart from the transmission line; and at least one grounded conducting section, each of which corresponds to one of the redundant conducting sections, and surrounds in separation from the corresponding redundant conducting section, wherein each of the at least two redundant conducting sections is disposed in a corresponding plating hole.

Abstract: A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer. When the wafer is diced, the die bond pads are severed along their length, leaving a portion of the die bond pads exposed at an edge of the diced semiconductor die. Having die bond pads at the edge of the die minimizes the offset between die when stacked into a package.

Abstract: An inductor bridge is provided with a flexible flat plate-shaped element body, a first connector, and a second connector. The element body includes therein an inductor portion. The inductor portion is configured by a spiral conductor pattern. The first connector is provided on the element body and is connected to a first circuit. The second connector is provided on the element body and is connected to a second circuit.

Abstract: The invention relates to a circuit carrier (1) comprising a plurality of inorganic substrate layers (1.1) that have partial metallizations (1.2, 1.3, 1.4, 1.5, 1.6) for the purpose of electrical and/or thermal conduction, and to a corresponding method for producing such a circuit carrier (1). According to the invention, at least one partial metallization is made in the form of an insert (1.2) that fills a corresponding shaped hole (1.7) introduced into one of said inorganic substrate layers (1.1).

Abstract: The invention describes a laser device comprising between two and six mesas (120) provided on one semiconductor chip (110), wherein the mesas (120) are electrically connected in parallel such that the mesas (120) are adapted to emit laser light if a defined threshold voltage is provided to the mesas (120). Two to six mesas (120) with reduced active diameter in comparison to a laser device with one mesa improve the yield and performance despite of the fact that two to six mesas need more area on the semiconductor chip thus increasing the total size of the semiconductor chip (110). The invention further describes a method of marking semiconductor chips (110). A functional layer of the semiconductor chip (110) is provided and structured in a way that a single semiconductor chip (110) can be uniquely identified by means of optical detection of the structured functional layer. The structured layer enables identification of small semiconductor chips (110) with a size below 200 ?m×200 ?m.

Abstract: The present disclosure provides a via structure and a multilayer circuit board including the via structure. The via structure is provided in three or more conductor layers in the same electrical network, the conductor layers overlapping with each other vertically and including at least one current input layer and at least one current output layer; wherein the via structure includes a plurality of rows of vias, each row of vias puncture through at least one current input layer and at least one current output layer, and a part of the rows of vias puncture through all of the conductor layers, and the other part of the rows of vias puncture through a part of the conductor layers. By using the via structure in the present disclosure, the vias are subject to even temperature and thus the lifetime of the circuit board is extended.

Abstract: Capacitively coupled vertical transitions are configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent vertical transitions is achieved with overlapping metal surfaces within the vertical transitions. In embodiments, one or more of the overlapping metal surfaces are vias, via pads, or metal stub features extending off a vertical transition. In embodiments, signal paths with overlapped vertical transitions are utilized to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, capacitively coupled vertical transitions are implemented in a package substrate, an interposer, or a printed circuit board.

Abstract: A method of forming a semiconductor package includes receiving a carrier, coating the carrier with a bonding layer, forming a first insulator layer over the bonding layer, forming a backside redistribution layer over the first insulator layer, forming a second insulator layer over the backside redistribution layer, patterning the second insulator layer to form a recess that extends through the second insulator layer and to the backside redistribution layer, filling the recess with a solder, and coupling a surface-mount device (SMD) to the solder.

Abstract: A printed wiring board includes a core laminate body including insulating layers, conductor layers including first and second conductor layers, and via conductors having smaller end surfaces connected to the first conductor layer, a first build-up layer formed on the core body and including an interlayer, a conductor layer on the interlayer, and via conductors having smaller end surfaces connected to the first conductor layer, and a second build-up layer formed on the core body and including an interlayer and a conductor layer on the interlayer. The first conductor layer is embedded such that the first conductor layer has exposed surface on the surface of the core body, the second conductor layer is formed on the other surface of the core body, and the first conductor layer has wiring pattern having the smallest minimum width of wiring patterns of the conductor layers in the core body and build-up layers.

Abstract: A method for the fabrication of organic electronic devices includes forming a fluoropolymer layer over a first area of a substrate and a first set of organic electronic devices. The first set of organic electronic devices are pre-fabricated on a second area of the substrate. The method further includes selectively removing the formed fluoropolymer layer from areas within the first area of the substrate by using a liquid solvent. The method further includes subsequent fabrication of organic electronic devices on the substrate.

Abstract: A sled for operation in a corresponding rack of a data center includes a chassis-less circuit board substrate having one or more physical resources coupled to a top side of the chassis-less circuit board and one or more memory devices coupled to a bottom side of the chassis-less circuit board. The sled does not include a housing or chassis and is opened to the local environment. In the illustrative embodiments, the sled may be embodied as a compute sled, an accelerator sled, or a storage sled.

Abstract: A multi-layer ceramic capacitor assembly includes a first terminal assembly member formed by arranging first protruded members at specific intervals, a second terminal assembly member formed by arranging second protruded members at specific intervals so that they face the respective first protruded members, insulated heat dissipation members supported by the first protruded members and the second protruded members and disposed therein, and multi-layer ceramic capacitors alternately disposed between the insulated heat dissipation members so that each multi-layer ceramic capacitor comes into contact with one side and the other side of each insulated heat dissipation member in a first direction, the end on one side of the multi-layer ceramic capacitor in a second direction orthogonal to the first direction is connected to the first terminal assembly member, and the end on the other side of the multi-layer ceramic capacitor in the second direction is connected to the second terminal assembly member.

Abstract: A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.

Abstract: A resin multilayer substrate includes a resin structure formed by laminating a plurality of resin layers and disposed components. Built-in components are embedded within the resin structure and a mounted component mounted on a surface of the resin structure. The resin structure includes a flexible part in which a first lamination number of the resin layers are laminated and a rigid part in which a second lamination number of the resin layers is laminated. The second lamination number is larger than the first lamination number. When viewed in a plan view, the flexible part has a shape which is not a rectangle, and a disposed component which is closest to a boundary line between the flexible part and the rigid part is disposed such that a side thereof which is closest to the boundary line is parallel to the boundary line.

Abstract: A substrate includes a first conductive structure, a second conductive structure attached to the first conductive structure and a third conductive structure attached to the second conductive structure. The first conductive structure includes a first dielectric layer and a first circuit layer embedded in the first dielectric layer. The second conductive structure includes at least one second dielectric layer disposed on a second surface of the first dielectric layer and at least one second circuit layer embedded in the second dielectric layer. The third conductive structure includes a third dielectric layer disposed on the second conductive structure and a third circuit layer disposed on the third dielectric layer. A material of the second dielectric layer is different from the a material of the first dielectric layer and a material of the third dielectric layer.

Abstract: A support is provided for attachment to an internal rear-view mirror made from plastic material or lightweight metal for a portable device having a telephone or GPS display screen or for generally electronic, electrical or other devices. The support includes a hooking member shaped to engage with another part of the rear-view mirror, the upper edge thereof, via two hooks, located to either side of a ball pin attaching the rear-view mirror to the windscreen. The hooking member is formed in part from a plurality of links articulated by hinges, in the manner of a metal watch strap. The hooking member is started by a hook-shaped link that secures to the upper edge of the rear-view mirror, followed by a series of links, varying in number, so as to match and constrain the shape of the rear-view mirror, and is finished by two leg feet that form a slide.

Abstract: An electric power sensor includes a sensor pad and an electric terminal. The sensor pad includes a flexible substrate that defines a first surface and a second surface that opposes the first surface. Additionally, the sensor pad includes an electrically-conductive layer applied to the first surface of the flexible substrate. The sensor pad further includes an adhesive layer applied to the second surface of the flexible substrate. The electric terminal is coupled to the electrically-conductive layer of the sensor pad.

Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

Abstract: A method for forming a semiconductor device package substrate including a fiducial mark is provided. The method of forming the package substrate includes forming a dielectric layer over a lower portion of the package substrate. A metal layer is formed over a fiducial region of the package substrate. The metal layer is etched to form a first signal line in the fiducial region. A passivation layer is formed over the first signal line. The passivation layer is etched over the first signal line to form a fiducial mark.

Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.

Abstract: Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits, and other electronic components having, for example, different communication capacities or clock domains. The interface supports communication between any components having any difference in capacity and over any distance. The interface utilizes request and acknowledge phases and signals and an initiator-target relationship between components that allow each side to throttle the communication rate to an accepted level for each component or achieve a desired hit error rate.

Abstract: An apparatus and system for attaining quick response to vibration damping of a printed circuit board (PCB) or other planar surface utilizing a defined travel displacement of a single spherical tungsten (or other material) ball in a single or plurality of sealed spherical chambers in a particle impact damper (PID). The single spherical tungsten (or other material) ball is not weighed down, constrained, encumbered or influenced by other spherical balls within the chamber; accordingly, providing unrestricted freedom for the ball to quickly respond at the first occurrence of excessive vibrational acceleration over 1G. The structure of a single spherical particle within a sealed spherical chamber also provides a path of minimum distance for the ball to travel before colliding with the ceiling or side walls of the PID chamber. A plurality of spherical chambers can be arranged in a variety of patterns within the PID housing such as desired.

Abstract: The present disclosure relates to providing via plugs in vias of a semiconductor material. The via plugs may be formed of a polymer, such as a polyimide, that can withstand subsequent soldering and operating temperatures. The via plugs effectively fill the vias to prevent the vias from being filled substantially with solder during a subsequent soldering processes.

Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors for coupling an integrated circuit die to the interposer to provide a stacked die. The interposer includes a pad coupled to a conductive network of the interposer to dissipate electrostatic charge from the interposer.

Abstract: An adapter assembly is used to attach a module having a mating interposed portion to an attachment member having a mating fixing portion. The adapter assembly comprises a main member having a fixed portion and an interposed portion, a fixing member, a first interposing member having a first interposing portion and a second interposing member having a rotation stopper and a second interposing portion. When the module is attached to the attachment member, the fixed portion is interposed and fixed between the fixing member and the mating fixing portion, and the mating interposed portion is interposed and held between the interposed portion pressed by the first interposing portion and the second interposing portion. During the attachment process of the module, the rotation stopper prevents the second interposing member from being rotated relative to the module.

Abstract: A power semiconductor module having a pressure application body, a circuit carrier, which is embodied with a first conductor track, a power semiconductor element arranged thereon and an internal connecting device, and also having a housing which is embodied with a guide device arranged therein, with a connecting element. The connecting element is embodied as a bolt with first and second end sections and an intermediate section therebetween, wherein the first end section rests on the circuit carrier and is electrically conductively connected thereto; the second end section projects out of the housing through a cutout; and wherein the connecting element is arranged in the assigned guide device. The pressure application body has a first rigid partial body and a second elastic partial body, wherein the second partial body protrudes out of the first partial body in the direction of the housing.

Abstract: An electronic structure is provided with a redistribution structure and the following elements. A first supporting structure has a first opening and is disposed on a first surface of the redistribution structure. A second supporting structure has a second opening and is disposed on a second surface of the redistribution structure opposite to the first surface. A first bonding protruding portions are disposed on the first surface of the redistribution structure and located in the first opening. A second bonding protruding portions are disposed on the second surface of the redistribution structure and located in the second opening. A first encapsulated material is filled between the first opening and the first bonding protruding portions. A second encapsulated material is filled between the second opening and the second bonding protruding portions. An electronic structure array is also provided.

Abstract: The present invention provides a printed circuit board assembly including a substrate having a plurality of conductive layers vertically sandwiched between a first cap-insulation layer and a second cap-insulation layer. The substrate has a first part, a second part and a third part. For protecting the conductive layers from moisture, each of the areas of the conductive layers corresponding to the second part is smaller than the area of the first cap-insulation layer corresponding to the second part for at least a first predetermined percentage, and each of the areas of the conductive layers corresponding to the second part is smaller than the area of the second cap-insulation layer corresponding to the second part for at least the first predetermined percentage.

Abstract: A “universal” substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the substrate material. The pillars extend from a top surface of the substrate material to a bottom surface of the substrate material. A die flag may be formed on the top surface of the substrate material. Pillars underneath the die flag are connected to pillars beyond a perimeter of the die flag with wires. Power and ground rings may be formed by connecting rows of pillars that surround the die flag.

Abstract: Waveguide A waveguide for carrying waves by inductive coupling comprises a plurality of resonant elements, the plurality of resonant elements including a first resonant element; a second resonant element; and a coupling section capacitively coupling the first and second resonant elements, wherein the coupling between the first and second elements produces a first pass-band and a second-pass band, different from the first pass-band, the first pass-band being associated with the resonance of the resonant elements and the second pass-band being associated with resonance of the coupling section.