Abstract: A wiring board includes: a core substrate including: a metal plate having first through holes; a first insulating layer covering an upper surface and a lower surface of the metal plate and inner wall surfaces of the first through holes; through electrodes penetrating the first insulating layer in a thickness direction and each having an upper end surface; a first wiring layer formed on a lower surface of the first insulating layer and connected to the through electrodes; a wiring structure formed on an upper surface of the first insulating layer; and an outermost insulating layer formed on a lower surface of the core substrate. A wiring density of the wiring structure is higher than that of the core substrate. The metal plate is located at a side of the wiring structure with respect to a center of the first insulating layer in a thickness direction thereof.

Abstract: Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs having Embedded Ground Plane (EGP) connections are provided. In one embodiment, the method includes forming a molded panel around an EGP array from which a plurality of preformed EGP connections project. One or more Redistribution Layers (RDLs) are produced over the molded panel. The molded panel is then singulated to yield a plurality of FO-WLPs each including a molded package body containing an EGP from the EGP array and one or more of preformed EGP connections.

Abstract: A wiring substrate includes a first reinforcement pattern stacked on a lower surface of a first insulation layer at a peripheral region located at an outer side of a wiring formation region. A first reinforcement via extends through a second insulation layer in the thickness-wise direction and contacts the first reinforcement pattern. A second reinforcement pattern is stacked on a lower surface of the second insulation layer and connected to the first reinforcement pattern by the first reinforcement via. The first reinforcement via includes a top that partially extends into the first insulation layer.

Abstract: An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed on the first and second surfaces of the circuit structure, respectively, the first circuit layer having a minimum trace width less than that of the second circuit layer; a separation layer formed on the first surface of the circuit structure; a metal layer formed on the separation layer and electrically connected to the first circuit layer; an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and an encapsulant formed on the circuit structure to encapsulate the electronic element. By disposing the electronic element having high I/O function on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package.

Abstract: A semiconductor device with enhanced interposer quality, and method of manufacturing thereof. For example and without limitation, various aspects of the present disclosure provide an interposer die that comprises a first signal distribution structure comprising at least a first dielectric layer and a first conductive layer, wherein the signal distribution structure is protected at lateral edges by a protective layer. Also for example, various aspects of the present disclosure provide a method of manufacturing a semiconductor device comprising such an interposer die.

Abstract: A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

Abstract: A wiring substrate for improving connection reliability with an electronic component, a component embedded substrate that incorporates an embedded component into the wiring substrate, and a package structure including an electronic component mounted on the wiring substrate or the component embedded substrate. The wiring substrate includes a metal plate, and a wiring layer including a plurality of insulating layers and a conductive layer arranged on the plurality of insulating layers arranged on at least one principal surface of the metal plate. The plurality of insulating layers includes a first insulating layer to contact the principal surface of the metal plate and has a larger thermal expansion rate in the planar direction than the metal plate and a second insulating layer which is laminated on the first insulating layer to contact the first insulating layer and has smaller thermal expansion rate in the planar direction than the metal plate.

Abstract: A wiring substrate is provided with a wiring pattern including a pad and a circuit pattern. The pad is formed in a mounting region where an electronic component is mounted, and the circuit pattern extends in a planar direction from the pad. An insulation layer covers a lower surface of the wiring pattern and a side surface of the wiring pattern and partially exposes an upper surface of the wiring pattern. The insulation layer includes a covering portion that continuously covers an entire peripheral portion of the upper surface of the wiring pattern. The insulation layer includes an upper surface located upward from the upper surface of the wiring pattern.

Abstract: A semiconductor device includes a base plate, a semiconductor chip, and a first to a fourth terminal plates. The first terminal plate includes a first main body unit. The second terminal plate includes a second main body unit. The second main body unit opposes the first main body unit. The third terminal plate includes a third main body unit. The third main body unit opposes the first main body unit and the second main body unit. The fourth terminal plate includes a fourth main body unit. The fourth main body unit opposes the third main body unit. A thickness of the third main body unit is thinner than a thickness of the first main body unit. A thickness of the fourth main body unit is thinner than a thickness of the second main body unit.

Abstract: An integrated circuit (IC) structure for radio frequency (RF) circuits having a multi-point selectably grounded die seal and multi-point selectably grounded signal paths. Embodiments include switch-coupled grounding pads that can selectively electrically couple an internal grounding pad within the die seal of an IC die to a connection point on the die seal and/or on a signal path. When the IC die is embedded in a grounded system, the die seal and/or signal path can be locally grounded at selected connection points, and thus an IC die may be “tuned” to mitigate the effects of parasitic coupling and/or to selective repurpose such parasitic coupling to generate a notch filter effect. Another aspect is selective grounding of inactive signal paths to improve isolation between signal ports.

Abstract: A method for bonding components is provided. The method includes preparing a surface of a metal component, applying a film adhesive to the prepared surface, forming a thermoplastic component using injection molding such that the film adhesive is positioned between the metal component and the thermoplastic component, and curing the film adhesive.

Abstract: The printed circuit board for the memory card includes an insulating layer; a mounting unit formed on a first surface of the insulating layer and electrically connected to a memory device; a terminal unit formed on a second surface of the insulating layer and electrically connected to electronic apparatuses of an outside; and metal layers formed at the mounting unit and the terminal unit and made of the same material.

Abstract: An example circuit board structure includes: a substrate; and vias that are electrically conductive and that pass through the substrate to enable electrical connection through the circuit board structure. The substrate is thinner, and lengths of the vias are shorter, in first areas of the circuit board structure that deliver first speed signals than in second areas of the circuit board structure that deliver second speed signals and power. The first speed signals have a shorter rise time than the second speed signals.

Abstract: A substrate for mounting an electronic component includes a base material including insulating resin, a first conductor layer formed on first surface of the material, a second conductor layer formed on second surface of the material, and a metal block inserted into a hole penetrating through the first conductor, material and second conductor such that the metal block is fitted in the hole. The material has a bent portion in contact with the metal block in the hole such that the bent portion is bending toward the second conductor, the metal block has surface on first conductor side such that the surface has an outer peripheral portion having a curved-surface shape, and the hole has a first fitting inlet on the first conductor layer side and a second fitting inlet on second conductor side and that the metal block is positioned in contact with the second fitting inlet.

Abstract: A printed circuit board is provided. The printed circuit board comprises a base substrate comprising a chip mounting region on an upper surface thereof, a plurality of connection pad structures in the chip mounting region, and an extension pattern on the base substrate, spaced from each of two adjacent connection pad structures from among the plurality of connection pad structures, and extending along the two adjacent connection pad structures. Upper surfaces of the plurality of connection pad structures are positioned at a higher level than an upper surface of the extension pattern.

Abstract: In a high frequency signal line, a first signal line extends along a first dielectric element assembly, a first reference ground conductor extends along the first signal line, a second signal line is provided in or on the second dielectric element assembly and extends along the second dielectric element assembly, a second reference ground conductor is provided in or on the second dielectric element assembly and extends along the second signal line. A portion of a bottom surface at an end of the first dielectric element assembly and a portion of the top surface at an end of the second dielectric element assembly are joined together such that a joint portion of the first and second dielectric element assemblies includes a corner. The second signal line and the first signal line are electrically coupled together. The first and second reference ground conductors are electrically coupled together.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a one-layer substrate with a symmetrical structure, the one-layer substrate having a redistribution pad and an insulation, the redistribution pad only at an insulation top side of the insulation; mounting an integrated circuit over the one-layer substrate; and forming an encapsulation over the integrated circuit.

Abstract: Some embodiments include a method. The method can include providing a carrier substrate, providing a release layer over the carrier substrate, and providing a device substrate over the carrier substrate and the release layer. Providing the device substrate can include bonding the device substrate to the carrier substrate, and bonding the device substrate to the release layer. Further, providing the release layer can include bonding the release layer to the carrier substrate. Meanwhile, the release layer can include polymethylmethacrylate, and the device substrate can be bonded to the carrier substrate with a first adhesion strength, the device substrate can be bonded to the release layer with a second adhesion strength less than the first adhesion strength, and the release layer can be bonded to the carrier substrate with a third adhesion strength greater than the second adhesion strength. Other embodiments of related methods and devices are also disclosed.

Abstract: A resin multilayer substrate includes a resin structure formed by laminating a plurality of resin layers and disposed components. Built-in components are embedded within the resin structure and a mounted component mounted on a surface of the resin structure. The resin structure includes a flexible part in which a first lamination number of the resin layers are laminated and a rigid part in which a second lamination number of the resin layers is laminated. The second lamination number is larger than the first lamination number. When viewed in a plan view, the flexible part has a shape which is not a rectangle, and a disposed component which is closest to a boundary line between the flexible part and the rigid part is disposed such that a side thereof which is closest to the boundary line is parallel to the boundary line.

Abstract: The light emitting device is manufactured by processing that includes forming encapsulating member at least on the upper surface and upper surface perimeter of a light emitting element, removing at least the part of the encapsulating member that is on upper surface of the light emitting element and form a cavity with a perimeter that surrounds the light emitting element, and forming a wavelength-conversion layer inside the cavity to convert the wavelength of light emitted from the light emitting element.

Abstract: A relieved component pad for 0201 component use between vias on a tight-pitch Ball Grid Array is disclosed herein. The relieved component pad for 0201 component use between vias provides substantially rectangular component pads having a relieved section at a point of closest approach to a via pad. The relieved component pad for 0201 component use is particularly useful for overcoming the problem of 0201 component placement on tight-pitch arrays known in the art.

Abstract: The present invention is a signal cable for transmitting the signal between the transmitter and the receiver, providing an electrical connection by a connecting part, wherein said connecting portion comprises a layer of graphene disposed on a polymer layer, characterized in that it comprises two conductors, wherein each conductor includes a connecting portion arranged in a protective insulating layer (3) and the coupling portion takes the form of a tape, in which the graphene layer (1) is disposed between two polymer layers (2).

Abstract: In one embodiment, a printed circuit board (PCB) assembly includes a PCB, the PCB being arranged to define a through-hole therein, the through-hole having a surface, wherein the PCB includes a top surface and a bottom surface. The PCB assembly also includes a slug arrangement and a surface mount component. The slug arrangement is formed from an electrically and thermally conductive material and includes at least a first portion and a second portion. At least a part of the first portion is positioned in the through-hole, and the second portion is coupled to the bottom surface. The surface mount component is positioned over the through-hole and the top surface, and has a first surface configured to contact the first portion.

Abstract: A display device includes a panel substrate including a pad region, and a COF (Chip On Film) including a wire region, the wire region including a plurality of wires connected to the pad region of the panel substrate, wherein the plurality of wires in the wire region is arranged into a plurality of sections, intervals between wires within each section being different from intervals between wires within an adjacent section, and at least one of the plurality of sections including a plurality of wires at a fixed interval.

Abstract: A circuit board includes conductive traces being sandwiched by an upper insulating layer and a lower insulating layer, a first array of conductive vias extending perpendicularly to the conductive traces, the vias in the first array of conductive vias being arranged such that any two adjacent vias in a row of vias extending along any given dimension in the first array of conductive vias are equally spaced from each other, and isolation resistors embedded within the first array of conductive vias such that each isolation resistor is disposed between at least two adjacent vias in the first array of conductive vias, each isolation resistor being disposed closer to the conductive via to which the isolation resistor is coupled than all other conductive vias surrounding the isolation resistor.

Abstract: A package substrate includes an inner interlayer, a first conductor layer, a second conductor layer, an outermost interlayer, an outermost conductor layer including first and second pads to mount electronic components, vias including first and second vias such that the first vias are connecting the first conductor layer and first pads and the second vias are connecting the first conductor layer and second pads, and skip vias penetrating through the outermost and inner interlayers such that the skip vias are connecting the outermost and second conductor layers. Sum of insulation distances (t1, t2) is in range of 40 ?m or less to 10 ?m or more, where the insulation distance (t1) is insulation distance between the outermost and first conductor layers and the insulation distance (t2) is insulation distance between the first and second conductor layers, and difference between the insulation distances (t1, t2) is less than 5 ?m.

Abstract: A method for manufacturing a printed wiring board includes forming on carrier a laminate including a second metal foil, a resin layer laminated on the second foil and a first metal foil laminated on the resin layer, irradiating laser upon the first foil such that opening is formed through the first foil and resin layer and exposes surface of the second foil at bottom, plating the first foil such that a via conductor is formed in the opening and a first conductor layer including the first foil and an electroplating film is formed on surface of the resin layer, removing the carrier from the laminate, patterning the first conductor layer on the resin layer, and patterning the second foil such that a second conductor layer including the second foil is formed on opposite surface of the resin layer. The second foil has thickness greater than thickness of the first foil.

Abstract: A system, power supplies, controller and method for enhanced phase current sharing are disclosed. For example, a power supply for enhanced phase current sharing is disclosed, which includes a plurality of power modules, a communication bus coupled to an input of each power module of the plurality power modules, and an output voltage node coupled to a first side of an inductor of each power module of the plurality of power modules, wherein each power module of the plurality of power modules includes a digital controller coupled to the input of the power module, and an RC circuit enabled to generate a feedback signal, coupled to a second side of the inductor and the output voltage node. In some implementations, the power supply is at least part of a power management integrated circuit (PMIC) or at least part of a power supply formed on a semiconductor IC, wafer, chip or die.

Abstract: A circuit device has a base plate, a first substrate arranged on a first outer side of the base plate, a second substrate arranged on a second outer side opposite the first outer side of the base plate, at least one electrical connection element that electrically connects the first substrate and the second substrate, at least one electronic component arranged on or in the first substrate, at least one electronic component arranged on or in the second substrate, a mold package molded around the two substrates and the electronic components arranged thereon, and at least one contacting element for electrically contacting the first substrate and/or the second substrate. The at least one contacting element is electrically conductively connected to the first substrate and/or the second substrate and is led out from the mold package.

Abstract: A multilayer rigid flexible printed circuit board including a flexible region including a flexible film having a circuit pattern formed on one or both surfaces thereof and a laser blocking layer formed on the circuit pattern and a rigid region formed adjacent to the flexible region and including a plurality of pattern layers on one or both surfaces of extended portions extended to both sides of the flexible film of the flexible region, and a method for manufacturing the same.

Abstract: A radio frequency module includes a plurality of insulating base material layers made of a thermoplastic resin defining a multilayer circuit board and including a cavity inside thereof, an IC chip disposed in the cavity and including a noise generation source, and planar ground conductive bodies provided in the multilayer circuit board. The planar ground conductive bodies are disposed on a layer not exposed to the inner surface of the cavity, and include inter-layer connection conductive bodies protruding in the direction of the noise generation source from the planar ground conductive bodies.

Abstract: According to one embodiment, a method of forming a pattern includes preparing a substrate having a liquid-repellent face and a lyophilic pattern which are located adjacent to each other on a surface of the substrate, the lyophilic pattern having a surface energy different from the liquid-repellent face, bringing ink into contact with the substrate, and applying the ink to the lyophilic pattern by moving a contacted ink surface. The lyophilic pattern includes a linear main lyophilic pattern and an auxiliary lyophilic pattern connected to the lyophilic pattern. A liquid-repellent region is defined in the liquid-repellent face between the main lyophilic pattern and the auxiliary lyophilic pattern.

Abstract: A method for preparing film patterns; firstly, a complementary film pattern (1) to a desired film pattern (201) is prepared on a substrate (3) with an erasable agent; secondly, a whole layer of film (2) is formed on the complementary film pattern (1); and thirdly, the desired film pattern (201) is obtained by removing the complementary film pattern (1). The preparation method can simplify the production process and reduce the production cost of the film patterns.

Abstract: In order to limit the stress and strain applied to a printed circuit board while still maintaining flexibility, a flexible section of the printed circuit board is configured to have a non-linear portion that functions as a hinge when the flexible section is bent, flexed, twisted or otherwise subjected to a motion related force. The hinge configuration improves durability and flexibility while minimizing ripping and cracking of the printed circuit board, particularly interconnects within the flexible section and a transition region between the flexible section and a rigid section of the printed circuit board. The hinge is configured to have a non-linear shape, such as a serpentine or circuitous path that can include curved portions, different linear portions or some combination of curved and linear portions.

Abstract: A method and apparatus for fabricating a carrier having a top surface and a bottom surface, the method comprising combining a conductive portion at the top surface and a dielectric at the bottom surface, wherein the dielectric includes contact island cavities, filling one or more of the contact island cavities with solder metal to form solder islands, selectively metal plating the conductive portion, selectively etching a portion of the conductive portion, and applying solder resist to the selectively plated and etched top surface of said conductive portion.

Abstract: A semiconductor structure is provided. The semiconductor structure includes an electronic component and a board structure. The board structure includes a dielectric layer structure and at least one elastomer. The dielectric layer structure has a mount region and a peripheral region surrounding the mount region. The electronic component is disposed on the mount region, and the peripheral region has at least one first through hole. The elastomer is disposed in the first through hole.

Abstract: A wired circuit board includes a first insulating layer, a conductive pattern disposed on the first insulating layer and including a plurality of terminals arranged in parallel to be spaced apart from each other, and a second insulating layer disposed on the first insulating layer so as to cover the conductive pattern. Each of the terminals includes a main body portion and a protruding portion protruding from the main body portion and having a dimension in a parallel arrangement direction of the terminals which is shorter than a dimension of the main body portion thereof. The second insulating layer includes a plurality of end-portion covering portions disposed individually on both end portions of the main body portion in the parallel arrangement direction and exposing a middle portion of the main body portion and the protruding portion.

Abstract: The present invention discloses a ceramic insulator for electronic packaging and a method for fabricating the same, and relates to a technical field of outer shell packaging of electronic devices. Under the circumstance of using neither a chemical coating nor any bonding wire connection circuit, through a design that builds a electroplated circuit into the ceramic insulator, the method accomplishes coating of a nickel alloy protection layer onto a porcelain by an electroplating method, so that not only quality of a coating layer but also requirement of a complete appearance can be ensured. All circuits of the ceramic insulator fabricated by the aforesaid method can conduct with external circuits, such that the electroplating method can be used to accomplish coating of the nickel alloy layer, after accomplishment of all metal coating, metallization parts on an end surface of the porcelain is removed.

Abstract: A printed wiring board includes a first resin insulating layer, a first conductor pattern including first mounting pads formed on the first resin insulating layer, and a wiring structure positioned on the first resin insulating layer and including a second resin insulating layer and a second conductor pattern such that the second resin insulating layer and second conductor pattern are positioned adjacent to the first conductor pattern and that the second conductor pattern includes second mounting pads. The second mounting pads are embedded in the second resin insulating layer such that the second mounting pads have mounting surfaces exposed on an exposed surface of the second resin insulating layer, and the first mounting pads have mounting surfaces such that the mounting surfaces of the first and second mounting pads are formed on a same plane.

Abstract: A printed circuit board and a method of manufacturing the same is provided. The printed circuit board includes an insulating substrate, a circuit disposed on the insulating substrate, a pair of first reinforcements spatially separated in the insulating substrate, the first reinforcements extending parallel to a surface of the insulating substrate, and a second reinforcement configured to connect the pair of first reinforcements.

Abstract: A manufacturing method is used for a current sensor including a current measurement circuit configured to include magnetoelectric conversion elements, a first amplification-and-correction circuit configured to amplify an output of the current measurement circuit and correct, based on a set first correction amount, a temperature characteristic of an offset, a second amplification-and-correction circuit configured to amplify an output of the first amplification-and-correction circuit, adjust a sensitivity, and correct, based on a set second correction amount, a magnitude of the offset, and a substrate in which the current measurement circuit, the first amplification-and-correction circuit, and the second amplification-and-correction circuit are provided, wherein after the first correction amount is set based on characteristics of the magnetoelectric conversion elements, the magnetoelectric conversion elements are mounted in the substrate and the second correction amount is set.

Abstract: An electronic device, suitable for achieving a smaller size, includes a semiconductor substrate having a main surface and a back surface opposite to the main surface, a main electronic element arranged on the substrate, and a conducting layer electrically connected to the main electronic element. The substrate is formed with an element arrangement recessed portion that is recessed from the main surface and in which the main electronic element is arranged. The element arrangement recessed portion has a bottom surface facing in the thickness direction, and a side surface inclined with respect to the thickness direction of the substrate. The electronic device includes an auxiliary electronic element formed on the side surface of the element arrangement recessed portion.

Abstract: A multi-layer wiring board that has stacked therein a first printed wiring bases on at least one surface of which a wiring pattern is formed and in which a conductive paste via is formed, that includes an electronic component terminal and a board terminal whose terminal pitch differs from that of the electronic component terminal, and that has an electronic component installed thereon via the electronic component terminal, wherein a second wiring base whose wiring pitch is smaller than that of the first wiring base is built in to a lower portion of an installing portion of the electronic component via the first wiring base, and the second wiring base is connected to the electronic component terminal via the conductive paste via of the first wiring base, has formed on both surfaces thereof a pattern that enlarges the terminal pitch from the electronic component terminal to the board terminal, and includes a via that connects the pattern of the both surfaces.

Abstract: A method and apparatus for matching the lengths of traces of differential signal pairs. The method includes determining that a first trace is longer than a second trace and modifying the second trace so that the length is substantially equal to the length of the first trace. In some implementations, the second trace can be modified by replacing one or more sections of the trace with two line segments that are substantially equal in length and meet at a vertex that is less than 180 degrees.

Abstract: A stack structure of a high frequency printed circuit, mainly includes a transmission conductor pin group in a form of single row, where each signal pair and each transmission pair of the transmission conductor pin group respectively have a through hole portion thereon, and the inner layer of the circuit board has a trace portion in electric connection with the through hole portion, allowing each four terminals to be formed into one group. Utilizing the clever arrangement of the through hole portions and trace portions separates each terminal properly, thereby increasing the property of transmitted signals, and, at the same time, reducing noise interferences such as EMI and RFI.

Abstract: A wiring substrate includes a first insulation layer, a first wiring layer formed on the first insulation layer, and a second insulation layer stacked on the first insulation layer. The second insulation layer covers the first insulation layer and includes a filler. A third insulation layer is stacked on the second insulation layer. The third insulation layer is filler-free. A through electrode extends through the second and third insulation layers in a thicknesswise direction. A second wiring layer is stacked on the third insulation layer and the through electrode. The through electrode electrically connects the second wiring layer to the first wiring layer.

Abstract: In a ceramic multilayer substrate including a ceramic laminate including ceramic layers, a surface electrode located on a surface of the ceramic laminate, and a cover ceramic layer that covers a peripheral portion of the surface electrode, a recess portion is provided in a peripheral portion of a surface electrode to extend along the periphery thereof, and the peripheral portion of the surface electrode includes a peripheral end portion thereof and a region in which the recess portion is covered with a cover ceramic layer. A height of a central portion of the surface electrode which is not covered with the cover ceramic layer is lower than a height of a primary surface of the ceramic laminate on which the surface electrode is located.

Abstract: A printed circuit board having two completed printed circuit board elements which consists of a plurality of interconnected plies or layers, wherein at least one printed circuit board element has a cutout or depression containing the component to be integrated on one of the printed circuit board elements or in the cutout of the at least one printed circuit board element, and the printed circuit board elements are connected with the component being accommodated in the cutout, as a result of which it is possible to obtain secure and reliable accommodation of the component in the printed circuit board. Furthermore, a printed circuit board of this type also contains an electronic component integrated therein.

Abstract: An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide multiple LED dies that are joined to a single carrier die. The multiple LED dies on the single carrier die are connected in series and/or in parallel by interconnection in the LED dies and/or in the single carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area. Related devices and fabrication methods are described.

Abstract: An inductor bridge is provided with a flexible flat plate-shaped element body, a first connector, and a second connector. The element body includes therein an inductor portion. The inductor portion is configured by a spiral conductor pattern. The first connector is provided on the element body and is connected to a first circuit. The second connector is provided on the element body and is connected to a second circuit.