With Sputter Etching Patents (Class 204/192.3)
  • Patent number: 7820020
    Abstract: A method of performing physical vapor deposition of copper onto an integrated circuit in a vacuum chamber of a plasma reactor includes providing a copper target near a ceiling of the chamber, placing an integrated circuit wafer on a wafer support pedestal facing the target near a floor of the chamber, introducing a carrier gas into the vacuum chamber having an atomic weight substantially less than the atomic weight of copper, maintaining a target-sputtering plasma at the target to produce a stream comprising at least one of copper atoms and copper ions flowing from the target toward the wafer support pedestal for vapor deposition, maintaining a wafer-sputtering plasma near the wafer support pedestal by capacitively coupling plasma RF source power to the wafer-sputtering plasma, and accelerating copper ions of the wafer sputtering plasma in a direction normal to a surface of the wafer support pedestal.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: October 26, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Karl M. Brown, John Pipitone, Vineet Mehta, Ralf Hofmann
  • Publication number: 20100155223
    Abstract: A multi-step process performed in a plasma sputter chamber including sputter deposition from the target and argon sputter etching of the substrate. The chamber includes a quadruple electromagnetic coil array coaxially arranged in a rectangular array about a chamber axis outside the sidewalls of a plasma sputter reactor in back of an RF coil within the chamber. The coil currents can be separately controlled to produce different magnetic field distributions, for example, between a sputter deposition mode in which the sputter target is powered to sputter target material onto a wafer and a sputter etch mode in which the RF coil supports the argon sputtering plasma. A TaN/Ta barrier is first sputter deposited with high target power and wafer bias. Argon etching is performed with even higher wafer bias. A flash step is applied with reduced target power and wafer bias.
    Type: Application
    Filed: January 28, 2010
    Publication date: June 24, 2010
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Tza-Jing GUNG, Xinyu FU, Arvind SUNDARRAJAN, Edward P. HAMMOND, IV, Praburam GOPALRAJA, John C. FORSTER, Mark A. PERRIN, Andrew S. GILLARD
  • Patent number: 7700484
    Abstract: An iPVD system is programmed to deposit uniform material, such as a metallic material, into high aspect ratio nano-sized features on semiconductor substrates using a process that enhances the feature filling compared to the field deposition, while maximizing the size of the grain features in the deposited material opening at the top of the feature during the process. Sequential deposition and etching are provided by controlling DC and high density power levels and other parameters.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: April 20, 2010
    Assignee: Tokyo Electron Limited
    Inventor: Frank M. Cerio, Jr.
  • Publication number: 20100089620
    Abstract: An electronic component module comprising: at least one multilayer ceramic circuit carrier (2, 3); at least one cooling device comprising at least one heat sink; a composite layer (5, 6) arranged at least in regions between the ceramic circuit carrier (2, 3) and the cooling device (4), said composite layer being formed for reactive connection to the ceramic circuit carrier (2, 3) during a primary process and for connection to the cooling device (4).
    Type: Application
    Filed: November 30, 2006
    Publication date: April 15, 2010
    Inventors: Richard Matz, Ruth Männer, Steffen Walter
  • Publication number: 20100078314
    Abstract: The present disclosure includes a method of producing a fuel system component. The method includes providing a substrate and a coating, wherein the substrate comprises steel and the coating comprises a metal nitride. The method also includes applying the coating to at least part of the substrate using a magnetron sputtering deposition process substantially conducted at a temperature less than about 200° C.
    Type: Application
    Filed: December 7, 2009
    Publication date: April 1, 2010
    Inventors: Steven C. TAYLOR, Bao Feng, Lucy V. Davies, Jeffrey P. Werwe
  • Patent number: 7686926
    Abstract: A multi-step process performed in a plasma sputter chamber including sputter deposition from the target and argon sputter etching of the substrate. The chamber includes a quadruple electromagnetic coil array coaxially arranged in a rectangular array about a chamber axis outside the sidewalls of a plasma sputter reactor in back of an RF coil within the chamber. The coil currents can be separately controlled to produce different magnetic field distributions, for example, between a sputter deposition mode in which the sputter target is powered to sputter target material onto a wafer and a sputter etch mode in which the RF coil supports the argon sputtering plasma. A TaN/Ta barrier is first sputter deposited with high target power and wafer bias. Argon etching is performed with even higher wafer bias. A flash step is applied with reduced target power and wafer bias.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: March 30, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Tza-Jing Gung, Xinyu Fu, Arvind Sundarrajan, Edward P. Hammond, IV, Praburam Gopalraja, John C. Forster, Mark A. Perrin, Andrew S. Gillard
  • Patent number: 7626183
    Abstract: Embodiments of methods of modifying surface features on a workpiece with a gas cluster ion beam are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: December 1, 2009
    Assignee: TEL Epion Inc.
    Inventors: Reinhard Wagner, Wesley Skinner
  • Publication number: 20090272641
    Abstract: In the present invention a sub-stoichiometric ceramic ZnOx:Al target, with 0.3<x<1, is used for depositing a ZnO:Al layer in a reactive sputtering process. The process is carried out in an Ar/O2 atmosphere. The diagram depicts the deposition rate R depending on the oxygen flow in a sputtering process according to the present invention compared with a conventional sputter process using a stoichiometric ZnO target. The upper line x<1 indicates the deposition rate R when using the inventive target and process. The lower line x=1, for comparison only, indicates the deposition rate R when using a stoichiometric ceramic ZnO target. It can be seen from the diagram that both processes are quite stable as there are no steep slopes when varying the oxygen flow. However, the line x<1 is above the line x=1. Therefore, a working point P may be selected which has a higher deposition rate R than a corresponding working point P of a corresponding ceramic target.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 5, 2009
    Applicant: Applied Materials, Inc.
    Inventors: Joachim Mueller, Daniel Severin, Markus Kress
  • Patent number: 7611610
    Abstract: An improved method of controlling topographical variations when milling a cross-section of a structure, which can be used to reduce topographical variation on a cross-section of a write-head in order to improve the accuracy of metrology applications. Topographical variation is reduced by using a protective layer that comprises a material having mill rates at higher incidence angles that closely approximate the mill rates of the structure at those higher incidence angles. Topographical variation can be intentionally introduced by using a protective layer that comprises a material having mill rates at higher incidence angles that do not closely approximate the mill rates of the structure at those higher incidence angles.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: November 3, 2009
    Assignee: Fei Company
    Inventors: James P. Nadeau, Pei Zou, Jason H. Arjavac
  • Publication number: 20090229657
    Abstract: The photovoltaic structure comprises a thin film coating on a transparent substrate, the thin film comprising an effective amount of nanocrystalline silicon embedded in a matrix of amorphous and/or microcrystalline silicon. A transparent conducting oxide layer on a layer of non-conductive transparent oxide provides light-trapping capability as well as electrical conductivity where needed. A chemical vapor deposition (“CVD”) reactor provides improved gas distribution to the substrates being coated in the reactor. An improved sputtering process and an improved RF plasma-enhanced CVD manufacturing method both using high levels of hydrogen in the hydrogen-silane mixture and high electrical power levels for the plasma to increase the speed and to lower the cost of manufacturing.
    Type: Application
    Filed: March 17, 2008
    Publication date: September 17, 2009
    Inventor: Anna Selvan John Appadurai
  • Patent number: 7582490
    Abstract: A method for controlling a gap in an electrically conducting solid state structure provided with a gap. The structure is exposed to a fabrication process environment conditions of which are selected to alter an extent of the gap. During exposure of the structure to the process environment, a voltage bias is applied across the gap. Electron tunneling current across the gap is measured during the process environment exposure and the process environment is controlled during process environment exposure based on tunneling current measurement. A method for controlling the gap between electrically conducting electrodes provided on a support structure. Each electrode has an electrode tip separated from other electrode tips by a gap. The electrodes are exposed to a flux of ions causing transport of material of the electrodes to corresponding electrode tips, locally adding material of the electrodes to electrode tips in the gap.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: September 1, 2009
    Assignee: President and Fellows of Harvard College
    Inventors: Jene A. Golovchenko, Gregor M. Schürmann, Gavin M. King, Daniel Branton
  • Patent number: 7550749
    Abstract: Embodiments of an apparatus and methods for offsetting systematic non-uniformities using a gas cluster ion beam are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: June 23, 2009
    Assignee: TEL Epion Inc.
    Inventors: Steve Caliendo, Nicholas J. Hofmeester
  • Patent number: 7550748
    Abstract: Embodiments of an apparatus and methods for correcting systematic non-uniformities using a gas cluster ion beam are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: June 23, 2009
    Assignee: TEL Epion, Inc.
    Inventors: Steve Caliendo, Nicholas J. Hofmeester
  • Patent number: 7541597
    Abstract: The invention relates to the automatic cleaning of ion sources inside mass spectrometers, especially the cleaning of ion sources where the ions are generated by matrix-assisted laser desorption (MALDI). The invention consists in cleaning the electrodes of the ion source, which are contaminated with organic material, in the mass spectrometer itself by etching with reactive ions produced by an electrically generated gas discharge in a specially admitted reactant gas.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: June 2, 2009
    Assignee: Bruker Daltonik, GmbH
    Inventors: Armin Holle, Gregor Przybyla
  • Publication number: 20090127095
    Abstract: A method of the present invention for forming fine particles includes forming fine particles on a substrate by supplying, in the presence of inert gas, to the substrate, atoms or molecules of a supply material capable of being combined with a material constituting a surface of the substrate to produce a compound, the atoms or the molecules being supplied from a supply source. The supply source is positioned in such a manner as not to be directly connected by a line with the surface of the substrate where the fine particles are to be formed, and a high-frequency voltage varying positively and negatively, ranging from 100 kHz to 100 MHz, is applied to at least one of the substrate and a substrate supporter for supporting the substrate. This realizes a method for forming fine particles that allows forming highly uniformed magnetic fine particles with a periodic pattern through a simple process at a time.
    Type: Application
    Filed: November 13, 2008
    Publication date: May 21, 2009
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Noboru Iwata, Yoshiteru Murakami
  • Patent number: 7504006
    Abstract: A DC magnetron sputter reactor for sputtering deposition materials such as tantalum and tantalum nitride, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and capacitively coupled plasma (CCP) sputtering are promoted, either together or alternately, in the same chamber. Also, bottom coverage may be thinned or eliminated by inductively-coupled plasma (ICP) resputtering. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. CCP is provided by a pedestal electrode which capacitively couples RF energy into a plasma. The CCP plasma is preferably enhanced by a magnetic field generated by electromagnetic coils surrounding the pedestal which act to confine the CCP plasma and increase its density.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: March 17, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Praburam Gopalraja, Jianming Fu, Xianmin Tang, John C. Forster, Umesh Kelkar
  • Publication number: 20090011217
    Abstract: The invention relates to a method for applying a porous glass layer. It is proposed to apply a porous glass layer by means of a PVD method. Porosity factor and average pore size can be varied by means of the process parameters such as pressure and deposition rate, as well as by deliberate addition of extrinsic substances.
    Type: Application
    Filed: September 14, 2006
    Publication date: January 8, 2009
    Applicant: SCHOTT AG
    Inventors: Clemens Ottermann, Joern Pommerehne
  • Patent number: 7427568
    Abstract: A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: September 23, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Liang-Yuh Chen, Daniel A. Carl, Israel Beinglass
  • Patent number: 7410590
    Abstract: A method for mounting the micro spring structures onto cables or contact structures includes forming a spring island having an “upside-down” stress bias on a first release material layer or directly on a substrate, forming a second release material over at least a portion of the spring island, and then forming a base structure over the second release material layer. The micro spring structure is then transferred in an unreleased state, inverted such that the base structure contacts a surface of a selected apparatus, and then secured (e.g., using solder reflow techniques) such that the micro spring structure becomes attached to the apparatus. The spring structure is then released by etching or otherwise removing the release material layer(s).
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: August 12, 2008
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Koenraad F. Van Schuylenbergh, Thomas Hantschel
  • Patent number: 7404879
    Abstract: Provided is an ionized physical vapor deposition (IPVD) apparatus having a helical self-resonant coil. The IPVD apparatus comprises a process chamber having a substrate holder that supports a substrate to be processed, a deposition material source that supplies a material to be deposited on the substrate into the process chamber, facing the substrate holder, a gas injection unit to inject a process gas into the process chamber, a bias power source that applies a bias potential to the substrate holder, a helical self-resonant coil that produces plasma for ionization of the deposition material in the process chamber, one end of the helical self-resonant coil being grounded and the other end being electrically open, and an RF generator to supply an RF power to the helical self-resonant coil. The use of a helical self-resonant coil enables the IPVD apparatus to ignite and operate at very low chamber pressure such as approximately 0.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: July 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yuri Nikolaevich Tolmachev, Dong-joon Ma, Sergiy Yakovlevich Navala, Dae-il Kim
  • Patent number: 7399388
    Abstract: A method of depositing a silica glass insulating film over a substrate. In one embodiment the method comprises exposing the substrate to a silicon-containing reactant introduced into a chamber in which the substrate is disposed such that one or more layers of the silicon-containing reactant are adsorbed onto the substrate; purging or evacuating the chamber of the silicon-containing reactant; converting the silicon-containing reactant into a silica glass insulating compound by exposing the substrate to oxygen radicals formed from a second reactant while biasing the substrate to promote a sputtering effect, wherein an average atomic mass of all atomic constituents in the second reactant is less than or equal to an average atomic mass of oxygen; and repeating the exposing, purging/evacuating and exposing sequence a plurality of times until a desired film thickness is reached.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: July 15, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Farhad K. Moghadam, Michael S. Cox, Padmanabhan Krishnaraj, Thanh N. Pham
  • Patent number: 7399539
    Abstract: A magneto-optic recording medium has a stacked structure composed of a memory layer, a domain wall displacement layer having domain wall-resistant magnetism smaller than the memory layer, and a switching layer having a lower Curie temperature than these layers interposed between these layers. A recording surface of the magneto-optic recording medium is divided into a plurality of tracks of a predetermined track pitch. A domain wall displacement layer has a recording track region limited in a track width direction in a central portion of each track. A magnetized state of a vertically magnetized memory layer is only transferred in the recording track region. A buffer region is magnetically oriented in an in-plane direction at a predetermined temperature or lower and is vertically magnetized at the predetermined temperature or higher.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: July 15, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tsutomu Shiratori
  • Patent number: 7338581
    Abstract: A sputtering apparatus includes paired targets 31 disposed in a vacuum chamber 30, substrate holder 33 disposed at a position nearly perpendicular to the paired target 31 and apart from a space formed by the paired targets 31, a plasma source 37 for generating reaction plasma by after-glow plasma in the vicinity of the substrate holder 33, and a lead-in pipe 38 which connects the plasma source 37 to the vacuum chamber 30. Since reaction plasma of after-glow plasma can be produced in the vicinity of the substrate holder 33, it is possible to form a thin film of compound close to bulk characteristics at a low substrate temperature without the film being damaged by plasma.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: March 4, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toshinari Noda
  • Patent number: 7300684
    Abstract: The coating of internal surfaces of a workpiece is achieved by connecting a bias voltage such that the workpiece functions as a cathode and by connecting an anode at each opening of the workpiece. A source gas is introduced at an entrance opening, while a vacuum source is connected at an exit opening. Pressure within the workpiece is monitored and the resulting pressure information is used for maintaining a condition that exhibits the hollow cathode effect. Optionally, a pre-cleaning may be provided by introducing a hydrocarbon mixture and applying a negative bias to the workpiece, so as to sputter contaminants from the workpiece using argon gas. Argon gas may also be introduced during the coating processing to re-sputter the coating, thereby improving uniformity along the length of the workpiece. The coating may be a diamond-like carbon material having properties which are determined by controlling ion bombardment energy.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: November 27, 2007
    Assignee: Sub-One Technology, Inc.
    Inventors: William John Boardman, Andrew William Tudhope, Raul Donate Mercado
  • Patent number: 7229533
    Abstract: A coated article is provided that may be used as a vehicle windshield, insulating glass (IG) window unit, or the like. An ion beam is used during at least part of forming an infrared (IR) reflecting layer(s) of such a coated article. Advantageously, this has been found to improve sheet resistance (Rs) properties, solar control properties, and/or durability of the coated article. Other layers may also be ion beam treated in certain example embodiments.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: June 12, 2007
    Assignee: Guardian Industries Corp.
    Inventor: Vijayen S. Veerasamy
  • Patent number: 7144520
    Abstract: An etching apparatus comprises a workpiece holder (21) for holding a workpiece (X), a plasma generator (10, 20) for generating a plasma (30) in a vacuum chamber (3), an orifice electrode (4) disposed between the workpiece holder (21) and the plasma generator (10, 20), and a grid electrode (5) disposed upstream of the orifice electrode (4) in the vacuum chamber (3). The orifice electrode (4) has orifices (4a) defined therein. The etching apparatus further comprises a voltage applying unit (25, 26) for applying a voltage between the orifice electrode (4) and the grid electrode (5) to accelerate ions from the plasma (30) generated by the plasma generator (10, 20) and to pass the extracted ions through the orifices (4a) in the orifice electrode (4). A first collimated neutral particle beam is generated and applied to the workpiece (X) for etching a surface of a processing layer (60) of the workpiece (X).
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: December 5, 2006
    Assignees: Ebara Corporation, Japan as Represented by President of Tohoku University
    Inventors: Katsunori Ichiki, Kazuo Yamauchi, Hirokuni Hiyama, Seiji Samukawa
  • Patent number: 7118657
    Abstract: For controlling a physical dimension of a solid state structural feature, a solid state structure is provided, having a surface and having a structural feature. The structure is exposed to a first periodic flux of ions having a first exposure duty cycle characterized by a first ion exposure duration and a first nonexposure duration for the first duty cycle, and then at a second periodic flux of ions having a second exposure duty cycle characterized by a second ion exposure duration and a second nonexposure duration that is greater than the first nonexposure duration, for the second duty cycle, to cause transport, within the structure including the structure surface, of material of the structure to the structural feature in response to the ion flux exposure to change at least one physical dimension of the feature substantially by locally adding material of the structure to the feature.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: October 10, 2006
    Assignee: President and Fellows of Harvard College
    Inventors: Jene A. Golovchenko, Derek M. Stein, Jiali Li
  • Patent number: 7081186
    Abstract: A PVD process for coating substrates, wherein the substrate is pre-treated in the vapor of a pulsed, magnetic field-assisted cathode sputtering operation, and during pre-treatment a magnetic field arrangement of the magnetron cathode type, with a strength of the horizontal component in front of the target of 100 to 1500 Gauss, is used for magnetic field-assistance, and after pre-treatment further coating is effected by means of cathode sputtering and the power density of the pulsed discharge during pre-treatment is greater than 1000 W.cm?2.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: July 25, 2006
    Assignee: Sheffield Hallam University
    Inventors: Arutiun Papken Ehiasarian, Papken Ehiasar Hovsepian, Wolf-Dieter Munz
  • Patent number: 7048837
    Abstract: Plasma etching or resputtering of a layer of sputtered materials including opaque metal conductor materials may be controlled in a sputter reactor system. In one embodiment, resputtering of a sputter deposited layer is performed after material has been sputtered deposited and while additional material is being sputter deposited onto a substrate. A path positioned within a chamber of the system directs light or other radiation emitted by the plasma to a chamber window or other optical view-port which is protected by a shield against deposition by the conductor material. In one embodiment, the radiation path is folded to reflect plasma light around the chamber shield and through the window to a detector positioned outside the chamber window.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: May 23, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Sasson R. Somekh, Marc O. Schweitzer, John C. Forster, Zheng Xu, Roderick C. Mosely, Barry L. Chin, Howard E. Grunes
  • Patent number: 6991709
    Abstract: A multi-step sputtering process in plasma sputter reactor having target and magnetron operable in two modes, for example, in a substrate sputter etch and a substrate sputter deposition. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. An integrated copper via filling process with the inventive reactor or other reactor includes a first step of highly ionized sputter deposition of copper, which can optionally be used to remove the barrier layer at the bottom of the via, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and a third step of electroplating copper into the hole to complete the metallization. The first two steps can be also used with barrier metals.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: January 31, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Praburam Gopalraja, Jianming Fu, Fusen Chen, Girish Dixit, Zheng Xu, Wei Wang, Ashok K. Sinha
  • Patent number: 6979388
    Abstract: A method of influencing variations in composition of thin films is described. The elemental plasma field distribution in sputtering systems is manipulated by generating a nonuniform electric field along a surface of the substrate to alter the composition by differentially re-sputtering the target elements. The nonuniform electric field is used to modulate the kinetic energy of the ions generated in the plasma which strike the thin film's surface. By applying varying electric potentials at a plurality of points on a conductive surface of a substrate, the electric field across the surface of the substrate can be modulated in a variety of patterns. In the preferred embodiment a radial voltage gradient is applied to a conductive surface of a disk on which a magnetic thin film is being formed to radially modulate the platinum content of the magnetic film.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: December 27, 2005
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Ernesto E. Marinero, Timothy Martin Reith, Hal Jerves Rosen, Brian R. York
  • Patent number: 6958112
    Abstract: Methods and systems are provided for depositing silicon oxide in a gap on a substrate. The silicon oxide is formed by flowing a process gas into a process chamber and forming a plasma having an overall ion density of at least 1011 ions/cm3. The process gas includes H2, a silicon source, and an oxidizing gas reactant, and deposition into the gap is achieved using a process that has simultaneous deposition and sputtering components. The probability of forming a void is reduced by ensuring that the plasma has a greater density of ions having a single oxygen atom than a density of ions having more than one oxygen atom.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: October 25, 2005
    Assignee: Applied Materials, Inc.
    Inventors: M. Ziaul Karim, Farhad K. Moghadam, Siamak Salimian
  • Patent number: 6929720
    Abstract: A plasma processing system is provided with a cylindrical target, open at both ends, and with a magnet array that forms a hollow cathode magnetron (HCM). At one of the open ends is placed an inductively coupled RF energy source. A dielectric window at one end of the cylindrical target forms a seal between atmosphere and the processing system. A deposition baffle shield permits the coupling of RF energy from the coil into the chamber. The open end of the cylindrical target opposite the RF source faces the processing space. Magnetron magnets produce a magnetic trapping field having a null which acts as a mirror and separates a plasma-source from the processing space.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: August 16, 2005
    Assignee: Tokyo Electron Limited
    Inventor: Glyn Jeremy Reynolds
  • Patent number: 6884329
    Abstract: A method of filling copper into a high-aspect ratio via by a plasma sputter process and allowing the elimination of electrochemical plating. In one aspect of the invention, the sputtering is divided into a first step performed at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole, and a second step performed at a higher temperature, e.g., at least 200° C. and with at least portions of low wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma. In still another aspect, copper sputtering, even in the final fill phase, is performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter from the corners.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: April 26, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Wei D. Wang, Anantha K. Subramani, Jianming Fu, Praburam Gopalraja, Jick M. Yu, Fusen Chen
  • Patent number: 6872289
    Abstract: A thin film is fabricated while causing ions in a plasma P to be incident by effecting biasing relative to the space potential of the plasma P by imparting a set potential to the surface of a substrate 9. A bias system 6 causes the substrate surface potential Vs to vary in pulse form by imposing an electrode imposed voltage Ve in pulse form on a bias electrode 23 which is in a dielectric block 22. The pulse frequency is lower than the oscillation frequency of ions in the plasma P, and the pulse period T, pulse width t and pulse height h are controlled by a control section 62 in a manner such that the incidence of ions is optimized. The imposed pulses are controlled in a manner such that the substrate surface potential Vs recovers to a floating potential Vf at the end of a pulse period T, and that the ion incidence energy temporarily crosses a thin film sputtering threshold value in a pulse period T.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: March 29, 2005
    Assignee: Anelva Corporation
    Inventors: Shigeru Mizuno, Makoto Satou, Manabu Tagami, Hideki Satou
  • Patent number: 6860975
    Abstract: A barrier layer is deposited on a substrate having a recess by sputtering tantalum in a nitrogen atmosphere. A flow of the nitrogen is selected to deposit mixed phase bcc/?Ta, and sputter ions are sufficiently energetic to cause re-sputtering of deposited material from the base of the recess to its sidewall or sidewalls.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: March 1, 2005
    Assignee: Trikon Technologies Limited
    Inventors: Hilke Donohue, Stephen Robert Burgess
  • Patent number: 6852203
    Abstract: A three-dimensional periodical structure whose period is about 1 ?m or smaller is provided. At least two kinds of films which have two-dimensionally substantially periodical projections are successively formed in layers substantially periodical to construct structure which is substantially three-dimensionally periodical. For instance, the films are made of materials different in refractive index. The three-dimensional periodical structure whose period is about 1 ?m or smaller can be obtained by a simple fabricating method. By this structure, the propagation of a wave with a specific wavelength in many solid angular directions including several axial directions parallel to the plane and the thickness direction of the layers can be cut off.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: February 8, 2005
    Assignee: Autocloning Technology, LTD
    Inventors: Shojiro Kawakami, Hiroyuki Sakaki, Kazuo Shiraishi
  • Publication number: 20040222083
    Abstract: A method for treating a silicon substrate is described. The silicon substrate is placed into a sputtering equipment. A sputtering step is performed to simultaneously dry clean and amorphize the silicon substrate surface by using the sputtering equipment. A titanium film is deposited on the silicon substrate by the sputtering equipment.
    Type: Application
    Filed: January 29, 2004
    Publication date: November 11, 2004
    Inventor: Su-Chen Fan
  • Publication number: 20040222082
    Abstract: In conjunction with sputtering a metal, especially copper, into high aspect-ratio holes in a wafer, an oblique ion milling method in which argon ions or other particles having energies in the range of 200 to 1500 eV are directed to the wafer at between 10 and 35° to the wafer surface to sputter etch material sputter deposited preferentially on the upper corners of the holes. The milling may be performed in the sputter deposition chamber either simultaneously with the deposition or after it or performed afterwards in a separate milling reactor. A plurality of ion sources arranged around the chamber improve angular uniformity or arranged axially improve radial uniformity or vary the angle of incidence. An annular ion source about the chamber axis allows a plasma current loop. Anode layer ion sources and sources composed of copper are advantageous.
    Type: Application
    Filed: May 5, 2003
    Publication date: November 11, 2004
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Praburam Gopalraja, Xianmin Tang, Jianming Fu, Mark A. Perrin, Jean Yue (Phillip) Wang, Arvind Sundarrajan, Hong Zhang, Jick Yu, Umesh Kelkar, Zheng Xu, Fusen Chen
  • Publication number: 20040211661
    Abstract: A method for depositing a barrier or coating layer (34) in a semiconductor recessed structure (28) within a substrate (20) using a plasma process (62) that includes alternating depositing steps (64) and resputtering steps (66). The depositing step (64) deposits a barrier layer (34), including a thick bottom region (38) and a sidewall region (40) along the recessed structure (28) surface. The resputtering step (66) reduces the barrier layer (34) thickness in the bottom region (38) and increases the barrier layer (34) thickness in the otherwise thinly covered portions of the substrate sidewall region (40). Control of powers ranges supplied to the sputtering target (14) and the substrate (20) achieve the depositing and resputtering steps. The process applies also to other coating layers than barrier layers (34), providing a uniform sidewall coverage and thin bottom coverage, e.g., for permalloy deposition in MRAM devices and dual gate electrode formation in CMOS devices.
    Type: Application
    Filed: April 23, 2003
    Publication date: October 28, 2004
    Inventors: Da Zhang, Dean J. Denning, Peter L. G. Ventzek
  • Patent number: 6808606
    Abstract: This invention relates to a method of making a window (e.g., vehicle windshield, architectural window, etc.), and the resulting window product. At least one glass substrate of the window is ion beam treated and/or milled prior to application of a coating (e.g., sputter coated coating) over the treated/milled substrate surface and/or prior to heat treatment. As a result, defects in the resulting window and/or haze may be reduced. The ion beam used in certain embodiments may be diffused. In certain embodiments, the ion beam treating and/or milling is carried out using a fluorine (F) inclusive gas(es) and/or argon/oxygen gas(es) at the ion source(s). In certain optional embodiments, F may be subimplanted into to treated/milled glass surface for the purpose of reducing Na migration to the glass surface during heat treatment or thereafter, thereby enabling corrosion and/or stains to be reduced for long periods of time.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: October 26, 2004
    Assignee: Guardian Industries Corp.
    Inventors: Scott V. Thomsen, Rudolph Hugo Petrmichl, Vijayen S. Veerasamy, Anthony V. Longobardo, Henry A. Luten, David R. Hall, Jr.
  • Patent number: 6802945
    Abstract: A method of forming a device, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer The wafer is placed upon the wafer holder and is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of a metal barrier layer. The exposed portions of the metal barrier layer are etched and removed, exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process which also removes any exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: October 12, 2004
    Assignee: Megic Corporation
    Inventors: Hsien-Tsung Liu, Chien-Kang Chou, Ching-San Lin
  • Patent number: 6800180
    Abstract: An improved apparatus and method for manufacturing semiconductor devices, and, in particular, for depositing material at the bottom of a contact hole, comprises sputtering a material onto a semiconductor substrate; applying a first bias voltage to the substrate, simultaneously removing the material surrounding the contact hole to form a facet at the top of the recess; and applying a second bias voltage to the substrate, simultaneously sputter-depositing the first material onto the bottom of the recess. A further embodiment of the invention utilizes an electrically isolated collimator for the sputtering apparatus. Another embodiment of the invention resputters a first material onto sidewalls of a contact hole during physical vapor deposition.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: October 5, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Shane P. Leiphart
  • Publication number: 20040188239
    Abstract: An iPVD apparatus (20) is programmed to deposit material (10) onto semiconductor substrates (21) by cycling between deposition and etch modes within a vacuum chamber (30). Static magnetic fields are kept to a minimum during at least the etch modes, at least less than 150 Gauss, typically less than 50 Gauss, and preferably in the range of 0-10 Gauss. Static magnetic fields during deposition modes may be more than 150 Gauss, in the range of 0-50 Gauss, or preferably 20-30 Gauss, and may be the same as during etch modes or switched between a higher level during deposition modes and a lower level, including zero, during etch modes. Such switching may be by switching electromagnet current or by moving permanent magnets, by translation or rotation. Static magnetic fields are kept to a minimum during at least the etch modes, at least less than 150 Gauss, typically less than 50 Gauss, and preferably in the range of 1-10 Gauss. The modes may operate at different power and pressure parameters.
    Type: Application
    Filed: March 5, 2004
    Publication date: September 30, 2004
    Inventors: Rodney Lee Robison, Jacques Faquet, Bruce Gittleman, Tugrul Yasar, Frank Cerio, Jozef Brcka
  • Publication number: 20040180216
    Abstract: A coated article is provided which includes a layer including titanium oxycarbide. In order to form the coated article, a layer of titanium oxide is deposited on a substrate by sputtering or the like. After sputtering of the layer including titanium oxide, an ion beam source(s) is used to implant at least carbon ions into the titanium oxide. When implanting, the carbon ions have sufficient ion energy so as to knock off oxygen (O) from TiOx molecules so as to enable a substantially continuous layer comprising titanium oxycarbide to form near a surface of the previously sputtered layer.
    Type: Application
    Filed: March 11, 2003
    Publication date: September 16, 2004
    Inventors: Vijayen S. Veerasamy, Scott V. Thomsen, Rudolph Hugo Petrmichl
  • Patent number: 6787006
    Abstract: A multi-step sputtering process in plasma sputter reactor having target and magnetron operable in two modes, for example, in a substrate sputter etch and a substrate sputter deposition. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. An integrated copper via filling process with the inventive reactor or other reactor includes a first step of highly ionized sputter deposition of copper, which can optionally be used to remove the barrier layer at the bottom of the via, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and a third step of electroplating copper into the hole to complete the metallization. The first two steps can be also used with barrier metals.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: September 7, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Praburam Gopalraja, Jianming Fu, Fusen Chen, Girish Dixit, Zheng Xu, Wei Wang, Ashok K. Sinha
  • Patent number: 6783643
    Abstract: A solid state structure having a surface is provided and exposed to a flux, F, of incident ions under conditions that are selected based on: ∂ ∂ t ⁢ C ⁡ ( r , t ) = F ⁢   ⁢ Y 1 + D ⁢ ∇ 2 ⁢ C - C τ trap - F ⁢   ⁢ C ⁢   ⁢ &sigm
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: August 31, 2004
    Assignee: President and Fellows of Harvard College
    Inventors: Jene A. Golovchenko, Daniel Branton, Michael J. Aziz, Jiali Li, Derek M. Stein, Ciaran J. McMullan
  • Publication number: 20040146661
    Abstract: A method of depositing a silicon oxide layer over a substrate having a trench formed between adjacent raised surfaces. In one embodiment the silicon oxide layer is formed in a multistep process that includes depositing a first portion of layer over the substrate and within the trench by forming a high density plasma process that has simultaneous deposition and sputtering components from a first process gas comprising a silicon source, an oxygen source and helium and/or molecular hydrogen with high D/S ratio, for example, 10-20 and, thereafter, depositing a second portion of the silicon oxide layer over the substrate and within the trench by forming a high density plasma process that has simultaneous deposition and sputtering components from a second process gas comprising a silicon source, an oxygen source and molecular hydrogen with a lower D/S ratio of, for example, 3-10.
    Type: Application
    Filed: January 23, 2003
    Publication date: July 29, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Bikram Kapoor, Ziaul Karim, Anchuan Fremont
  • Patent number: 6767436
    Abstract: A plasma-enhanced coaxial magnetron sputter-cleaning and coating assembly for sputter-cleaning and coating the interior surfaces of a cylindrical workpiece is provided. The apparatus sputter-coats the workpiece using a cylindrical sputtering material, the material having an interior and an exterior. The apparatus includes a core cooling system surrounded by a ring magnet assembly including a plurality of axially aligned ring magnets, with the core cooling system and the ring magnet assembly axially aligned with, and residing in the interior of, the cylindrical sputtering material. A cylindrical-shaped filament circumferentially surrounds the exterior of the cylindrical sputtering material. An anode comprised of a wire screen circumferentially surrounds, and is external to the filament; whereby the apparatus for plasma-enhanced coaxial magnetron sputter-cleaning and coating may be housed inside the workpiece in order to sputter-clean and coat the interior of the workpiece.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: July 27, 2004
    Assignee: HRL Laboratories, LLC
    Inventor: Ronghua Wei
  • Patent number: 6758947
    Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: July 6, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang