With Sputter Etching Patents (Class 204/192.3)
  • Patent number: 6755945
    Abstract: An iPVD apparatus (20) is programmed to deposit material (10) into high aspect ratio submicron features (11) on semiconductor substrates (21) by cycling between deposition and etch modes within a vacuum chamber (30). The modes operate at different power and pressure parameters. Pressure of more than 50 mTorr, for example, is used for sputtering material from a target while pressure of less than a few mTorr, for example, is used to etch. Bias power on the substrate is an order of magnitude higher for etching, producing several hundred volt bias for etching, but only a few tens of volts for deposition. The alternating etching modes remove deposited material that overhangs edges of features on the substrate, removes some of the deposited material from the bottoms (15) of the features, and resputters the removed deposited material onto sidewalls (16) of the features. The substrate (21) is cooled during deposition and etching, and particularly during etching to substantially below 0° C.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: June 29, 2004
    Assignee: Tokyo Electron Limited
    Inventors: Tugrul Yasar, Glyn Reynolds, Frank Cerio, Bruce Gittleman, Michael Grapperhaus, Rodney Robison
  • Patent number: 6743485
    Abstract: A method for treating a silicon substrate is described. The silicon substrate is placed into a sputtering equipment. A sputtering step is performed to simultaneously dry clean and amorphize the silicon substrate surface by using the sputtering equipment. A titanium film is deposited on the silicon substrate by the sputtering equipment.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: June 1, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Su-Chen Fan
  • Patent number: 6740211
    Abstract: This invention relates to a method of making a laminated window such as a vehicle windshield. At least one of the two glass substrates of the window is ion beam milled prior to heat treatment and lamination. As a result, defects in the resulting window and/or haze may be reduced.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: May 25, 2004
    Assignee: Guardian Industries Corp.
    Inventors: Scott V. Thomsen, Rudolph Hugo Petrmichl, Anthony V. Longobardo, Vijayen S. Veerasamy, David R. Hall, Jr., Henry Luten
  • Patent number: 6730605
    Abstract: A method to redistribute solid copper deposited by PVD on a wafer topography. The deposited copper is solubilized in a fluid for redistribution. The copper redistribution prevents inherent nonuniformity of the deposited copper film thickness by improving the uniformity of thickness of the copper film on the covered surfaces, such as vertical and bottom surfaces. The method provides the advantages of good adhesion and good grain growth and orientation that are achieved with copper deposited by PVD, and also provides the good step coverage as achieved with copper deposited by CVD.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: May 4, 2004
    Assignee: Tokyo Electron Limited
    Inventors: Chantal Arena-Foster, Robert F. Foster, Joseph T. Hillman, Thomas J. Licata, Tugrul Yasar
  • Publication number: 20040079632
    Abstract: A method of depositing a film on a substrate disposed in a substrate processing chamber. In one embodiment the method includes depositing a first portion of the film to at partially fill a gap formed between to adjacent features formed on the substrate. The first portion of film is deposited using a high density plasma formed from a first gaseous mixture flown into the process chamber. The film deposition process is then stopped before or shortly after the entry of the gap pinches off and the film is etched to widen entry to the gap using a two step etching process that includes a first physical etch step and a subsequent chemical etch step. The physical etch step sputter etches the first portion of film by forming a plasma from a sputtering agent introduced into the processing chamber and biasing the plasma towards the substrate. After the physical etching step, the film is chemically etched by forming a plasma from a reactive etchant gas introduced into the processing chamber.
    Type: Application
    Filed: October 23, 2002
    Publication date: April 29, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Farhan Ahmad, Michael Awdshiew, Alok Jain, Bikram Kapoor
  • Publication number: 20040060812
    Abstract: A method of controlling intrinsic stress in metal films deposited on a substrate using physical vapor deposition (PVD) techniques is disclosed. The film stress is controlled, by applying a bias power to the substrate during the deposition process. The magnitude of the bias power applied to the substrate modulates the film stress such that as-deposited material layers have an intrinsic stress that may be either tensile or compressive. Also, a reflected bias power may be applied to the substrate during the deposition process, in addition to the bias power. The magnitude of the reflected bias power in combination with the bias power also modulates the film stress such that as-deposited material layers have an intrinsic stress that may be either tensile or compressive.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 1, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Jr-Jyan Chen, Harald Herchen, Kenny King-Tai Ngan
  • Publication number: 20040055870
    Abstract: A plasma-enhanced coaxial magnetron sputter-cleaning and coating assembly for sputter-cleaning and coating the interior surfaces of a cylindrical workpiece is provided. The apparatus sputter-coats the workpiece using a cylindrical sputtering material, the material having an interior and an exterior. The apparatus includes a core cooling system surrounded by a ring magnet assembly including a plurality of axially aligned ring magnets, with the core cooling system and the ring magnet assembly axially aligned with, and residing in the interior of, the cylindrical sputtering material. A cylindrical-shaped filament circumferentially surrounds the exterior of the cylindrical sputtering material. An anode comprised of a wire screen circumferentially surrounds, and is external to the filament; whereby the apparatus for plasma-enhanced coaxial magnetron sputter-cleaning and coating may be housed inside the workpiece in order to sputter-clean and coat the interior of the workpiece.
    Type: Application
    Filed: September 25, 2002
    Publication date: March 25, 2004
    Inventor: Ronghua Wei
  • Patent number: 6709553
    Abstract: A method and apparatus for depositing a film on a substrate comprising a deposition interval wherein DC power is applied to a target to form a first plasma and material is sputtered from the target onto a substrate and, during a subsequent forming interval, high frequency power is applied to the target to remove material from at least a portion of the substrate. The sputtering working gas admitted to the chamber may be maintained at a first pressure during the deposition interval and the pressure of the sputtering working gas may be increased to a second pressure during the forming interval.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: March 23, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Wei Wang, Praburam Gopalraja, Jianming Fu
  • Publication number: 20040050687
    Abstract: The present invention provides a bias sputtering film forming process and film forming apparatus that can form a coating film having a good film thickness distribution in a minute coated surface of a complicated shape, such as contact holes, through-holes and wiring grooves, especially for the sidewall portions thereof.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 18, 2004
    Applicant: ULVAC, INC.
    Inventors: Myounggoo Lee, Yoshihiro Okamura, Kazuyuki Tomizawa, Satoru Toyoda, Narishi Gonohe
  • Publication number: 20040048468
    Abstract: A new method is provided for the creation of damascene copper interconnects. A method is provided whereby created copper surfaces are capped with a layer of barrier material. With the cap structure of barrier material, the surface of the created copper interconnect is shielded against outside influences such as effects of processing chemicals. As a result of the creation of a cap of barrier material, conventional concerns of copper oxidation, copper back-sputtering and the like are eliminated.
    Type: Application
    Filed: September 10, 2002
    Publication date: March 11, 2004
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Wuping Liu, Beichao Zhang, Liang Choo Hsia
  • Publication number: 20040011385
    Abstract: A process for cleaning a glass-coating reactor includes: (a) providing the reactor to be cleaned, wherein the reactor contains a glass substrate within a chamber and the chamber has an internal surface coated with at least one substance selected from the group consisting of Si3N4 or SiO2; (b) terminating a flow of a deposition gas to the reactor; (c) adding to the reactor at least one cleaning gas to react with the at least one substance to form at least one volatile product; and (d) removing from the reactor the at least one volatile product.
    Type: Application
    Filed: July 22, 2002
    Publication date: January 22, 2004
    Inventors: Philip Bruce Henderson, Mario Joseph Moniz, Andrew David Johnson, Eugene Joseph Karwacki,, Richard R. Bodette, Christopher Robert Cording, Herbert David Johnson
  • Patent number: 6652718
    Abstract: A method of depositing thin films comprising Ti and TiN within vias and trenches having high aspect ratio openings of 6:1 is disclosed. The Ti and TiN layers are formed on an integrated circuit substrate using a Ti target in a non-nitrided mode in a hollow cathode magnetron apparatus in combination with an RF biased electrostatic chuck to modulate the properties of the deposited Ti and TiN layers in the same chamber, without the use of a collimator or a shutter. The resulting Ti and TiN layers are superior in step coverage, grain size, grain orientation, roughness and uniformity such that subsequent filling of the high aspect ratio opening is substantially void-free.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: November 25, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Gerard C. D'Couto, George Tkach, Michal Danek
  • Publication number: 20030209433
    Abstract: Disclosed herein is a gas sensor and a method of making a gas sensor comprising disposing a reference electrode on an inner surface of an electrolyte; sputtering a sensing electrode on an outer surface of the electrolyte; sputtering a zirconia layer on a side of the sensing electrode opposite the electrolyte, wherein the zirconia layer has a thickness of about 20 nanometers to about 1 micrometer, and disposing a protective layer on a side of the zirconia layer opposite the sensing electrode.
    Type: Application
    Filed: May 8, 2002
    Publication date: November 13, 2003
    Inventors: William J. LaBarge, Eric J. Detwiler, Paul C. Kikuchi, Richard F. Beckmeyer
  • Patent number: 6646277
    Abstract: A method and apparatus for gas cluster ion beam (GCIB) processing uses X-Y scanning of the workpiece relative to the GCIB. A neutralizer reduces surface charging of the workpiece by the GCIB. A single Faraday cup sensor is used to measure the GCIB current for dosimetry and scanning control and also to measure and control the degree of surface charging that may be induced in the workpiece during processing.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: November 11, 2003
    Assignee: Epion Corporation
    Inventors: Michael E. Mack, Bruce K. Libby
  • Publication number: 20030165632
    Abstract: A method of reducing stress induced defects in a substrate according to an HDP-CVD process including providing a substrate for depositing a layer of material according to an HDP-CVD process; igniting a plasma for carrying out an HDP-CVD process; adjusting plasma operating parameters to achieve a first deposition-sputter ratio with respect to the substrate; depositing a first portion of the layer of material according to a first range of substrate temperatures; and, depositing at least a second portion of the layer of material according to at least a second range of substrate temperatures.
    Type: Application
    Filed: March 1, 2002
    Publication date: September 4, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Sheng Lin, Jui-Hei Huang, Chi-Sheng Lo, Long-Siang Chuang
  • Patent number: 6572933
    Abstract: Process for forming adherent coatings using plasma processing. Plasma Immersion Ion Processing (PIIP) is a process where energetic (hundreds of eV to many tens of keV) metallic and metalloid ions derived from high-vapor-pressure organometallic compounds in a plasma environment are employed to deposit coatings on suitable substrates, which coatings are subsequently relieved of stress using inert ion bombardment, also in a plasma environment, producing thereby strongly adherent coatings having chosen composition, thickness and density. Four processes are utilized: sputter-cleaning, ion implantation, material deposition, and coating stress relief. Targets are placed directly in a plasma and pulse biased to generate a non-line-of-sight deposition without the need for complex fixturing. If the bias is a relatively high negative potential (20 kV-100 kV) ion implantation will result.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: June 3, 2003
    Assignee: The Regents of the University of California
    Inventors: Michael A. Nastasi, Kevin C. Walter, Donald J. Rej
  • Patent number: 6569295
    Abstract: A method is provided for grading the surface topography of a surface to improve step coverage for an overcoat. In accordance with one aspect of the present invention, an ABS of a slider and sensitive element of a magnetic head is graded to provide better step coverage of an overcoat of ultra-thin DLC film. After lapping the ABS, a thin film is deposited on the lapped surface to cover any scratches, irregularities, and steps. The thin film is sputter etched at a glancing angle to grade the topography of the slider ABS. Sputtering at a glancing angle removes the thin film in planar regions faster than the thin film under the shadow of the glancing angle, which is near surface irregularities. The graded surface is then covered by a DLC deposition.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: May 27, 2003
    Assignee: International Business Machines Corporation
    Inventors: Cherngye Hwang, Eun Kyoung Row, Ning Shi
  • Publication number: 20030062254
    Abstract: A method and an apparatus for depositing a metal layer on a substrate use a sputtering technique wherein first sputter particles sputtered from a first target including a metal are deposited on the substrate. A first metal layer portion having a first thickness corresponding to 40 to 60% of the whole deposition thickness is formed on the substrate. Second sputter particles sputtered from a second target including a metal identical to the first target are deposited on the first metal layer portion. Thus, a second metal layer portion including a material identical to the first metal layer portion and having a second thickness corresponding to 40 to 60% of the whole deposition thickness is formed on the first metal layer portion. When depositing the second metal layer portion, a radio frequency bias is applied to a bottom surface of the substrate so that the first and second sputter particles deposited on the substrate are resputtered towards the surface of the substrate.
    Type: Application
    Filed: September 18, 2002
    Publication date: April 3, 2003
    Inventors: Seung-Soo Choi, Seung-Cheol Choi
  • Publication number: 20030059634
    Abstract: A personal ornament having a white coating layer comprises a base article made of a metal, and a white-colored stainless steel coating layer formed by a dry plating process on at least a part of the surface of the base article. Another personal ornament having a white coating layer comprises a base article made of a nonferrous metal, an underlying plating layer formed on the surface of the base article, and a white-colored stainless steel coating layer formed by a dry plating process on at least a part of the surface of the underlying plating layer.
    Type: Application
    Filed: February 26, 2002
    Publication date: March 27, 2003
    Inventors: Koichi Naoi, Akiyoshi Takagi, Yukio Miya, Fumio Tase, Kazumi Hamano
  • Publication number: 20030034244
    Abstract: An iPVD apparatus (20) is programmed to deposit material (10) into high aspect ratio submicron features (11) on semiconductor substrates (21) by cycling between deposition and etch modes within a vacuum chamber (30). The modes operate at different power and pressure parameters. Pressure of more than 50 mTorr, for example, is used for sputtering material from a target while pressure of less than a few mTorr, for example, is used to etch. Bias power on the substrate is an order of magnitude higher for etching, producing several hundred volt bias for etching, but only a few tens of volts for deposition. The alternating etching modes remove deposited material that overhangs edges of features on the substrate, removes some of the deposited material from the bottoms (15) of the features, and resputters the removed deposited material onto sidewalls (16) of the features. The substrate (21) is cooled during deposition and etching, and particularly during etching to substantially below 0° C.
    Type: Application
    Filed: May 3, 2002
    Publication date: February 20, 2003
    Inventors: Tugrul Yasar, Glyn Reynolds, Frank Cerio, Bruce Gittleman, Michael Grapperhaus, Rodney Robison
  • Publication number: 20030027020
    Abstract: The invention relates to a process which is suitable for applying a permanently adhering, stable, dirt and water repellent coating to metallic surfaces, specifically chromium surfaces, specifically sanitary and kitchen fixtures, and also to the components coated in this manner. The process is based on first chemically activating the surface and then coating it by means of a sol.
    Type: Application
    Filed: July 10, 2002
    Publication date: February 6, 2003
    Inventors: Siegfried Berg, Thomas Bolch, Friedrich Auer
  • Patent number: 6491799
    Abstract: The method disclosed herein comprises initially providing a tool comprised of a process chamber, a lid above the process chamber, an RF coil for assisting in generating a plasma in the chamber, a substrate support, and a power supply coupled to the substrate support. The method continues with the step of positioning a substrate in the tool adjacent the substrate support, introducing a noble gas into the chamber, and forming a layer of material above the substrate by sputtering the lid material by performing at least the following steps: applying approximately 200-300 watts of power to the RF coil at a frequency of approximately 400 KHz and applying approximately 20-60 watts of power to the substrate at a frequency of approximately 13.56 MHz.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: December 10, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frederick N. Hause, Karsten Wieczorek, Manfred Horstmann
  • Patent number: 6478933
    Abstract: A process for increasing the lubrication of ductile-iron lubricated contacts includes abrasive-blasting and plasma etching a ductile-iron component prior to coating. A wear resistant or low friction coating is then formed on the iron substrate and the resulting coated component has greater lubrication than a corresponding non-blasted and non-coated component.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: November 12, 2002
    Assignee: Caterpillar Inc.
    Inventors: Chuong Q. Dam, Robert E. Hawbaker
  • Patent number: 6471832
    Abstract: A method of producing a wear-resistant protective film for a thermal head comprises depositing a wear-resistant protective film by sputtering on a thermal head which includes a substrate, and a heat-developing layer and a pair of electrodes formed on either the substrate or a heat-regenerative layer formed thereon. A layer of the wear resistant protective film is formed under a RF larger bias and another layer without a bias or with a smaller bias. Good step coverage is obtained by the RF sputter layer of the wear-resistant and the protective film prevents the intrusion of water that can cause cracking, and the layer formed under no or smaller bias reduces internal stresses and inhibits the development of cracks due to internal stresses as well as the cracking by RF sputtering.
    Type: Grant
    Filed: May 2, 1996
    Date of Patent: October 29, 2002
    Assignee: TDK Corporation
    Inventors: Masatoshi Nakayama, Masahiro Nakano, Tsukimi Endo
  • Patent number: 6468404
    Abstract: A PVD system comprises a hollow cathode magnetron with a capability of producing a high magnetic field for PVD and a low magnetic field for pasting. The high magnetic field is used for PVD and causes an optimal uniform film to form on a substrate but redeposits some metals onto a top portion of a target within the magnetron. The low magnetic field erodes redeposited materials from a top portion of a target within the magnetron.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: October 22, 2002
    Assignee: Novellus Systems, Inc.
    Inventors: Jean Qing Lu, Tom Yu, Jeffrey Tobin
  • Publication number: 20020148720
    Abstract: A method to redistribute solid copper deposited by PVD on a wafer topography. The deposited copper is solubilized in a fluid for redistribution. The copper redistribution prevents inherent nonuniformity of the deposited copper film thickness by improving the uniformity of thickness of the copper film on the covered surfaces, such as vertical and bottom surfaces. The method provides the advantages of good adhesion and good grain growth and orientation that are achieved with copper deposited by PVD, and also provides the good step coverage as achieved with copper deposited by CVD.
    Type: Application
    Filed: April 12, 2001
    Publication date: October 17, 2002
    Applicant: Tokyo Electron Limited
    Inventors: Chantal Arena-Foster, Robert F. Foster, Joseph T. Hillman, Thomas J. Licata, Tugrul Yasar
  • Publication number: 20020134667
    Abstract: A dental or orthopedic implantable prosthetic device (1) which has a bioactive surface of an alloyed layer of material having calcium phosphate compounds. The device is formed by placing a suitable substrate of biocompatible material in a vacuum chamber (10), the substrate is cleaned by ion beam sputtering (18a) and then ion beam sputtering (14a) evolves and deposits (16a) bioactive material onto the surface of the device. The bioactive layer is mixed into the surface forming an alloyed zone by augmenting ion beam (18a) and is grown out to a selected thickness while being continuously bombarded by the augmenting ion beam.
    Type: Application
    Filed: January 11, 2002
    Publication date: September 26, 2002
    Inventors: Thomas D. Driskell, Arnold H. Deutchman
  • Patent number: 6451181
    Abstract: A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: September 17, 2002
    Assignee: Motorola, Inc.
    Inventors: Dean J. Denning, Sam S. Garcia, Bradley P. Smith, Daniel J. Loop, Gregory Norman Hamilton, Md. Rabiul Islam, Brian G. Anthony
  • Patent number: 6440277
    Abstract: An improved method and apparatus for applying discrete area holograms or other optical devices directly onto documents or other substrates in a continuous process analogous to the operation of a printing press. The continuous process is carried out in a vacuum chamber in which at least two process steps are performed in sequence: the formation of a micro-grooved discrete resin area and a localized coating of it with a reflective or refractive material layer. The formation of the micro-grooved resin area can be accomplished by electron beam curing of the resin. The localized coating of the micro-grooved resin can be done by sputtering. One or more other steps, including pre-coating, post-coating and partial removal of the reflective or refractive layer, may also be carried out as part of the continuous process within the vacuum chamber.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: August 27, 2002
    Inventor: Salvatore F. D'Amato
  • Publication number: 20020112951
    Abstract: A method for treating a silicon substrate is described. The silicon substrate is placed into a sputtering equipment. A sputtering step is performed to simultaneously dry clean and amorphize the silicon substrate surface by using the sputtering equipment. A titanium film is deposited on the silicon substrate by the sputtering equipment.
    Type: Application
    Filed: February 11, 2002
    Publication date: August 22, 2002
    Inventor: Su-Chen Fan
  • Patent number: 6428659
    Abstract: A process for coating super fine ion particles of multiple elements on the surface of a micro route substrate includes a coating step operated under low temperatures and vacuums. First, raw micro routers are cleaned by electron beams under atmospheric pressures and room temperatures, then the raw micro routers are transferred into a vacuum environment, and the temperature of the environment is increased to a range between 120° C. to 180° C. Next, the surface of the micro route is cleaned by ions, and then a coating process is started. An arc source is used to bombard cations from a target while a filtration net is used to pass small cation particles. An ion assistant device is operated to further refine the filtered particles so that only super fine ion particles are coated on the surface of the micro route substrates.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: August 6, 2002
    Assignee: Cosmos Vacuum Technology Corporation
    Inventors: Chung-Lin Chou, Chen-Chun Hsu
  • Publication number: 20020084181
    Abstract: The present invention provides a method and apparatus for achieving conformal step coverage on a substrate by PVD. A target provides a source of material to be sputtered by a plasma and then ionized. Ionization is facilitated by maintaining a sufficiently dense plasma using, for example, an inductive coil. The ionized material is then deposited on the substrate which is biased to a negative voltage. A signal provided to the target during processing includes a negative voltage portion and a zero-voltage portion. During the negative voltage portion, ions are attracted to the target to cause sputtering. During the zero-voltage portion, sputtering from the target is terminated while the bias on the substrate cause reverse sputtering therefrom. Accordingly, the negative voltage portion and the zero-voltage portion are alternated to cycle between a sputter step and a reverse sputter step.
    Type: Application
    Filed: November 7, 2001
    Publication date: July 4, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Praburam Gopalraja, Sergio Edelstein, Avi Tepman, Peijun Ding, Debabrata Ghosh, Nirmalya Maity
  • Patent number: 6410101
    Abstract: A method for scrubbing and passivating an anode plate (100) of a field emission display (120) includes the steps of providing a scrubbing passivation material (127); imparting to scrubbing passivation material (127) an energy selected to cause removal of a contamination layer (123, 117) from anode plate (100); causing scrubbing passivation material (127) to be received by contamination layer (123, 117), thereby removing contamination layer (123, 117); and depositing at least a portion of scrubbing passivation material (127) on anode plate (100), thereby forming a passivation layer (129).
    Type: Grant
    Filed: February 16, 2000
    Date of Patent: June 25, 2002
    Assignee: Motorola, Inc.
    Inventors: James E. Jaskie, Albert Alec Talin
  • Publication number: 20020064605
    Abstract: A method of coating a substrate includes the step of forming a chrome layer on the substrate by using a magnetron sputtering device, and the step of forming a chrome nitride layer on the chrome layer by using an arc type ion plating device while maintaining the temperature of the substrate between 100 and 200° C. A vane used for a vane-type compressor, which is subjected to a surface treatment according to the coating method of the present invention is also provided.
    Type: Application
    Filed: May 15, 2001
    Publication date: May 30, 2002
    Inventors: Kiyoharu Hatakenaka, Naoyuki Omori
  • Patent number: 6395148
    Abstract: The invention relates to a method for producing improved tantalum conductive and resistive materials for use in ink jet heater chips. Specifically, a method for producing thin film tantalum layers of a desired phase on a semiconductor substrate comprises depositing protective layers upon the semiconductor substrate; pre-sputter etching the semiconductor substrate; preheating the semiconductor substrate; maintaining the substrate at a predetermined temperature while depositing the thin film tantalum layer by sputtering for a predetermined period of time at a predetermined input power. Use of the method enables production of a desired tantalum phase for use on a semiconductor substrate thereby providing enhanced corrosion and/or cavitation resistance depending on the use of the semiconductor device.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: May 28, 2002
    Assignee: Lexmark International, Inc.
    Inventor: Charles Spencer Whitman
  • Patent number: 6365015
    Abstract: A method of forming a HDPCVD oxide layer over metal lines, the metal lines having gaps between the metal lines having an aspect ratio of two or more. The method comprises the steps of: forming a liner oxide layer over the metal lines; and forming an HDPCVD oxide layer over the liner oxide layer, the formation of the HDPCVD oxide layer being done such that the deposition-to-sputter ratio is increasing as the gaps are being filled.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: April 2, 2002
    Assignee: Wafertech, Inc.
    Inventors: Jessie C. Shan, Chang-Kuei Huang, Steve H. Y. Yang
  • Publication number: 20020025378
    Abstract: A method is disclosed for treating the surface of tools made of tool steel, wherein primary carbides are embedded in the tool steel matrix. The thickness of the primary carbides disposed near the surface can be reduced by forming a surface which has point-wise recess; alternatively, the primary carbides can be completely removed. A hard material layer is deposited on this surface. The invention also describes tools made of tool steel, wherein primary carbides are embedded in the tool steel matrix. The primary carbides are significantly recessed, and a hard material layer is deposited thereon.
    Type: Application
    Filed: August 13, 2001
    Publication date: February 28, 2002
    Inventors: Klaus Keller, Fritz Koch
  • Patent number: 6350353
    Abstract: The present invention provides a method and apparatus for achieving conformal step coverage on a substrate by PVD. A target provides a source of material to be sputtered by a plasma and then ionized. Ionization is facilitated by maintaining a sufficiently dense plasma using, for example, an inductive coil. The ionized material is then deposited on the substrate which is biased to a negative voltage. A signal provided to the target during processing includes a negative voltage portion and a zero-voltage portion. During the negative voltage portion, ions are attracted to the target to cause sputtering. During the zero-voltage portion, sputtering from the target is terminated while the bias on the substrate cause reverse sputtering therefrom. Accordingly, the negative voltage portion and the zero-voltage portion are alternated to cycle between a sputter step and a reverse sputter step.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: February 26, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Praburam Gopalraja, Sergio Edelstein, Avi Tepman, Peijun Ding, Debabrata Ghosh, Nirmalya Maity
  • Patent number: 6348238
    Abstract: A thin film is fabricated while causing ions in a plasma P to be incident by effecting biasing relative to the space potential of the plasma P by imparting a set potential to the surface of a substrate 9. A bias system 6 causes the substrate surface potential Vs to vary in pulse form by imposing an electrode imposed voltage Ve in pulse form on a bias electrode 23 which is in a dielectric block 22. The pulse frequency is lower than the oscillation frequency of ions in the plasma P, and the pulse period T, pulse width t and pulse height h are controlled by a control section 62 in a manner such that the incidence of ions is optimized. The imposed pulses are controlled in a manner such that the substrate surface potential Vs recovers to a floating potential Vf at the end of a pulse period T, and that the ion incidence energy temporarily crosses a thin film sputtering threshold value in a pulse period T.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: February 19, 2002
    Assignee: Anelva Corporation
    Inventors: Shigeru Mizuno, Makoto Satou, Manabu Tagami, Hideki Satou
  • Patent number: 6346177
    Abstract: A method of in-situ cleaning and deposition of device structures in a high density plasma environment. A device structure is located in a reaction chamber containing a sputter target. A high density plasma containing ionized gas particles is generated. The ionized gas particles are accelerated toward the device structure during a cleaning phase. The cleaning phase may be divided into a first cleaning phase during which no power is applied to the sputter target and a second cleaning phase during which power is supplied to the sputter target at a level sufficient to remove at least a portion of by-products deposited on the sputter target during the first cleaning phase.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: February 12, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Shane P. Leiphart
  • Patent number: 6342134
    Abstract: A quality-assurance method is described that is useful in the fabrication of piezoelectric films of electronic devices, particularly resonators for use in RF filters. For example, the method comprises determining the surface roughness of an insulating layer on which the piezoelectric film is to be deposited and achieving a surface roughness for the insulating layer that is sufficiently low to achieve the high-quality piezoelectric film. According to one aspect of the invention, the low surface roughness for the insulating layer is achieved with use of a rotating magnet magnetron system for improving the uniformity of the deposited layer. According to other aspects of the invention, the high-quality piezoelectric film is assured by optimizing deposition parameters including determination of a “cross-over point” for reactive gas flow and/or monitoring and correcting for the surface roughness of the insulating layer pre-fabrication of the piezoelectric film.
    Type: Grant
    Filed: February 11, 2000
    Date of Patent: January 29, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Bradley Paul Barber, Ronald Eugene Miller
  • Patent number: 6340417
    Abstract: The uniformity, density and directionality of an ionized metal plasma is significantly improved by positioning a cylindrical target between an RF coil and the chamber wall and wafers above and below the coil at opposite ends of the sputtering chamber. Ions generated by electron impact are attracted to the biased substrates, thereby providing essentially void free interconnections through insulating layers having through holes with very high aspect ratios.
    Type: Grant
    Filed: March 14, 1996
    Date of Patent: January 22, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic
  • Publication number: 20010050220
    Abstract: The present invention provides a method and apparatus for achieving conformal step coverage on a substrate by ionized metal plasma deposition. A target provides a source of material to be sputtered and ionized by a plasma maintained by a coil. The ionized material is deposited on the substrate that is biased to a negative voltage. A power supply coupled to the target supplies a modulated or time-varying signal thereto during processing. Preferably, the modulated signal includes a negative voltage portion and a positive voltage portion. The negative voltage portion and the positive voltage portion are alternated to cycle between a center-strong sputter step and an edge-strong sputter step. The film quality and uniformity can be controlled by adjusting the frequency and amplitude of the signal, the duration of the positive portion of the signal, the power supplied to each of the support member and the coil, and other process parameters.
    Type: Application
    Filed: November 16, 1999
    Publication date: December 13, 2001
    Applicant: Applied Materials, Inc.
    Inventors: TONY CHIANG, BARRY CHIN, PEIJUN DING
  • Publication number: 20010047931
    Abstract: Before submitting a sample, including a first material layered upon a substrate, to an ion milling process, whereby a second material is sputtered onto the surface of the first material and the sample is then submitted to an etching process, an irregularity is formed on the surface of the first material. The overall process results in the formation of cones, or micro-tip structures, which may then be layered with a layer of low work function material, such as amorphous diamond. The irregularity in the surface of the first material may be formed by polishing, sandblasting, photolithography, or mechanical means such as scratching.
    Type: Application
    Filed: February 7, 2001
    Publication date: December 6, 2001
    Applicant: SI Diamond Technology, Inc.
    Inventors: Chenggang Xie, Dean Joseph Eichman
  • Patent number: 6296740
    Abstract: Before submitting a sample, including a first material layered upon a substrate, to an ion milling process, whereby a second material is sputtered onto the surface of the first material and the sample is then submitted to an etching process, an irregularity is formed on the surface of the first material. The overall process results in the formation of cones, or micro-tip structures, which may then be layered with a layer of low work function material, such as amorphous diamond. The irregularity in the surface of the first material may be formed by polishing, sandblasting, photolithography, or mechanical means such as scratching.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: October 2, 2001
    Assignee: SI Diamond Technology, Inc.
    Inventors: Chenggang Xie, Dean Joseph Eichman
  • Patent number: 6294058
    Abstract: Compositely micro-textured thin film, magnetic disc media, with methods and apparatus for producing such, which are characterized by the incorporation of a first stage of micro-texturing provided by etching of a disc substrate, with a second, disparate, micro-texturing stage depositing rounded globules of eutectic alloy on the etched substrate.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: September 25, 2001
    Assignee: United Module Corporation
    Inventors: Edward F. Teng, Atef H. Eltoukhy, Bryan K. Clark, Wilfred M. Goh
  • Publication number: 20010018137
    Abstract: We have discovered that, by depositing a tantalum layer upon a substrate at a temperature of at least 325° C., it is possible to obtain an ultra low resistivity which is lower than that previously published in the literature. In addition, it is possible deposit a TaxNy film having an ultra low resistivity by depositing the TaxNy film upon a substrate at a temperature of at least 275° C., wherein x is 1 and y ranges from about 0.05 to about 0.18. These films having an ultra low resistivity are obtained at temperatures far below the previously published temperatures for obtaining higher resistivity films. A combination of elevated substrate temperature and ion bombardment of the film surface during deposition enables the use of lower substrate temperatures while maintaining optimum film properties.
    Type: Application
    Filed: January 25, 2001
    Publication date: August 30, 2001
    Applicant: Applied Materials, Inc.
    Inventors: Tony Chiang, Peijun Ding, Barry Chin
  • Publication number: 20010012570
    Abstract: A metal alloy solder ball comprising a first metal and a second metal, the first metal having a sputtering yield greater than the second metal. The solder ball comprises a bulk portion having a bulk ratio of the first metal to the second metal, an outer surface, and a surface gradient having a depth and a gradient ratio of the first metal to the second metal that is less than the bulk ratio. The gradient ratio increases along the surface gradient depth from a minimum at the outer surface. The solder ball may be formed by the process of exposing the ball to energized ions of a sputtering gas for an effective amount of time to form the surface gradient.
    Type: Application
    Filed: February 1, 2001
    Publication date: August 9, 2001
    Inventors: Frank D. Egitto, Edmond O. Fey, Luis J. Matienzo, David L. Questad, Rajinder S. Rai, Daniel C. Van Hart
  • Patent number: 6267852
    Abstract: Disclosed is a method of forming a PVD deposition chamber which is modified with an electrical circuit that allows a voltage bias to be applied to any one or more of a target, an in-process integrated circuit wafer, and collimator. The collimator can also be isolated from the electrical circuit. This configuration allows a preclean of the in-process integrated circuit wafer in situ in the PVD deposition chamber by ion sputtering and a subsequent sputter deposition through the collimator. A method is also disclosed wherein an in-process integrated circuit wafer is first precleaned in the PVD deposition chamber by applying a negative voltage bias to the in-process integrated circuit wafer. A film of conducting material is then sputter deposited on the surface of the in-process integrated circuit wafer by applying a negative voltage bias to the target. The collimator is electrically isolated during this process or is set at a higher potential than the in-process integrated circuit wafer.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: July 31, 2001
    Assignee: Micron Technology, Inc.
    Inventors: John H. Givens, Shane B. Leiphart
  • Publication number: 20010006147
    Abstract: A method for treating a silicon substrate is described. The silicon substrate is placed into a sputtering equipment. A sputtering step is performed to simultaneously dry clean and amorphize the silicon substrate surface by using the sputtering equipment. A titanium film is deposited on the silicon substrate by the sputtering equipment.
    Type: Application
    Filed: February 6, 2001
    Publication date: July 5, 2001
    Inventor: Su-Chen Fan