Semiconductor Wafer Boat Patents (Class 206/832)

Cross-Reference Art Collections

Apertured side walls (Class 206/833)
  • Publication number: 20030029771
    Abstract: The disk carrier with spindle comprises an outer shell including an upper portion and a lower portion that connect together to form a chamber to enclose disks and constrain a spindle in place in the chamber. The spindle further comprises elongated portions or partial cylinder sections joined by a hinge so that the spindle can be moved into a contracted position to freely pass through a central aperture of a disk or into an expanded position to contact the inner perimeter of the disk and secure the disk.
    Type: Application
    Filed: July 30, 2002
    Publication date: February 13, 2003
    Applicant: Entegris, Inc.
    Inventors: Thomas J. Whalen, Michael S. Adams
  • Patent number: 6382419
    Abstract: Disclosed is a container box for storage and transportation of wafer materials or other precision substrate plates in the electronic industries as well as for automatic loading of the wafer materials on a wafer-processing machine. Several accessory parts can be mounted on the container box as selected according to the usage conditions of the container box so as to accomplish improvements in the weight decrease, handleableness and storage. The wafer container box consists of a box body having a front opening and a covering thereon and comprises an upper mounting means provided on the top wall of the box body for supporting a robotic flange, a lower side mounting means provided on the outer surface of each of the side walls of the box body for supporting a side rail, and a side mounting means provided on the outer surface of each of the oppositely facing side walls of the box body for supporting a manual handle, each in a demountable fashion.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: May 7, 2002
    Assignee: Shin-Etsu Polymer Co. Ltd.
    Inventors: Yoshiaki Fujimori, Masato Takahashi
  • Patent number: 6247597
    Abstract: A jig for accommodating and transferring a carrier for carrying at least an article, the carrier having a first container with a first opening larger than the article, and the carrier having at least a first flange structure which extends from a peripheral portion of the first opening, and the first flange structure having a first size defined to be a distance between opposite edges of the first flange structure in a first direction, wherein the jig comprises a second container having a second opening with a second size larger than the first size of the first flange structure of the carrier, and the jig further has at least a second flange structure in an opposite side to a side provided with the second opening, and the second flange structure has a third size larger than the second size, and the jig also has at least a window structure which extends at least opposite sides and which is positioned adjacent to the second flange structure, so that the window structure is closer to the second opening than the se
    Type: Grant
    Filed: January 13, 1999
    Date of Patent: June 19, 2001
    Assignee: NEC Corporation
    Inventor: Akira Sato
  • Patent number: 6245147
    Abstract: A thermal processing jig 1 made from quartz for use in manufacturing semiconductor devices is provided, which may effectively prevent deposition of contaminating metals on the semiconductor devices during heat treatments thereof, and a method of manufacturing such jig in the form having a good structure for fabrication. The thermal processing jig 1 is designed to support silicon wafers 2 during heat treatments thereof. The body of the jig is made from a first type of quartz 8 having high heat resistance such as electric fusion quartz, while those portions of the jig coming adjacent to said silicon wafers 2 are made from a second type of quartz 7 such as oxyhydrogen flame fusion quartz and synthetic quartz which contains only a small amount of metal impurities and does not liberate metal impurities appreciably during the heat treatments.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: June 12, 2001
    Assignee: Fujitsu Limited
    Inventor: Masanori Kobayashi
  • Patent number: 6171400
    Abstract: An apparatus for holding a plurality of semiconductor wafers during heat treatment of the wafers in a furnace comprises a plurality of rails extending essentially vertically between a top and bottom plate. Each rail contains a plurality of teeth arranged such that the space between adjacent teeth can receive a portion of a single semiconductor wafer. Each tooth contains a raised support structure, typically a ledge, located on the top surface of each tooth for supporting the wafer, usually from the edge of the wafer inward to a point located from the center of the wafer a distance equal to between about 25% and about 75% of the wafer's radius. Such an apparatus with its relatively long teeth is especially designed to uniformly support larger wafers, i.e., wafers having a nominal diameter greater than about 200 millimeters, such that their own weight does not cause the wafers to sag and thereby produce crystal dislocations or slip when the wafers are heated to high temperatures.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: January 9, 2001
    Assignee: Union Oil Company of California
    Inventor: Larry S. Wingo
  • Patent number: 6139983
    Abstract: This invention relates to a corrosion-resistant member having a resistance to plasma of a halogen based corrosive gas, which comprises a main body and a corrosion-resistant layer formed on a surface of the main body and containing a fluoride of at least one element selected from the group consisting of rare earth elements and alkaline earth elements.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: October 31, 2000
    Assignee: NGK Insulators, Ltd.
    Inventors: Tsuneaki Ohashi, Kiyoshi Araki, Sadanori Shimura, Yuji Katsuda
  • Patent number: 6099686
    Abstract: In a wet processing system included in a semiconductor device production line, a wafer carrier has bars formed with grooves for receiving the edge portions of wafers, and a pair of support plates each having a width smaller than the diameter of the wafers. The carrier reduces a volume required of a processing bath and promotes the smooth flow of aqueous solutions. Hence, the system reduces the consumption of chemicals and pure water as well as the cleaning time and other processing times.
    Type: Grant
    Filed: July 20, 1995
    Date of Patent: August 8, 2000
    Assignee: NEC Corporation
    Inventor: Hiroyuki Sugiuti
  • Patent number: 6095335
    Abstract: A size-convertible device for supporting wafers in a parallel relationship includes a removable insert that enables the device to be non-destructively switched from providing edge support for large diameter wafers to providing edge support for small diameter wafers. The insert maintains the original wafer pitch and the original insertion angle. In the preferred embodiment, the device is a Front Opening Unified Pod (FOUP) specifically designed for use with 300 mm diameter wafers. Inserts are releasably attached to opposite sides of the FOUP to convert the device to a 200 mm diameter pod. The axis of the rest positions of the small wafers is coaxial with the rest positions of the large wafers. However, the inserts may be adapted to move the rest positions of the small wafers forwardly to a position such that there is front edge alignment with respect to rest positions of the large and small wafers.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: August 1, 2000
    Assignee: H-Square Corporation
    Inventor: William G. Busby
  • Patent number: 6093644
    Abstract: The invention is aimed at reducing the influence of the pollution from impurities in the wafer to improve the wafer yield on the basis of prevention of the pollution from impurities while occurrence of slip lines in the wafer is minimized to enhance the efficiency of the surface treatment of the wafer loading faces of the vertical wafer board. For example, the surface of the jig for semiconductor wafers which is composed of the substrate of a high purity carbon is formed with a SiC film by the CVD method, said surface being ground by a grinding tool again formed of a SiC film. Hangover particles produced by said grinding operation are subjected to a high temperature oxydizing treatment to be dissolved thereafter. Application of this method to the vertical wafer board realizes that when n times of measurements are conducted for a length of Lmm in the range of L.times.n.gtoreq.100 mm to obtain a result that said SiC film has a maximum surface roughness Rmax. which is maintained constantly below 10 .mu.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: July 25, 2000
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Takeshi Inaba, Atsuo Kitazawa
  • Patent number: 6089377
    Abstract: The invention provides a boat-type semiconductor wafer carrier which prevents such a situation that, upon wet processing of semiconductor wafers, the wafers carried thereon are displaced from grooves thereof and inclined until they fall down or contact with each other to break themselves or damage the surfaces of them. A holding member for holding down upper portions of the wafers is mounted on the boat-type carrier, and the wafer holding member is removable from the boat-type carrier, and is mounted onto the boat-type carrier to fix the wafers aligned on the boat-type carrier. Transportation of the wafers between processing tanks is performed by transporting the boat-type carrier on which the wafers are carried.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: July 18, 2000
    Assignee: NEC Corporation
    Inventor: Yuji Shimizu
  • Patent number: 6074479
    Abstract: This invention anneals a vertical stack of two or more groups of unseparated wafers, with approximately 10 wafers in each group. The invention makes it possible to anneal more wafers in a single annealing operation under a variety of conditions, including: oxygen outer diffusion annealing to form a denuded zone; annealing to control bulk micro defects and provide intrinsic gettering functions; annealing to enhance gate oxide integrity by eliminating crystal-originated particles from the wafer surface and internal grown-in or as-grown defects; and suppression of dislocation and slip in elevated temperature environments.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: June 13, 2000
    Assignee: Sumitomo Metal Industries Ltd.
    Inventors: Naoshi Adachi, Takehiro Hisatomi, Masakazu Sano
  • Patent number: 6039186
    Abstract: A composite wafer carrier for holding and restraining circular semiconductor wafer disks during their transport, storage, and processing. The composite wafer carrier generally comprising an open top and bottom for insertion and removal of wafer disk, an upright front end member having an interface portion such as an H-bar, an upright back end member, and a pair of sidewall members with vertical sidewall slots extending rearwardly from the front end member to said back end member. At least one of said members separately molded and joined to the other members of the wafer carrier by cooperating engagement portions without external fasteners. The wafer carrier may be snapped together. A separate second interface at the back end member may be provided to allow the carrier to interface with equipment with the wafer top side up or inverted.
    Type: Grant
    Filed: April 10, 1998
    Date of Patent: March 21, 2000
    Assignee: Fluoroware, Inc.
    Inventors: Sanjiv M. Bhatt, Shawn D. Eggum, Wayne C. Olson
  • Patent number: 5988393
    Abstract: A storage box is provided for the safe-keeping of fabricated or semi-fabricated semiconductor wafers. This wafer storage box allows the wafers to be tightly secured in position when held in the storage box for storage or shipping without the possibility of breaking the wafers as in the prior art. The wafer storage box includes a receptacle member having a first piece of soft material such as anti-static sponge on the inside thereof, a holding member which is accommodated in the receptacle member, and a covering member having a second piece of soft material such as anti-static sponge on the inside thereof. When the covering member is mounted on the receptacle member, the first and second pieces of anti-static sponge are disposed on opposite sides of the holding member, thus pressing against the wafers to secure them in position in the storage box.
    Type: Grant
    Filed: August 4, 1998
    Date of Patent: November 23, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Jason Hsia, Jason Horng
  • Patent number: 5960960
    Abstract: A wafer carrier includes a housing having an interior chamber which has a plurality of rows of grooves having a predetermined spacing formed thereon such that a plurality of wafers can be stored into the grooves of each row, respectively. The wafer carrier further includes a plurality of rows of movable elastic pieces provided around the interior chamber. The movable elastic pieces of each row corresponds to the grooves of each row formed on the interior chamber, respectively, and each movable elastic piece of each row is movable along a direction of the row between a first position of a corresponding groove and a second position between the corresponding groove and an adjacent groove.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: October 5, 1999
    Assignee: NEC Corporation
    Inventor: Nobuo Yamamoto
  • Patent number: 5931662
    Abstract: The present invention is designed to provide an annealing method for silicon single crystal wafers, which makes it possible to increase the number of silicon single crystal wafers processed during a single annealing process under a variety of annealing performed on silicon single crystal wafers, such as oxygen outer diffusion annealing for forming a DZ layer, annealing that generates and controls BMD for providing IG functions, and annealing that endeavors to improve and enhance GOI characteristics by eliminating wafer surface layer COP, and internal grown-in defects, and also enables the suppression of dislocation and slip in elevated temperature annealing environments. It calls for annealing to be performed by stacking up around 10 wafers, treating this group as a unit, placing this group, either horizontally or slightly inclined at an angle of roughly 0.5.about.5.degree.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: August 3, 1999
    Assignee: Sumitomo Sitix Corporation
    Inventors: Naoshi Adachi, Takehiro Hisatomi, Masakazu Sano
  • Patent number: 5858103
    Abstract: A radius of 0.1-1 mm is provided at a corner between a bottom of each of semiconductor wafer inserting and supporting grooves and a base of a supporting piece between the supporting groove and a supporting groove adjacent thereto, which are formed in bars connecting upper and lower end plates of a vertical wafer boat.
    Type: Grant
    Filed: May 14, 1997
    Date of Patent: January 12, 1999
    Assignee: Asahi Glass Company Ltd.
    Inventors: Toshio Nakajima, Hisao Yamamoto
  • Patent number: 5642813
    Abstract: A plastic container for storing and shipping semiconductor wafers comprising a wafer carrier of substantially rigid and transparent material supporting the wafers and maintaining the wafers in spaced relation to each other, top and bottom covers for the wafer carrier formed of stiff but resiliently flexibly yieldable material, the wafer carrier having upper and lower enlarged rim portions extending around the peripheries of the top and bottom of the wafer carrier and being embraced by enlarged peripherally extending rim portions of the top and bottom covers, the top and bottom covers having partially cylindrical panels with elongate beads or ridges formed thereon to engage and maintain the edges of the wafers spaced from the partially cylindrical surfaces, offset tabs on the wafer carrier and top and bottom covers facilitating of flexibly lifting small portions of the covers off the wafer carriers and then progressively disengaging the covers from the wafer carriers; a package comprising a multiplicity of cov
    Type: Grant
    Filed: April 5, 1996
    Date of Patent: July 1, 1997
    Assignee: Fluoroware, Inc.
    Inventor: David L. Nyseth
  • Patent number: 5593916
    Abstract: A holding container which is made of a polyether ether ketone resin and is suitable for use in holding one or more substrates upon fabrication of the corresponding number of thin-film semiconductor substrates useful in driving a planar display, for example, a liquid crystal display.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 14, 1997
    Assignee: Mitsui Toatsu Chemicals, Incorporated
    Inventors: Yoshihisa Gotoh, Motoo Kawamata, Toshiaki Takahashi
  • Patent number: D409158
    Type: Grant
    Filed: February 5, 1998
    Date of Patent: May 4, 1999
    Assignee: Tokyo Electron Limited
    Inventor: Tomohisa Shimazu