Adhesive Or Autogenous Bonding Of Two Or More Self-sustaining Preforms Wherein At Least Two Of The Preforms Are Not Intended To Be Removed (e.g., Prefabricated Base, Etc.) Patents (Class 216/33)
  • Patent number: 6656368
    Abstract: A method for manufacturing micromechanical components, and a micromechanical component, in which a movable element is produced on a sacrificial layer. In a subsequent step the sacrificial layer beneath the movable element is removed so that the movable element becomes movable. After removal of the sacrificial layer, a protective layer is deposited on a surface of the movable element. Silicon oxide and/or silicon nitride is used for the protective layer.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: December 2, 2003
    Assignee: Robert Bosch GmbH
    Inventors: Martin Schoefthaler, Peter Hein, Helmut Skapa, Horst Muenzel
  • Publication number: 20030201247
    Abstract: An etchant and a method for roughening a copper surface each capable of permitting copper with roughened surface which exhibits acid resistance and permits a copper conductive pattern and an outer layer material to be firmly bonded to each other therethrough in manufacturing of a printed wiring board to simplify the manufacturing. The etchant may contain an oxo acid such as sulfuric acid, peroxide such as hydrogen peroxide and an auxiliary component such as an azole and chlorine. The azole may comprise benzotriazole (BTA). The chlorine may be in the form of sodium chloride (NaCl). The etchant permits a copper surface to be roughened in an acicular manner.
    Type: Application
    Filed: March 21, 2003
    Publication date: October 30, 2003
    Applicant: Ebara Densan Ltd.
    Inventors: Yoshihiko Morikawa, Kazunori Senbiki, Nobuhiro Yamazaki
  • Patent number: 6625874
    Abstract: A method of forming a thermal bend actuator (6) is provided with upper arms (23, 25, 26) and lower arms (27, 28) which are non planar, so increasing the stiffness of the arms. The arms (23, 25, 26, 27, 28) may be spaced transversely of each other and do not overly each other in plan view, so enabling all arms to be formed by depositing a single layer of arm forming material.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: September 30, 2003
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 6623654
    Abstract: In accordance with the objectives of the invention a new method is provided for improving adhesion strength that is deposited over the surface of a layer of copper. Conventional etch stop layers of for instance dichlorosilane (SiCl2H2) or SiOC have poor adhesion with an underlying layer of copper due to poor molecular binding between the interfacing layers. The surface of the deposited layer of copper can be provided with a special enhanced interface layer by using a method provided by the invention. That is pre-heat of the copper layer followed by a pre-cleaning treatment with ammonia (NH3) and N2, followed by forming an adhesive enhanced layer over the copper layer by treatment with N2 or O2 or N2 with alkyl-silane or alkyl silane.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: September 23, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Bi-Trong Chen, Lain-Jong Li, Syun-Ming Jang, Shu E Ku, Tien I. Bao, Lih-Ping Li
  • Patent number: 6624077
    Abstract: A method for forming an optical waveguide includes depositing a cladding material on a first substrate, forming a trench in the cladding material on the first substrate, and filling the trench with a optically conductive core material. The upper surface of the cladding material and the optically conductive core material are then planarized to produce a substantially planar surface. The method further includes depositing a cladding material on a second substrate, forming a mirror image trench into the cladding material on the second substrate, and filling the mirror image trench with the optically conductive core material. The upper surface of the second cladding layer and the core material therein is then planarized. Thereafter, the first substrate is affixed to the second substrate such that the trench and the mirror image trench are in abutment and form a substantially circular optical core.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: September 23, 2003
    Assignee: Applied Materials, Inc.
    Inventor: John M. White
  • Patent number: 6616854
    Abstract: A donor substrate (12) which is patterned to include a donor mesa (18) is bonded to a receiving substrate (20). In a one embodiment, a bulk portion of the donor substrate is removed while leaving a transferred layer (26) bonded to the receiving substrate. The transferred layer is a layer of material transferred from the donor mesa. A portion of receiving substrate can be processed to form a recess (27, 28, or 32) to receive the donor mesa. Alternatively, the transferred layer can be formed over a dummy feature (46) formed on the receiving substrate, either with or without the use of mesas on the donor substrate. In a preferred embodiment, the transferred layer is used to form an optical device such as a photodetector in a semiconductor device. With the invention, bonding can be achieve despite having a non-planar surface on the receiving substrate.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: September 9, 2003
    Assignee: Motorola, Inc.
    Inventors: Robert E. Jones, Sebastian Csutak
  • Patent number: 6602431
    Abstract: A connection component for making microelectronic assemblies includes a dielectric structural layer having a first surface and a plurality of conductive leads having first and second ends overlying the first surface of the dielectric structural layer. An adhesive is provided between the second ends of the leads and the dielectric structural layer such that the adhesive forms connections between the second ends of the leads and the structural layer. The formed connections have areas smaller than the areas of the second ends. The second ends of the leads are releasably attached to the structural layer by the connections. Thus, the second ends of the leads may be engaged with features on a microelectronic device and the microelectronic elements may be moved away from the structural layer so as to bend the second ends of the leads away from the structural layer.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: August 5, 2003
    Assignee: Tessera, Inc.
    Inventor: Konstantine Karavakis
  • Patent number: 6599436
    Abstract: A method is disclosed to form external interconnections to a microfluidic device for coupling of a fluid or light or both into a microchannel of the device. This method can be used to form optical or fluidic interconnections to microchannels previously formed on a substrate, or to form both the interconnections and microchannels during the same process steps. The optical and fluidic interconnections are formed parallel to the plane of the substrate, and are fluid tight.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: July 29, 2003
    Assignee: Sandia Corporation
    Inventors: Carolyn M. Matzke, Carol I. H. Ashby, Leonardo Griego
  • Patent number: 6596183
    Abstract: A cutting-free method for making a hologram sticker includes the steps of adding a releasing layer on a base; plating a metal layer on the releasing layer; printing an epoxy layer with a holographic pattern on the metal layer; chemically etching the metal layer not covered by the epoxy layer together to remove the excess metal layer; washing the residual layers; drying the washed and etched layers; applying an adhesive layer on top of the washed epoxy layer and applying a releasing layer on top of the adhesive layer.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: July 22, 2003
    Inventor: Teng-Kuei Chen
  • Publication number: 20030111441
    Abstract: The present invention is concerned with a miniature microdevice package and a process of making thereof. The package has a miniature frame substrate made of a material selected from the group including: ceramic, metal and a combination of ceramic and metal. The miniature frame substrate has a spacer delimiting a hollow. The package also includes a microdevice die having a microdevice substrate, a microdevice integrated on the microdevice substrate, bonding pads integrated on the microdevice substrate, and electrical conductors integrated in the microdevice substrate for electrically connecting the bonding pads with the microdevice. The microdevice die is mounted on the spacer to form a chamber. The microdevice is located within the chamber. The bonding pads are located outside of the chamber.
    Type: Application
    Filed: November 25, 2002
    Publication date: June 19, 2003
    Applicant: Institut National D'Optique
    Inventors: Hubert Jerominek, Christine Alain
  • Publication number: 20030111440
    Abstract: A method of fabricating nanosized holes with controlled geometries employs tools and methods developed in the microelectronics industry. The method exploits the fact that epitaxially grown film thicknesses can be controlled within a few atomic monolayers and that by using etching techniques, trenches and channels can be created that are only a few nanometers wide. The method involves bonding two shallow channels at an angle such that a nanopore is defined by the intersection. Thus, a nanopore-defining device includes a nanopore with dimensions that are determined by the dimensions and orientations of the intersecting channels, with the dimensions being accurately controlled within a few monolayers.
    Type: Application
    Filed: December 19, 2001
    Publication date: June 19, 2003
    Inventors: Daniel B. Roitman, Dietrich W. Vook, Theodore I. Kamins
  • Patent number: 6579462
    Abstract: A flat display device, preferably of the PALC type, in which the plasma channels are formed by etching laterally-spaced slots in a spacer plate, attaching a thin dielectric sheet over the etched spacer plate, and bonding the etched spacer plate to a transparent substrate such that each channel is formed by the portion of the substrate between flanking walls formed by the etched slots in the spacer plate, adjacent flanking walls in the spacer plate, and the overlying portion of the thin dielectric sheet. In a modification, strengthening crossbars are formed between adjacent flanking walls.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: June 17, 2003
    Assignees: Philips Electronics North America Corporation, Tektronix, Inc.
    Inventors: Babar A. Khan, Henri R. J. R. Van Helleputte, Adrianus L. J. Burgmans, Karel Elbert Kuijk, Petrus F. G. Bongaerts, Jacob Bruinink, Thomas Stanley Buzak, Kevin John Ilcisin, Paul Christopher Martin
  • Patent number: 6572781
    Abstract: A sheet including lead regions with conductors and a main region surrounding the lead regions is formed on the front surface of a microelectronic element such as a wafer, or assembled thereto, so that the conductors are connected to contacts on the microelectronic element. After the sheet is in place, the sheet is eroded to form gaps partially bounding the lead regions, leaving tip ends of the lead regions moveable with respect to the main region. The tip ends of the lead regions, or the main region, is lifted away from the microelectronic element, thus bending the tip ends away from the main region. Because the gaps are not formed until after the conductors are connected to the contacts, the connecting step is simplified.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: June 3, 2003
    Assignee: Tessera, Inc.
    Inventor: Belgacem Haba
  • Publication number: 20030098289
    Abstract: A method of forming an optical component is disclosed. The method includes obtaining an optical component precursor having a first medium positioned over a base and converting a portion of the first medium to a second medium. The method further includes removing a portion of the second medium so as to form a ridge in the second medium. The portion of the second medium is removed so as to expose a portion of the first medium.
    Type: Application
    Filed: November 29, 2001
    Publication date: May 29, 2003
    Inventors: Dawei Zheng, Yiqiong Wang, Dazeng Feng, Xiaoming Yin
  • Patent number: 6568067
    Abstract: The present invention provides a method of efficiently manufacturing a dielectric waveguide with high reliability and precision. In the method, a resist material is formed on the outer surface of a green compact provided with a removal inhibiting layer, and predetermined portion of the green compact defined by the resist material is removed by the sand blasting method using the resist material as a mask, until the removal inhibiting layer is exposed to obtain a shaped green compact structure. The thus-obtained structure is fired to obtain a sintered body which comprises a dielectric strip and a wing.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: May 27, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Toshikazu Takeda
  • Patent number: 6571126
    Abstract: In one aspect, a method of manufacturing a capacitor includes disposing one or more conductive layers of a first electrode stack in a recess of an alignment mechanism, where the recess is positioned relative to two or more alignment elements. The method further includes placing a separator over the one or more conductive layers where an outer edge of the separator contacts the two or more alignment elements. In one embodiment, a capacitor includes anode and cathode foils having offsetting edge portions. In one embodiment, a multiple tab cathode for a flat capacitor. A plurality of cathode tabs are portioned into a plurality of cathode tab groups positioned in different locations along the edge of the capacitor stack to reduce the amount of space required for connecting and routing the cathode tabs.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: May 27, 2003
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: Michael J. O'Phelan, James M. Poplett, Robert R. Tong, A. Gordon Barr, Richard J. Kavanagh, Brian V. Waytashek
  • Patent number: 6562252
    Abstract: The invention relates to a method for reproducing images or text on a metalized holographic film, comprising a coupling step, in which a bottom metalized holographic film is laminated to a second film, thereon an adhesive mass has been preliminarily deposited, a spreading step in which on the bottom film a copolymeric primer is spread, a printing step in which a suitably activated basic substance is printed, a staged spreading removal step, in which demineralized water and decanting are used in order to remove the crystallized material obtained by the basic substance, a forced air hot bed drying step, a reinforcement processing step, and a printing step in which the text or image is printed in polymeric material colors.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: May 13, 2003
    Assignee: Illinois Tool Works Inc.
    Inventor: Mario Ferro
  • Patent number: 6540929
    Abstract: A book cover paper that is to be glued to a book block back has material scooped out on the side facing the book back, reducing the thickness of the cover paper at least over the width of the book block back, before the cover paper is joined to the book block back.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: April 1, 2003
    Assignee: Grapha Holding AG
    Inventors: Raphael Wicki, Peter Geiser
  • Publication number: 20030054662
    Abstract: Systems and methods are described for synthesis of films, coatings or layers using surfactants. A method includes providing a surfactant as an impurity within at least one of a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.
    Type: Application
    Filed: September 20, 2001
    Publication date: March 20, 2003
    Inventor: Billy J. Stanbery
  • Publication number: 20030054296
    Abstract: A ruler or similar flat article is provided with an upstanding handle in the form of a decorative design. The ruler and handle may be formed by a photoetch or chemical milling process, with full etching through the metal at edges and partial etching at the design elements in the body portion and handle portion. The handle portion can be unitarily formed and bent at a partially etched join line, and then reinforced using a solder or a braze. Brass or another metal may be used. The partially etched design detail in the handle portion creates a textured surface that facilitates gripping.
    Type: Application
    Filed: September 19, 2001
    Publication date: March 20, 2003
    Inventor: David Howell
  • Patent number: 6533947
    Abstract: Method for manufacturing microelectromechanical mirror and mirror array. Control electrodes and addressing circuitry are etched from a metallic layer deposited onto a reference layer substrate. Standoff-posts are etched from a subsequently deposited polyimide layer. A freely movable plate flexibly suspended from a plurality of electrostatic actuators that are flexibly suspended from a support frame is etched from an actuation layer substrate using a high aspect ratio etch. A mirror support post and surface are etched from a mirror substrate using a high aspect ratio etch. The mirror and actuation layer substrates are fusion bonded together. The reference and actuation layer substrates are bonded together and held apart by the standoff posts. A reflective metallic layer is deposited onto the mirror surface and polished. The mirror is etched from the mirror surface to free the microelectromechanical mirror. Mirror arrays are made by performing the aforementioned steps using standard IC processing techniques.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: March 18, 2003
    Assignee: Transparent Optical, Inc.
    Inventors: Steven Nasiri, James H. Smith, David Lambe Marx, Mitchell Joseph Novack
  • Patent number: 6521149
    Abstract: A method for manufacturing a free-standing solid diamond microchannel plate produces a base structure, including a silicon material, having a backing and a vertical extension. A chemical vapor deposition diamond material is deposited onto the backing. The diamond material is leveled with the vertical extension of the base structure. The silicon backing is removed from the leveled base structure.
    Type: Grant
    Filed: June 6, 2000
    Date of Patent: February 18, 2003
    Inventors: Gerald T. Mearini, Laszlo A. Takacs
  • Patent number: 6517736
    Abstract: A micro-fluidic device is disclosed with a gasket layer laminated between a silicon wafer patterned with channels and a glass wafer. The gasket layer is formed in two parts. A first portion of the gasket layer is formed on the inner walls of the channels and along the channel edges. A complimentary gasket is formed on the glass wafer. The silicon wafer and the glass wafer are anodically bonded together through their respective surface to enclosed channels or portions thereof. The fluidic properties of the micro-fluidic devices are altered depending on the gasket material that is used. In the preferred embodiments of the invention, the gasket material is selected from the group consisting of silicon carbide and silicon nitride.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: February 11, 2003
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Anthony Flannery, Nicholas J. Mourlas
  • Publication number: 20020174686
    Abstract: A process for micromachining capillaries was having circular cross-sections in glass substrates. Microchannels are isotropically etched into a flat glass substrate, resulting in a semi-circular half-channel (or a rectangle with rounded corners). A second flat glass substrate is then fusion bonded to the first substrate, producing sealed microchannels with rounded bottom corners and a flat top surface having sharp corners. The process is completed by annealing at a sufficiently high temperature (approximately 750 C.) to allow surface tension forces and diffusional effects to lower the over-all energy of the microchannels by transforming the cross-section to a circular shape. The process can be used to form microchannels with circular cross-sections by etching channels into a glass substrate, then anodically bonding to a silicon wafer and annealing. The process will work with other materials such as polymers.
    Type: Application
    Filed: May 7, 2001
    Publication date: November 28, 2002
    Applicant: The Regents of the University of California
    Inventors: Peter Krulevitch, Julie K. Hamilton, Harold D. Ackler
  • Patent number: 6475399
    Abstract: Disclosed is a method for fabricating a stencil mask for use in electron beam lithography which improves resolution by effectively reducing beam blur resulting from coulomb repulsion effects in the electron beam. The disclosed method includes fabricating a first mask and a second mask that are then aligned and joined to form the final stencil mask. The structure of the second mask limits the number and controls the initial pattern of the electrons that pass through the stencil mask to limit beam blur, narrow the incident energy distribution, and improve the resolution of the final image.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: November 5, 2002
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae Seung Choi
  • Patent number: 6475398
    Abstract: In a semiconductor device having a front surface where circuits are formed and a back surface, a hemishperical solid immersion lens is formed at the back surface of the semiconductor device in a body with the semiconductor device.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: November 5, 2002
    Assignee: NEC Corporation
    Inventor: Hideki Kitahata
  • Publication number: 20020158040
    Abstract: A method for fabricating MEMS structure includes etching a recess in an upper surface of a substrate that is bonded to a wafer that ultimately forms the MEMS structure. Accordingly, once the etching processes of the wafer are completed, the recess facilitates the release of an internal movable structure within the fabricated MEMS structure without the use of a separate sacrificial material.
    Type: Application
    Filed: April 26, 2001
    Publication date: October 31, 2002
    Inventors: Mark A. Lucak, Richard D. Harris, Michael J. Knieser, Robert J. Kretschmann
  • Patent number: 6461527
    Abstract: A method for fabricating a flexible printed circuit board with access on both sides includes the steps of applying a metallic conductor track sheet to a base sheet and patterning the metallic conductor track sheet in order to produce conductor tracks. A conductor track covering with first contact-making cutouts is applied over the conductor tracks. Second contact-making cutouts are produced in the base sheet material by locally removing the base sheet through the use of laser irradiation. As an alternative, the first contact-making cutouts as well as the second contact-making cutouts can be produced by removing material with a laser.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: October 8, 2002
    Assignee: Siemens Aktiengesellschaft
    Inventors: Detlef Haupt, Frank Franzen
  • Patent number: 6449831
    Abstract: A process is provided for forming a heater chip module comprising a carrier adapted to be secured to an ink-filled container, at least one heater chip having a base coupled to the carrier, and at least one nozzle plate coupled to the heater chip. The carrier includes a support substrate having at least one passage which defines a path for ink to travel from the container to the heater chip. The heater chip is secured at its base to a portion of the support substrate. At least the portion of the support substrate is formed from a material having substantially the same coefficient of thermal expansion as the heater chip base. A flexible circuit is coupled to the heater chip module such as by TAB bonding or wire bonding.
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: September 17, 2002
    Assignee: Lexmark International, Inc
    Inventors: Steven Robert Komplin, Ashok Murthy, Carl Edmond Sullivan
  • Patent number: 6428713
    Abstract: A micro-electro-mechanical structure including a semiconductor layer mounted to an annular support structure via an isolation layer wherein the semiconductor layer is micromachined to form a suspended body having a plurality of suspension projections extending from the body to the rim and groups of integral projections extending toward but spaced from the rim between said suspension projections. Each projection in said groups has a base attached to the body and a tip proximate the rim. The structure includes a plurality of inward projections extending from and supported on the rim and toward the body. Each such projection has a base attached to the rim and a tip proximate the body; wherein the grouped projections and the inward projections are arranged in an interdigitated fashion to define a plurality of proximate projection pairs independent of the suspension elements such that a primary capacitive gap is defined between the projections of each projection pair.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: August 6, 2002
    Assignee: Delphi Technologies, Inc.
    Inventors: John Carl Christenson, Steven Edward Staller, John Emmett Freeman, Troy Allan Chase, Robert Lawrence Healton, David Boyd Rich
  • Publication number: 20020084247
    Abstract: A method for recycling a disk having a layered structure on a glass substrate is disclosed. Initially, the disk is exposed to gaseous sulphur dioxide in a humid environment. Then, the disk is treated with hot water to remove the layered structure from the glass substrate.
    Type: Application
    Filed: November 26, 2001
    Publication date: July 4, 2002
    Applicant: International Business Machines Corporation
    Inventors: Dirk Hammel, Holger Roehl, Theo Schmitz, Johannes Windeln
  • Publication number: 20020084246
    Abstract: A method of producing indicia on a metallized and/or a holographic film comprising the steps of (a) printing, on an etchable surface of the film, a co-polymeric primer in a predetermined pattern, (b) depositing an activated etching substance on top of at least the unprinted metallized and/or holographic material under conditions sufficient to etch away portions of the film not covered by the primer and thereby forming a crystallized material as the debris of etching, (c) removing the crystallized material formed during etching and also removing any excess etching substance, and (e) drying the etched, printed film. Optionally, a reinforcing film layer may be disposed over the etched surface. The reinforcing layer may be colored in a predetermined pattern, especially a pattern that corresponds to the pattern of printing of the non-etchable copolymer.
    Type: Application
    Filed: November 23, 2001
    Publication date: July 4, 2002
    Inventor: Mario Ferro
  • Patent number: 6406636
    Abstract: Wafer-to-wafer bonding using, e.g., solder metal bonding, glass bonding or polymer (adhesive) bonding is improved by profiling one or both of the wafer surfaces being bonded to define microstructures therein. Profiling means providing other than the conventional planar bonding surface to define cavities therein. The bonding material fills the cavities in the microstructures. For instance, a system of ridges and trenches (e.g. in cross-section vertical, slanted, key-holed shaped, or diamond-shaped) are microstructures that increase the surface area of the wafers to which the bonding material can adhere. Use of the key-hole shaped or diamond-shaped profile having a negative slope at the trench interior substantially increases the bonding force.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: June 18, 2002
    Assignee: MegaSense, Inc.
    Inventor: Vladimir I. Vaganov
  • Patent number: 6391211
    Abstract: A method for making multi-layer electronic circuit board including a pre-circuit assembly 12 and a ground layer 14 which are automatically aligned and bonded together by use of solder material or deposits 26, 28.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: May 21, 2002
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Andrew Z. Glovatsky, Robert Joseph Gordon, Vivek Amir Jairazbhoy, Vladimir Stoica
  • Publication number: 20020051281
    Abstract: A method of making a galvano-mirror is provided. It includes the following steps. First, a first material substrate formed with a plurality of mirror plate regions is prepared. The mirror plate regions correspond in arrangement to the mirror plate of the galvano-mirror. Then, a second material substrate formed with a plurality of driver plate regions is prepared. The driver plate regions correspond in arrangement to the driver plate of the galvano-mirror. Then, the first and the second material substrates are attached to each other so that each of the mirror plate regions faces a relevant one of the driver plate regions. Finally, the attached first and second material substrates are divided into individual gaslvano-mirrors.
    Type: Application
    Filed: March 12, 2001
    Publication date: May 2, 2002
    Applicant: Fujitsu Limited
    Inventors: Satoshi Ueda, Ippei Sawaki, Yoshihiro Mizuno
  • Patent number: 6380099
    Abstract: A given planarity of the underlying layer is ensured after removal of a porous layer. In the first step, a porous layer is filled with a preprocess solution (e.g., water). In the second step, the preprocess solution filling the porous layer is replaced with an etchant (e.g., fluoric acid), and the porous layer is etched by the etchant. With this process, the time in which the porous layer is filled with the etchant is shortened to suppress variations in progress of etching.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: April 30, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Kazutaka Yanagita
  • Patent number: 6368515
    Abstract: In a method of manufacturing an ink-jet printer which uses a thin film sheet having adhesive layers respectively formed on the top and bottom sides, as an orifice plate, orifices are formed in the ink-ejecting side of the thin film sheet after the adhesive layer on that ink-ejecting side has been removed. This prevents the formation of the orifices from being adversely affected by any otherwise residual of the adhesive layer and can thus permit accurate formation of orifices of a desired shape. Even if helicon-wave dry etching which ensure fast etching using high-power energy is used to form orifices, therefore, no adhesive layer is thermally expanded to be a residual so that multiple orifices can be formed simultaneously and quickly.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: April 9, 2002
    Assignee: Casio Computer Co., Ltd.
    Inventors: Katsuzo Kaminishi, Junji Shiota, Ichiro Kohno, Kazuyoshi Arai
  • Patent number: 6337027
    Abstract: The present invention relates to micro electromechanical systems (MEMS) devices and more specifically to a process for manufacturing MEMS devices having at least one suspended structural element. The present invention seeks to provide an improved method for manufacture of MEMS devices having improved safety and increased yield and throughput compared to conventional EDP immersion process techniques. MEMS devices are made using a modified dissolution process that removes, in a selective etch step, inactive silicon to release an active silicon device from a sacrificial substrate. The present invention uses a selective etchant in conjunction with a commercial spray acid processing tool to provide a dissolution process with improved throughput, improved repeatable and uniform etch rates and reduction in the number of processing steps and chemical containment for improved safety.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: January 8, 2002
    Assignee: Rockwell Science Center, LLC
    Inventor: Kurt D. Humphrey
  • Publication number: 20010050266
    Abstract: Methods for making a micromachined device (e.g. an microoptical submount) having positive features (extending up from a device surface) and negative features (extending into the device surface). The present techniques locate the positive feature and negative features according to a single mask step. In one embodiment, a hard mask is patterned on top of the device layer of an SOI wafer. Then, RIE is used to vertically etch to the etch stop layer, forming the positive feature. Then, the positive feature is masked, and metal or hard mask is deposited on the exposed areas of the etch stop layer. Then, portions of the device layer are removed, leaving the patterned metal layer on the etch stop layer. Then, the etch stop layer is removed in an exposed area, uncovering the handle layer. Then, the handle layer is etched in an exposed area to form the negative feature.
    Type: Application
    Filed: May 2, 2001
    Publication date: December 13, 2001
    Inventors: David W. Sherrer, Gregory A. Ten Eyck, Dan A. Steinberg, Neal Ricks
  • Patent number: 6319418
    Abstract: A new pattern is provided for the bus lines that are used to facilitate plating of layers of electrical lines that form a Printed Circuit Board. Where Prior Art bus lines have a straight-line geometry, the bus lines of the invention have any geometry that is not a straight-line geometry. The geometry of the bus lines of the invention can be of any design as long as this design allows for interrupted cutting of the bus line, that is the cutting tool does not, during the process of cutting the bus line, make constant and continuous contact with the bus line.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: November 20, 2001
    Assignee: St. Assembly Test Services Pte Ltd.
    Inventors: Arvin Verdeflor, Albert Loh, Steven Liew, William S. Villaviray
  • Publication number: 20010023010
    Abstract: A substrate on which a plurality of thin films having a plurality of cross-sections corresponding to the cross-section of a micro-structure are formed is placed on a substrate holder. The substrate holder is elevated to bond a thin film formed on the substrate to the surface of a stage, and by lowering the substrate holder, the thin film is separated from the substrate and transferred to the stage side. The transfer process is repeated to laminate a plurality of thin films on the stage and to form the micro-structure. Accordingly, there are provided a micro-structure having high dimensional precision, especially high resolution in the lamination direction, which can be manufactured from a metal or an insulator such as ceramics and can be manufactured in the combined form of structural elements together, and a manufacturing method and an apparatus thereof.
    Type: Application
    Filed: February 26, 2001
    Publication date: September 20, 2001
    Applicant: Fuji Xerox Co. Ltd.
    Inventors: Takayuki Yamada, Mutsuya Takahashi, Masaki Nagata
  • Patent number: 6251782
    Abstract: A method for preparing small area parallel lapping specimens by a focused ion beam technique is disclosed in which a multiple-staged ion beam milling process is used to prepare a specimen for microscopic examination. The method may be carried out by first providing a high current ion beam for removal of a top surface of a specimen exposing a surface that immediately covers the characteristic feature to be examined to define a small window area that contains the characteristic feature. The present invention novel method may further be combined with a wet etching step after the ion beam milling process is completed. In the wet etching step, a three dimensional surface containing the characteristic feature to be examined is revealed which can then be observed under a scanning electron microscope.
    Type: Grant
    Filed: July 23, 1999
    Date of Patent: June 26, 2001
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Angela Y.C. Lee, Ting Chou
  • Patent number: 6245249
    Abstract: A substrate on which a plurality of thin films having a plurality of cross-sections corresponding to the cross-section of a micro-structure are formed is placed on a substrate holder. The substrate holder is elevated to bond a thin film formed on the substrate to the surface of a stage, and by lowering the substrate holder, the thin film is separated from the substrate and transferred to the stage side. The transfer process is repeated to laminate a plurality of thin films on the stage and to form the micro-structure. Accordingly, there are provided a micro-structure having high dimensional precision, especially high resolution in the lamination direction, which can be manufactured from a metal or an insulator such as ceramics and can be manufactured in the combined form of structural elements together, and a manufacturing method and an apparatus thereof.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: June 12, 2001
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Takayuki Yamada, Mutsuya Takahashi, Masaki Nagata
  • Patent number: 6242163
    Abstract: Micro-Mold Shape Deposition Manufacturing (&mgr;-Mold SDM) is a method for fabricating complex, three-dimensional microstructures from layered silicon molds. Silicon wafers are etched using conventional silicon-processing techniques to produce wafers with surface patterns, some of which contain through-etched regions. The wafers are then stacked and bonded together to form a mold, which is filled with part material. In one embodiment, the part material is a ceramic or metallic gelcasting slurry that is poured into the mold and solidified to form a part precursor. The mold is removed, and the precursor is sintered to form the final part. The gelcasting material may also be a polymer or magnetic slurry, in which case sintering is not needed. The mold can also be filled by electroplating a metal into it; if necessary, each layer is filled with metal after being bonded to a previously filled layer.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: June 5, 2001
    Assignee: Board of Trustees of the Leland Stanford Junior University
    Inventors: Jurgen Stampfl, Alexander Cooper, Rudolf Leitgeb, Yih-Lin Cheng, Friedrich Prinz
  • Patent number: 6221738
    Abstract: There are provided a method of producing an SOI wafer of high quality with excellent controllability, productivity and economy and a wafer produced by such a method. In the method of producing a substrate utilizing wafer bonding, a first substrate member and a second substrate member are mutually bonded, and then the second substrate member is separated from the first substrate member at the interface of a first layer and a second layer formed on the main surface of the first substrate member, whereby the second layer is transferred onto the second substrate member. In the separation, the separation position at the interface of the first and the second layers is ensured by varying the porosity of a porous Si layer, forming an easily separable plane by the coagulation of pores in porous Si, effecting ion implantation to the interface or utilizing a heteroepitaxial interface.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: April 24, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Nobuhiko Sato
  • Patent number: 6159385
    Abstract: The present invention relates to a fabrication process relating to a fabrication process for manufacture of micro-electromechanical (MEM) devices such as cantilever supported beams. This fabrication process requires only two lithographic masking steps and offers moveable electromechanical devices with high electrical isolation. A preferred embodiment of the process uses electrically insulating glass substrate as the carrier substrate and single crystal silicon as the MEM component material. The process further includes deposition of an optional layer of insulating material such as silicon dioxide on top of a layer of doped silicon grown on a silicon substrate. The silicon dioxide is epoxy bonded to the glass substrate to create a silicon--silicon dioxide-epoxy-glass structure. The silicon is patterned using anisotropic plasma dry etching techniques.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: December 12, 2000
    Assignee: Rockwell Technologies, LLC
    Inventors: Jun J. Yao, Robert J. Anderson
  • Patent number: 6137550
    Abstract: A channel structure for a PALC display panel comprises a channel member defining at least one channel, a cathode having an upper surface exposed in the channel, and an anode having an upper surface exposed in the channel. The upper surface of the anode is of substantially uniform composition and has a conductivity perpendicular to its upper surface of at least about 10.sup.-4 ohm.sup.-1 cm.sup.-1.
    Type: Grant
    Filed: September 9, 1997
    Date of Patent: October 24, 2000
    Assignee: Tektronix, Inc.
    Inventors: Robert D. Hinchliffe, Kevin J. Ilcisin, Mark W. Roberson
  • Patent number: 6129854
    Abstract: A method of performing a lower temperature bonding technique to bond together two mating pieces of glass includes applying a sodium silicate aqueous solution between the two pieces.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: October 10, 2000
    Assignee: UT-Battelle, LLC
    Inventors: J. Michael Ramsey, Robert S. Foote
  • Patent number: 6117395
    Abstract: A distributor, in particular for a chemical analysis arrangement, is disclosed, having at least two plate-like housing parts which lie against each other with respective contact faces, wherein in the contact face of at least one housing part there is provided at least one channel that is covered by the other housing part. In a distributor device of that kind it is desirable to be able to structure the channels as precisely as possible and for the channels to be well-sealed, and for the volume to correspond as accurately as possible to a predetermined value. To that end, in one of the two contact faces there is provided a recess for receiving a bonding agent, which recess is arranged adjacent to the channel and follows its course.
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: September 12, 2000
    Assignee: Danfoss A/S
    Inventors: Ole Ploug, John Thrane Hansen, Jakob B.o slashed.gh Schubert, Steen Gaardsted Kristensen, Theiss Stenstr.o slashed.m
  • Patent number: 6110391
    Abstract: A method of manufacturing a bonding substrate is disclosed. An oxide film is formed on at least one of two semiconductor substrates, and the two substrates are brought into close contact with each other via the oxide film. The substrates are heat-treated in an oxidizing atmosphere in order to firmly join the substrates together. Subsequently, the peripheral portion of a device-fabricating substrate is ground to a predetermined thickness, and an unjoined portion at the periphery of the device-fabricating substrate is completely removed through etching. The device-fabricating substrate is then ground and/or polished in order to reduce the thickness of the device-fabricating substrate to a desired thickness. The step of grinding the peripheral portion of the device-fabricating substrate to a predetermined thickness is performed by relative and radial movement of a grinding stone from the peripheral portion of the substrate toward the center thereof.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: August 29, 2000
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tokio Takei, Susumu Nakamura, Kazushi Nakazawa