Abstract: A method of forming an ultrasonic transducer device includes forming an insulating layer having topographic features over a lower transducer electrode layer of a substrate; forming a conformal, anti-stiction layer over the insulating layer such that the conformal layer also has the topographic features; defining a cavity in a support layer formed over the anti-stiction layer; and bonding a membrane to the support layer.

Abstract: A method for forming a cutting tool includes masking a metal base with one or more masks, the one or more masks including at least one variable permeability mask, and chemically etching the masked metal base to form a blade of the cutting tool.

Abstract: Embodiments are directed to forming reentrant multi-layer micro-scale or millimeter scale three dimensional structures, parts, components, or devices where each layer is formed from a plurality of deposited materials and more specifically where each layer is formed from at least one metal structural material and at least one organic sacrificial material (e.g. polymer) that are co-planarized and a portion of the sacrificial material located on a plurality of layers is removed after formation of the plurality of layers via one or more plasma etching operations or one or more neutral radical etching operations.

Abstract: A method of making a glass article, for example a glass light guide plate comprising at least one structured surface including a plurality of channels and peaks. The glass article may be suitable for enabling one dimensional dimming when used in a backlight unit for use as an illuminator for liquid crystal display devices.

Abstract: A method for producing at least one pattern in a substrate is provided, including providing a substrate having a front face surmounted by at least one masking layer carrying at least one mask pattern, carrying out an ion implantation of the substrate so as to form at least one first zone having a resistivity ?1 less than a resistivity ?2 of at least one second non-modified zone, after the ion implantation step, immersing the substrate in an electrolyte, and removing the at least one first zone selectively at the at least one second zone, the removing including at least an application of an electrochemistry step to the substrate to cause a porosification of the at least one first zone selectively at the at least one second zone.

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

Abstract: Memory devices for embedded applications are described. A memory device may include an array of memory cells having a first area and configured to operate at a first voltage, and circuitry having a second area that at least partially overlaps the first area. The circuitry may be configured to operate at a second voltage lower than the first voltage. The circuitry maybe be further configured to access the array of memory cells using decoder circuitry configured to operate at the first voltage. The array of memory cells and the circuitry may be on a single substrate. The circuitry may include microcontroller circuitry, cryptographic controller circuitry, and/or memory controller circuitry. The memory cells may be self-selecting memory cells that each include a storage and selector element having a chalcogenide material. The memory cells may not include separate cell selector circuitry.

Abstract: Described herein is a top-side vertical outcoupler for use in an integrated photonics device. The integrated photonics device can include a photonics circuit, where light can propagate through waveguide(s) to outcoupler(s). The outcoupler(s) can redirect the light to optics, which can then collimate, focus, and/or direct the light to a launch region located on an external surface of the device. The integrated photonics device can include a plurality of layers deposited on a supporting layer. The plurality of layers can be used to form the waveguide(s) and the outcoupler(s). By forming the outcoupler(s) of the same material as the waveguide(s), the amount of light that is lost can be reduced or minimized. Additionally, the reduced number of interfaces that the light has to pass through to reach the outcoupler(s) can allow for better control of the divergence angles of the emitted light.

Abstract: A semiconductor device having a barrier metal layer positioned over a metallization layer, and an under bump metallurgy layer over the barrier metal layer, and a solder bump over the under bump metallurgy layer.

Abstract: Examples include a method for forming an intermediate in the fabrication of a field-effect transistor sensor, the method comprising: providing a substrate having a substrate region comprising a gate dielectric thereon and optionally a nanocavity therein, providing a sacrificial element over the substrate region, providing one or more layers having a combined thickness of at least 100 nm over the sacrificial element, opening an access to the sacrificial element through the one or more layers, and optionally selectively removing the sacrificial element, thereby opening a sensor cavity over the substrate region; wherein the sacrificial element is removable by oxidation and wherein selectively removing the sacrificial element comprises an oxidative removal.

Abstract: Embodiments provided herein provide methods for preparing patterned neutral layers using photolithography, and structures prepared using the same. A method of preparing a structure may include disposing a film over a surface of a substrate, and removing plurality of elongated trenches from the film so as to define a plurality of spaced lines. A neutral layer may be disposed over the outer surface of each line, and may include a neutral group attached to the outer surface of that line via a covalent bond or a hydrogen bond. The surface of the substrate between the lines may be substantially free of the neutral layer.

Abstract: A memory device may include an array of memory cells having a first area and configured to operate at a first voltage, and circuitry having a second area that at least partially overlaps the first area. The circuitry may be configured to operate at a second voltage lower than the first voltage. The circuitry maybe be further configured to access the array of memory cells using decoder circuitry configured to operate at the first voltage. The array of memory cells and the circuitry may be on a single substrate. The circuitry may include microcontroller circuitry, cryptographic controller circuitry, and/or memory controller circuitry. The memory cells may be self-selecting memory cells that each include a storage and selector element having a chalcogenide material. The memory cells may not include separate cell selector circuitry.

Abstract: Provided is a method for removing barrier layer for minimizing sidewall recess. The method comprises the following steps: introduce noble-gas-halogen compound gas and carrier gas into an etching chamber within which a thermal gas phase etching process is being performed for etching a barrier layer (206) on non-recessed areas of an interconnection structure (501); detect an end point of the thermal gas phase etching process (502), if the thermal gas phase etching process reaches the end point end point, then execute the next step; if the thermal gas phase etching process doesn't reach the end point, then return to the previous step; stop introducing the noble-gas-halogen compound gas and the carrier gas to the etching chamber (503).

Abstract: The present invention provides a method for manufacturing a resist composition which is used in a manufacturing process of a semiconductor apparatus, comprising the steps of: cleaning a manufacturing apparatus for the resist composition with a cleaning solution; analyzing the cleaning solution taken out from the manufacturing apparatus; repeating the step of cleaning and the step of analyzing until a concentration of a nonvolatile component(s) contained in the cleaning solution became 10 ppm or less; and manufacturing the resist composition by using the manufacturing apparatus after the step of repeating. There can be provided a method for manufacturing a resist composition which can manufacture a resist composition lowered in coating defects.

Abstract: This is to provide a process for manufacturing a resist composition which can prepare a resist composition lowered in coating defects, and the manufacturing process is a process for manufacturing a resist composition to be used in a process for manufacturing a semiconductor apparatus, the process comprising the steps of: cleaning a manufacturing apparatus for a resist composition with a cleaning solution; analyzing the cleaning solution taken out from the manufacturing apparatus; repeating the step of cleaning and the step of analyzing until a concentration of metal components contained in the cleaning solution becomes 5 ppb or less; and manufacturing the resist composition by using the manufacturing apparatus after the step of repeating.

Abstract: A method of etching is described. The method includes forming a first chemical mixture by plasma-excitation of a first process gas containing an inert gas and at least one additional gas selected from the group consisting of He and H2, and exposing the first material on the substrate to the first chemical mixture to modify a first region of the first material. Thereafter, the method includes forming a second chemical mixture by plasma-excitation of a second process gas containing an inert gas and an additional gas containing C, H, and F, and exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material, which contains silicon nitride, relative to the second material and remove the modified first material from the first region of the substrate.

Abstract: The present disclosure advances the art by providing a method and system for forming electronic devices. In particular, and by example only, methods are described for forming devices for harvesting energy in the terahertz frequency range on flexible substrates, wherein the methods provide favorable accuracy in registration of the various device elements and facilitate low-cost R2R manufacturing.

Abstract: A method of etching is described. The method includes providing a substrate having a first material containing organic material and a second material that is different from the first material, forming a first chemical mixture by plasma-excitation of a first process gas containing an inert gas, and exposing the first material on the substrate to the first chemical mixture. Thereafter, the method includes forming a second chemical mixture by plasma-excitation of a second process gas containing S and O, and optionally a noble element, and exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second material.

Abstract: A method of etching is described. The method providing a substrate having a first material composed of silicon-containing organic material and a second material that is different from the first material, forming a chemical mixture by plasma-excitation of a process gas containing SF6 and an optional inert gas, controlling a processing pressure at or above 100 mtorr, and exposing the first material on the substrate to the chemical mixture to selectively etch the first material relative to the second material.

Abstract: A method of forming vertical spacers for spacer-defined multiple patterning, includes: depositing a first conformal pattern-transfer film having a first film stress, and continuously depositing a second conformal pattern-transfer film having a second film stress on a template; dry-etching the template except for a core material and a vertical portion of the first and second pattern-transfer films to form vertical spacers; and dry-etching the core material, forming a vacant space between the vertical spacers, wherein by adjusting the difference in film stress between the first and second pattern-transfer films, the leaning angle of the spacers is adjusted.

Abstract: An ion beam apparatus may include a chamber assembly configured to hold a material and direct an ion beam on the material, a detector configured to detect a signal generated from the material based on the ion beam being directed on the material, and a controller configured to control at least one parameter associated with the chamber assembly based on the signal, such that at least one of an ion energy associated with the ion beam, an ion current associated with the ion beam, and an incident angle of the ion beam with respect to a top surface of the material is changed continuously with time.

Abstract: The disclosure relates to methods for a multi-step plasma process to remove metal hard mask layer from an underlying hard mask layer that may be used to implement a sub-lithographic integration scheme. The sub-lithographic integration scheme may include iteratively patterning several features into the metal hard mask layer that may be transferred to the hard mask layer. However, the iterative process may leave remnants of previous films on top of the metal hard mask that may act as mini-masks that may interfere with the pattern transfer to the hard mask layer. One approach to remove the mini-masks may be to use a two-step plasma process that removes the mini-mask using a first gas mixture ratio of a carbon-containing gas and a chlorine-containing gas. The remaining metal hard mask layer may be removed using a second gas mixture ratio of the carbon-containing gas and the chlorine-containing gas.

Abstract: An extreme ultraviolet lithography pattern stack, including, an inorganic hardmask layer, an under layer on the inorganic hardmask layer, and a resist layer on the under layer, where the inorganic hardmask layer, under layer, and resist layer have a combined thickness in the range of about 8.5 nm to about 70 nm.

Abstract: A solar cell structure includes a semiconductor region disposed in or above a substrate. A damage buffer can be disposed above the semiconductor region. First and second conductive layers can be bonded together at a location above the damage buffer.

Abstract: Provided is a method for creating a mask blank that includes a capping layer and a shifter layer. The capping layer is optically compatible and process compatible with the shifter layer. The method may include providing a cleaned and polished mask substrate to a deposition tool and depositing, within the deposition tool, a shifter layer over a cleaned and polished mask substrate. The shifter layer may include each material of a set of materials in a first proportion. The method may also include depositing an additional layer over the shifter layer, the additional layer providing a capping layer over the shifter layer. The capping layer includes the materials in a second proportion unequal to the first proportion. The capping layer includes molybdenum, silicon, and nitride in a proportion that aids in detection by a residual gas analyzer. Also provided is also a mask blank structure incorporating the compatible capping layer.

Abstract: Methods for fabricating semiconductor devices are provided including sequentially stacking hardmask layers, a first sacrificial layer, and a second sacrificial layer on a substrate, forming first mandrels on the first sacrificial layer by etching the second sacrificial layer, forming first spacers on side walls of the first mandrels, forming a photoresist pattern disposed outside a region from which the first mandrels have been removed, forming second and third mandrels by etching the first sacrificial layer using the first spacers and the photoresist pattern as respective etching masks, forming second and third spacers on side walls of the second and third mandrels, forming first and second active patterns respectively having first and second pitches by etching the hardmask layer and at least a portion of the substrate, and forming a device isolation layer so that upper portions of the first and second active patterns protrude therefrom.

Abstract: Disclosed is a high-pressure discharge lamp (100) that reduces the occurrence of cracks even under high mercury vapor pressure. The high-pressure discharge lamp (100) is provided with a glass arc tube (102) including a light-emitting part (103) and a sealing part (104) connected to the light-emitting part (103), the light-emitting part (103) enclosing a discharge space, and a pair of electrodes (101), one end of each of the electrodes (101) facing one end of the other electrode (101) in the discharge space, and another end of each electrode (101) being embedded in the sealing part (104) and connected to a metal foil (105), at least one embedded section of the pair of electrodes (101) including at least one projection (101c).

Abstract: An under-layer composition of resist having superior thermal stability, etching resistance, gap-filling property and void-preventing property, and a method for forming pattern using the same are disclosed. The under-layer composition of resist comprises: an aromatic ring containing polymer having the repeating unit of the following Formula 1; a compound of the following Formula 4; and an organic solvent. in Formula 1, R1 is a monocyclic or polycyclic aromatic hydrocarbon group having 5 to 20 carbon atoms, R2 and R3 is independently a monocyclic or polycyclic aromatic hydrocarbon group having 4 to 14 carbon atoms, a is an integer of 1 to 3, and b is an integer of 0 to 2. in Formula 4, n is an integer of 1 to 250.

Abstract: Methods of fabricating semiconductor devices are provided including performing two photolithography processes and two spacer processes such that patterns are formed to have a pitch that is smaller than a limitation of photolithography process. Furthermore, line and pad portions are simultaneously defined by performing the photolithography process once and, thus, there is no necessity to perform an additional photolithography process for forming the pad portion. Related devices are also provided.

Abstract: A method is disclosed for the selective etching of a multi-layer metal oxide stack comprising a platinum layer on a TiN layer on an HfO2 or ZrO2 layer on a substrate. In some embodiments, the method comprises a physical sputter process to selectively etch the platinum layer, followed by a plasma etch process comprises CHF3 and oxygen to selectively etch the TiN, HfO2 or ZrO2 layers with respect to the substrate.

Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to the process of plasma etching an amorphous carbon layer. In one implementation, a method of etching a feature in an amorphous carbon layer is provided. The method comprises transferring a substrate including a patterned photoresist layer disposed above the amorphous carbon layer into an etching chamber, exposing the amorphous carbon layer to a fluorine-free etchant gas mixture including a fluorine-free halogen source gas and a passivation source gas and etching the amorphous carbon layer with a plasma of the fluorine-free etchant gas mixture. It has been found that plasma etching with a fluorine-free halogen based gas mixture reduces the formation of top critical dimension clogging oxides.

Abstract: A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.

Abstract: The present invention relates to a novel absorbing antireflective coating composition comprising a novel crosslinkable polymer comprising at least one repeat unit (A) having structure (1), at least one repeat unit (B) having a structure (2), and at least one repeat unit (C) having structure (3) where D is a direct valence bound or C(R1)(R2) methylene moiety where R1 and R2 are independently H, C1-C8 alkyl, C3-C24 cycloalkyl or C6-C24 aryl; Ari, Arii, Ariii and Ariv are independently phenylenic and naphthalenic moiety, R3 and R4 are independently hydrogen or C1-C8 alkyl; and R5 and R6 are independently hydrogen or C1-C8 alkyl; and a solvent. The invention also relates to a process for forming an image using the novel antireflective coating composition.

Abstract: A method of fabricating a semiconductor device is provided. An etch-target layer is formed on a substrate. A photoresist layer is formed on the etch-target layer. A first exposure process is performed using a first photo mask to form a plurality of first-irradiated patterns in the photoresist layer. The first photo mask includes a plurality of first transmission regions. Each first transmission region has different optical transmittance. A second exposure process is performed using a second photo mask to form a plurality of second-irradiated patterns in the photoresist layer. The second photo mask includes a plurality of second transmission regions. Each second transmission region has different optical transmittance. A photoresist pattern is formed from the photoresist layer by removing the plurality of first-irradiated and second-irradiated patterns from the photoresist layer. A lower structure is formed from the etch-target layer by etching the etch-target layer using the photoresist pattern.

Abstract: Methods of manufacturing a semiconductor device are provided. The method may include forming an etch target layer on a substrate, forming a carbon layer doped with boron on the etch target layer, a top end portion of the carbon layer having a different boron concentration from a bottom end portion of the carbon layer, patterning the carbon layer to form at least one opening exposing the etch target layer, and etching the exposed etch target layer using the carbon layer as an etch mask.

Abstract: A method for forming a patterned topography on a substrate is provided. The substrate is initially provided with an exposed plurality of lines formed atop. An embodiment of the method includes aligning and preparing a first directed self-assembly pattern (DSA) pattern immediately overlying the plurality of lines, and transferring the first DSA pattern to form a first set of cuts in the plurality of lines. The embodiment further includes aligning and preparing a second DSA pattern immediately overlying the plurality of lines having the first set of cuts formed therein, and transferring the second DSA pattern to form a second set of cuts in the plurality of lines. The first and second DSA patterns each comprise a block copolymer having a hexagonal close-packed (HCP) morphology and a characteristic dimension Lo that is between 0.9 and 1.1 times the spacing between individual lines of the plurality of lines.

Abstract: A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.

Abstract: Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby are provided. Two photolithography processes and two spacer processes are performed to provide final patterns that have a pitch that is smaller than a limitation of photolithography process. Furthermore, since initial patterns are formed to have line and pad portions simultaneously by performing a first photolithography process, there is no necessity to perform an additional photolithography process for forming the pad portion.

Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.

Abstract: A method of producing a structure containing a phase-separated structure, including: forming a layer including a neutralization film on a substrate; forming a layer containing a block copolymer on the layer including the neutralization film, the PA block and PB block being mutually bonded in the block copolymer, and the PB block including a structural unit other than a structural unit constituting the PA block; and subjecting the layer containing the block copolymer to an annealing treatment, such that, in the case where a surface free energy of the PA block, a surface free energy of the PB block and a surface free energy of the neutralization film are represented by a coordinate point A of the PA block, a coordinate point B of the PB block and a coordinate point N of the neutralization film, respectively in the plane of coordinates, the coordinate point N of the neutralization film is within the predetermined range.

Abstract: The present invention provides a composition for forming a coating type BPSG film, which comprises: one or more structures comprising a silicic acid represented by the following general formula (1) as a skeletal structure, one or more structures comprising a phosphoric acid represented by the following general formula (2) as a skeletal structure and one or more structures comprising a boric acid represented by the following general formula (3) as a skeletal structure. There can be provided a composition for forming a coating type BPSG film which is excellent in adhesiveness in fine pattern, can be easily wet etched by a peeling solution which does not cause any damage to the semiconductor apparatus substrate, the coating type organic film or the CVD film mainly comprising carbon which are necessary in the patterning process, and can suppress generation of particles by forming it in the coating process.

Abstract: A monomer for a hardmask composition is represented by the following Chemical Formula 1,

Abstract: A mask is disclosed. The mask includes at least one support base having at least one opening formed therein, where at least a portion of the boundary of the opening is tapered. The mask also includes at least one positioning layer disposed on the at least one support base, where at least one through opening corresponding to and aligned with the at least one opening is formed in the at least one positioning layer. In addition, at least a portion of the boundary of the through opening is tapered.

Abstract: A stack of a hard mask layer, a soft mask layer, and a photoresist is formed on a substrate. The photoresist is patterned to include at least one opening. The pattern is transferred into the soft mask layer by an anisotropic etch, which forms a carbon-rich polymer that includes more carbon than fluorine. The carbon-rich polymer can be formed by employing a fluorohydrocarbon-containing plasma generated with fluorohydrocarbon molecules including more hydrogen than fluorine. The carbon-rich polymer coats the sidewalls of the soft mask layer, and prevents widening of the pattern transferred into the soft mask. The photoresist is subsequently removed, and the pattern in the soft mask layer is transferred into the hard mask layer. Sidewalls of the hard mask layer are coated with the carbon-rich polymer to prevent widening of the pattern transferred into the hard mask.

Abstract: Disclosed is a method for fabricating a cliché that can prevent formation of a defective thin film pattern, and a method for forming a thin film pattern using the same. The method for fabricating a cliché includes providing a base substrate having first and second regions, forming a first depressed pattern having a first depth and a first width at a first region, and a second depressed pattern having a second width greater than the first width and a depth the same with the first depth at a second region, forming a protective film for exposing the second region and covering the first region, the protective film having adhesivity, forming the second depressed pattern to have a second depth deeper than the first depth of the first depressed pattern at the first region by using the protective film having the adhesivity, and removing the protective film.

Abstract: In accordance with an embodiment of the present invention, a method of polishing a device includes providing a layer having a non-uniform top surface. The non-uniform top surface includes a plurality of protrusions. The method further includes removing the plurality of protrusions by exposing the layer to a fluid that has gas bubbles and a liquid.

Abstract: A method of forming memory device is provided. A substrate having at least two cell areas and at least one peripheral area between the cell areas is provided. A target layer, a sacrificed layer and a first mask layer having first mask patterns in the cell areas and second mask patterns in the peripheral area are sequentially formed on the substrate. Sacrificed layer is partially removed to form sacrificed patterns by using the first mask layer as a mask. Spacers are formed on sidewalls of the sacrificed patterns. The sacrificed patterns and at least the spacers in the peripheral area are removed. A second mask layer is formed in the cell areas. Target layer is partially removed, using the second mask layer and remaining spacers as a mask, to form word lines in the cell areas and select gates in a portion of cell areas adjacent to the peripheral area.

Abstract: A phenolic monomer used in the lithographic process for semiconductor fabrication, a polymer for preparing a resist under-layer comprising the same, and a resist under-layer composition comprising the same, are disclosed.

Abstract: A method for fabricating a structure in magnetic recording head is described. First and second hard mask layers are provided on the layer(s) for the structure. A BARC layer and photoresist mask having a pattern are provided on the second hard mask layer. The pattern includes a line corresponding to the structure. The pattern is transferred to the BARC layer and the second hard mask layer in a single etch using an etch chemistry. At least the second hard mask layer is trimmed using substantially the same first etch chemistry. A mask including a hard mask line corresponding to the line and less than thirty nanometers wide is thus formed. The pattern of the second hard mask is transferred to the first hard mask layer. The pattern of the first hard mask layer is transferred to the layer(s) such that the structure has substantially the width.

Abstract: A photomask blank is provided comprising a transparent substrate, a single or multi-layer film including an outermost layer composed of chromium base material, and an etching mask film. The etching mask film is a silicon oxide base material film formed of a composition comprising a hydrolytic condensate of a hydrolyzable silane, a crosslink promoter, and an organic solvent and having a thickness of 1-10 nm. The etching mask film has high resistance to chlorine dry etching, ensuring high-accuracy processing of the photomask blank.