Mask Is Multilayer Resist Patents (Class 216/47)
  • Patent number: 8048473
    Abstract: When a mask layer is formed, a first liquid composition containing a mask-layer-forming material is applied on an outer side of a pattern that is desired to be formed (corresponding to a contour or an edge portion of a pattern) to form a first mask layer having a frame shape. A second liquid composition containing a mask-layer-forming material is applied so as to fill a space inside the first mask layer having a frame shape to form a second mask layer. The first mask layer and the second mask layer are formed to be in contact with each other, and the first mask layer is formed to surround the second mask layer. Therefore, the first mask layer and the second mask layer can be used as one continuous mask layer.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: November 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hironobu Shoji, Ikuko Kawamata
  • Patent number: 8048323
    Abstract: A method for manufacturing a magnetic recording medium (30) having magnetically separate magnetic recording patterns on at least one surface of a nonmagnetic substrate (1), includes the steps of forming a magnetic layer (2) on the nonmagnetic substrate, forming a mask layer (3) on the magnetic layer, forming a resist layer (4) on the mask layer, transferring negative patterns of the magnetic recording patterns to the resist layer using a stamp (5), removing portions of the mask layer which correspond to the negative patterns of the magnetic recording patterns, implanting ions in the magnetic layer from a resist layer-side surface to partly demagnetize the magnetic layer, and removing the resist layer and the mask layer.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: November 1, 2011
    Assignee: Showa Denko K.K.
    Inventors: Masato Fukushima, Akira Sakawaki
  • Publication number: 20110253670
    Abstract: Methods for etching silicon-based antireflective layers are provided herein. In some embodiments, a method of etching a silicon-based antireflective layer may include providing to a process chamber a substrate having a multiple-layer resist thereon, the multiple-layer resist comprising a patterned photoresist layer defining features to be etched into the substrate disposed above a silicon-based antireflective coating; and etching the silicon-based antireflective layer through the patterned photoresist layer using a plasma formed from a process gas having a primary reactive agent comprising a chlorine-containing gas. In some embodiments, the chlorine-containing gas is chlorine (Cl2).
    Type: Application
    Filed: October 1, 2010
    Publication date: October 20, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: YIFENG ZHOU, QINGJUN ZHOU, RYAN PATZ, JEREMIAH T. PENDER, MICHAEL D. ARMACOST
  • Patent number: 8029688
    Abstract: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: October 4, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shi-Yong Yi, Myeong-Cheol Kim, Dong-Ki Yoon, Kyung-Yub Jeon, Ji-Hoon Cha
  • Publication number: 20110236836
    Abstract: A method includes forming a hard mask layer over an etch target layer that extends across first and second regions, forming a sacrificial layer pattern over the hard mask layer of the first region, removing the sacrificial layer pattern after forming a spacer pattern on side walls thereof, selectively etching the hard mask layer of the first region by using the spacer pattern as an etch barrier while protecting the hard mask layer of the second region from being etched, removing the spacer pattern, forming a cut mask pattern over the hard mask layer of the first and second regions, etching the hard mask layer of the first and second regions by using the cut mask pattern as an etch barrier, removing the cut mask pattern, and forming patterns in the first and second regions respectively by using the hard mask layer of the first and second regions as an etch barrier and etching the etch target layer.
    Type: Application
    Filed: July 9, 2010
    Publication date: September 29, 2011
    Inventors: Sarohan Park, Eun-Ha Lee
  • Patent number: 8008210
    Abstract: An exposure mask for forming a G-type active region with a double patterning technology includes a bar shaped first light-blocking pattern to define an I-type active region, and an island shaped second light-blocking pattern to define a bit line contact region. The first light-blocking pattern and the second light-blocking pattern are arranged alternately.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: August 30, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seo Min Kim
  • Patent number: 7998357
    Abstract: For integrated circuit fabrication, at least one spacer support structure is formed in a first area over a semiconductor substrate, and a mask material is deposited on exposed surfaces of the spacer support structure and on a second area over the semiconductor substrate. A masking structure is formed on a portion of the mask material in the second area, and the mask material is patterned to form spacers on sidewalls of the spacer support structure and to form a mask pattern under the masking structure. The spacer support structure and the masking structure are comprised of respective high carbon content materials that have been spin-coated and have substantially a same etch selectivity.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-Myun Cho, Myeong-Cheol Kim, Shi-Yong Yi, Young-Hoon Song, Young-Ju Park
  • Patent number: 7998355
    Abstract: A method of generating a mask for printing a pattern including a plurality of features. The method includes the steps of depositing a layer of transmissive material having a predefined percentage transmission on a substrate; depositing a layer of opaque material on the transmissive material; etching a portion of the substrate, the substrate being etched to a depth based on an etching selectivity between the transmissive layer and the substrate; exposing a portion of the transmissive layer by etching the opaque material; etching the exposed portion of the transmissive layer so as to expose an upper surface of the substrate; where the exposed portions of the substrate and the etched portions of the substrate exhibit a predefined phase shift relative to one another with respect to an illumination signal.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: August 16, 2011
    Assignee: ASML Masktools B.V.
    Inventors: Douglas Van Den Broeke, Kurt E. Wampler, Jang Fung Chen
  • Publication number: 20110132870
    Abstract: A method of making a microfluidic module is disclosed that includes forming a fluid flow channel in a self-bonding rebondable polyimide film to provide a channel sheet, the self-bonding rebondable polyimide film having a first mask layer self-bonded thereto; removing the first mask layer from the channel sheet after forming the fluid flow channel; and self-bonding the surface of the channel sheet exposed by removal of the first mask layer to a cover sheet.
    Type: Application
    Filed: February 16, 2011
    Publication date: June 9, 2011
    Applicant: YSI INCORPORATED
    Inventor: Donald R. Moles
  • Publication number: 20110108473
    Abstract: A micromechanical filter for microparticles is suitable in particular for filtering pathogenic bacteria and viruses, and comprises a substrate and a perforated membrane permanently connected to the substrate, for filtering out microparticles from a medium while flowing through the membrane, and furthermore a device for removing the filtered-out microparticles from the surface of the membrane. The device for removing the microparticles is embodied, for example, as a heating device, in order to burn the microparticles located on the surface of the membrane. It can also be embodied as an actuator structure for deforming the membrane or as a microinjector for generating a flow parallel to the surface of the membrane.
    Type: Application
    Filed: June 1, 2007
    Publication date: May 12, 2011
    Inventors: Alois Friedberger, Gerhard Mueller
  • Patent number: 7938973
    Abstract: By incorporating a material exhibiting a high adhesion on chamber walls of a process chamber during sputter etching, the defect rate in a patterning sequence on the basis of an ARC layer may be significantly reduced, since the adhesion material may be reliably exposed during a sputter preclean process. The corresponding adhesion layer may be positioned within the ARC layer stack so as to be reliably consumed, at least partially, while nevertheless providing the required optical characteristics. Hence, a low defect rate in combination with a high process efficiency may be achieved.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: May 10, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf Richter, Joerg Hohage, Martin Mazur
  • Patent number: 7935635
    Abstract: A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: May 3, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-yub Jeon, Myeong-cheol Kim, Doo-youl Lee, Hak-sun Lee
  • Publication number: 20110089141
    Abstract: A multi-stepped substrate having a plurality of steps is produced by forming, on the principal surface of a substrate, a plurality of masks which are put on top of each other, which differ from each other in the materials used for forming them and which are likewise different, from each other, in the means for peeling off the same; and that the substrate is subjected, in order, to dry-etching operations through the plurality of masks each having a desired shape such that the substrate has a plurality of steps each of which reflects the shape of each corresponding mask.
    Type: Application
    Filed: June 15, 2009
    Publication date: April 21, 2011
    Applicant: ULVAC,INC.
    Inventors: Ai Tanaka, Atsushi Kira, Koh Fuwa
  • Patent number: 7888193
    Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: February 15, 2011
    Assignees: Fujitsu Limited, Fujitsu Quantum Devices Limited
    Inventors: Kozo Makiyama, Naoya Ikechi, Takahiro Tan
  • Patent number: 7888267
    Abstract: A method of dry developing a multi-layer mask having a silicon-containing anti-reflective coating (ARC) layer on a substrate is described. The method comprises forming the multi-layer mask on the substrate, wherein the multi-layer mask comprises a lithographic layer overlying the silicon-containing ARC layer. A feature pattern is then formed in the lithographic layer using a lithographic process. Thereafter, the feature pattern is transferred from the lithographic layer to the silicon-containing ARC layer using a dry plasma etching process, wherein the offset in the critical dimension (CD) bias is reduced between nested structures and isolated structures.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: February 15, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Akiteru Ko, Christopher Cole
  • Patent number: 7867408
    Abstract: A silicon oxide film is formed on one principal surface of a silicon substrate by thermal oxidation, and thereafter, a silicon nitride film is formed on the silicon oxide film by CVD. A lamination layer of the silicon oxide film and silicon nitride film is selectively dry etched to form a mask opening 22 and leave an etching mask made of a left region of the lamination layer. The substrate is selectively and anisotropically etched with alkali etchant such as TMAH by using the etching mask to form a substrate opening. By setting a ration of the thickness of the silicon oxide film to the thickness of the silicon nitride film to 1.25 or larger or preferably 1.60 or larger, it is possible to prevent the deformation of the etched shape of the inner walls of the openings and cracks in the etching mask.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: January 11, 2011
    Assignee: Yamaha Corporation
    Inventor: Tomoyasu Aoshima
  • Patent number: 7862859
    Abstract: A method of correcting for pattern run out in a desired pattern in directional deposition or etching comprising the steps of providing a test substrate; providing a stencil of known thickness on the test substrate; providing a stencil pattern extending through the stencil to the test substrate.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: January 4, 2011
    Assignee: RFMD (UK) Limited
    Inventor: Jason McMonagle
  • Publication number: 20100327412
    Abstract: Small feature patterning is accomplished using a multilayer hard mask (HM). Embodiments include sequentially forming a first HM layer and a multilayer HM layer over a substrate, the multilayer HM layer comprising sublayers, etching the multilayer HM layer to form a first opening having an upper first opening with sides converging to a lower second opening and a second opening with substantially parallel sides and an opening substantially corresponding to the lower second opening of the first opening, etching through the second opening to form a corresponding opening in the first HM layer, and etching the substrate through the corresponding opening in the first HM layer.
    Type: Application
    Filed: June 29, 2009
    Publication date: December 30, 2010
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Doug H. Lee, Erik P. Geiss
  • Patent number: 7857982
    Abstract: The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the feature pattern therein as a mask. After the partial etching, at least one of the hard mask layers is etched selectively relative to the substrate material and remaining of the hard mask layers. After etching at least one of the hard mask layers, the feature is further etched into the substrate material using at least an innermost of the hard mask layers as a mask. After the further etching, the innermost hard mask layer and any hard mask layers remaining thereover are removed from the substrate, and at least a portion of the feature is incorporated into an integrated circuit.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: December 28, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, Gurtej S. Sandhu, Aaron R. Wilson, Tony Schrock
  • Patent number: 7850862
    Abstract: Textured surface having micro recesses such that the outer surface overhangs the micro recesses. Embodiments of the textured surface include sharp edges for promoting bone deposition and growth within the micro recesses, protrusions of varying depth from the surface that include overhangs, and micro recesses that are at least partially defined by complex ellipsoids.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: December 14, 2010
    Assignee: Tecomet Inc.
    Inventors: Mark Amrich, Jonathan Rolfe, Joseph Buturlia, Robert Lynch
  • Patent number: 7837459
    Abstract: The process of producing a dual damascene structure used for the interconnect architecture of semiconductor chips. More specifically the use of imprint lithography to fabricate dual damascene structures in a dielectric and the fabrication of dual damascene structured molds.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: November 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Matthew E. Colburn, Kenneth Raymond Carter, Gary M. McClelland, Dirk Pfeiffer
  • Patent number: 7838426
    Abstract: A method for etching a dielectric layer is provided. A patterned mask with mask features is formed over a dielectric layer. The mask has isolated areas and dense areas of the mask features. The mask is trimmed by a plurality of cycles, where each cycle includes depositing a deposition layer, and selectively etching the deposition layer and the patterned mask. The selective etching selectively trims the isolated areas of the mask with respect to the dense areas of the mask. The dielectric layer is etched using the thus trimmed mask. The mask is removed.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: November 23, 2010
    Assignee: Lam Research Corporation
    Inventors: Supriya Goyal, Dongho Heo, Jisoo Kim, S.M. Reza Sadjadi
  • Patent number: 7811942
    Abstract: Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch process. The single plasma etch process can be used to remove one or more portions/layers of the TLR stack that needs to be reworked in a single process. The removed portions/layers can then be re-formed and resulting in a reworked TLR stack for subsequent photo-resist (PR) processing. The disclosed plasma-etch resist rework method can be a fast, simple, and cost effective process used in either single or dual damascene tri-layer patterning processes for the fabrication of, for example, sub 45-nm node semiconductor structures.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: October 12, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Jeannette Michelle Jacques, Yong Seok Choi
  • Patent number: 7805820
    Abstract: A thin-film resonator and a method for producing a thin-film component includes, for the purpose of structuring an upper first dielectric layer, a mask that comprises a second dielectric layer facing the upper dielectric layer and a photoresist layer. Initially, the photoresist layer that serves as photomask during the structuring of the second dielectric layer is structured. The structures of the second dielectric layer, together with the structures of the photoresist layer located thereabove, form a mask that is used for structuring the first dielectric layer.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: October 5, 2010
    Assignee: Epcos AG
    Inventors: Christoph Eggs, Ansgar Schäufele, Martin Woelky
  • Patent number: 7799696
    Abstract: A method of manufacturing an integrated circuit including a memory device that includes the following processes: forming a mask layer structure above a composite structure including a resistivity changing layer and an electrode layer disposed above the resistivity changing layer; partially patterning the mask layer structure using a first substance; stopping patterning the mask layer structure before exposing the top surface of the electrode layer; at least partially exposing the top surface of the electrode layer using a second substance, the second substance chemically not reacting with the electrode layer material.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: September 21, 2010
    Assignees: Qimonda AG, Altis Semiconductor, SNC
    Inventor: Stéphane Cholet
  • Patent number: 7785484
    Abstract: A method for etching a dielectric layer disposed below an antireflection layer (ARL) is provided. The method comprises (a) forming a patterned mask with mask features over the ARL, the mask having isolated areas and dense areas of the mask features, (b) trimming and opening, and (c) etching the dielectric layer using the trimmed mask. The trimming and opening comprises a plurality of cycles, where each cycle includes (b1) a trim-etch phase which etches the ARL in a bottom of the mask features and selectively trims the isolated areas of the mask with respect to the dense areas, and (b2) a deposition-etch phase which deposits a deposition layer on the mask while further etching the ARL in the bottom of the mask features. The trimming and opening result in a net trimming of the mask in the isolated areas.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: August 31, 2010
    Assignee: Lam Research Corporation
    Inventors: Dongho Heo, Supriya Goyal, Jisoo Kim, S. M. Reza Sadjadi
  • Publication number: 20100209675
    Abstract: The invention is directed to a method for patterning a material layer. The method comprises steps of providing a material layer having a first hard mask layer and a second hard mask layer successively formed thereon and then patterning the second hard mask layer. Thereafter, an etching process is performed to pattern the first hard mask layer by using the patterned second hard mask layer as a mask, and the etching process is performed with a power of about 1000 W. Next, the material layer is patterned by using the patterned first hard mask layer as a mask.
    Type: Application
    Filed: February 17, 2009
    Publication date: August 19, 2010
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Chung Chen, Hsin-Fang Su, Shih-Chang Tsai
  • Patent number: 7765676
    Abstract: A method for constructing a magnetoresistive sensor using an etch mask that is resistant to the material removal process used to define the sensor width and stripe height. The method may include the use of a Ta etch mask formed under a photoresist mask, and the use of an ion milling process to define the sensor. The etch mask remains substantially intact after performing the ion milling and therefore is readily removed by a later CMP process. The etch mask layer is also very resistant to high temperatures such as those used in a desired atomic layer deposition of alumina, which is used to deposit conformal layers of alumina around the sensor.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: August 3, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Marie-Claire Cyrille, Elizabeth Ann Dobisz, Wipul Pemsiri Jayasekara, Jui-Lung Li
  • Patent number: 7760435
    Abstract: A method is for forming three-dimensional micro- and nanostructures, based on the structuring of a body of material by a mould having an impression area which reproduces the three-dimensional structure in negative form. This method includes providing a mould having a substrate of a material which can undergo isotropic chemical etching, in which the impression area is to be formed. An etching pattern is defined on (in) the substrate, having etching areas having zero-, uni- or bidimensional extension, which can be reached by an etching agent. A process of isotropic chemical etching of the substrate from the etching areas is carried out for a corresponding predetermined time, so as to produce cavities which in combination make up the impression area. The method is advantageously used in the fabrication of sets of microlenses with a convex three-dimensional structure, of the refractive or hybrid refractive/diffractive type, for forming images on different focal planes.
    Type: Grant
    Filed: February 21, 2005
    Date of Patent: July 20, 2010
    Assignee: Consiglio Nazionale Delle Ricerche- INFM Instituto Nazionale per la Fisica Della Materia
    Inventors: Massimo Tormen, Alessandro Carpentiero, Enzo Mario Di Fabrizio
  • Publication number: 20100170871
    Abstract: A disclosed fine pattern forming method includes steps of: forming patterns made of a first photoresist film, arranged at a first pitch on a film; trimming the patterns made of the first photoresist film; depositing a protection film on the patterns made of the first photoresist film on the trimmed patterns made of the first photoresist film, the protection film being made of reaction products of an etching gas, thereby obtaining first patterns; forming other patterns made of a second photoresist film, arranged at a second pitch, on the protection film, the other patterns made of the second photoresist film being shifted by half of the first pitch from the corresponding patterns made of the first photoresist film; trimming the other patterns made of the second photoresist film into second patterns; and etching the film using the first patterns and the second patterns.
    Type: Application
    Filed: January 4, 2010
    Publication date: July 8, 2010
    Inventors: TAKASHI SONE, Eiichi Nishimura
  • Patent number: 7749902
    Abstract: Provided is a method of manufacturing a semiconductor device using double patterning. The method includes: forming a first material layer pattern having recesses in a first direction on an object layer and a second material layer pattern formed on the first material layer pattern; selectively etching the second material layer pattern and the first material layer pattern in a direction perpendicular to the first direction to form an etching mask; and etching the object layer to form minute patterns.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: July 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-chul Kim, Sung-il Cho, Jae-seung Hwang, Jun Sen, Yong-hyun Kwon
  • Publication number: 20100163526
    Abstract: The present invention is directed to substrates comprising amplified patterns, methods for making the amplified patterns, and methods of using the amplified patterns to form surface features on the substrates.
    Type: Application
    Filed: June 29, 2009
    Publication date: July 1, 2010
    Applicant: Nano Terra Inc.
    Inventors: Brian T. MAYERS, Jeffrey Carbeck, Wajeeh Saadi, George M. Whitesides
  • Patent number: 7745104
    Abstract: There is disclosed a bottom resist layer composition for a multilayer-resist film used in lithography comprising, at least, a polymer comprising a repeating unit represented by the following general formula (1). Thereby, there can be provided a bottom resist layer composition that exhibits optimum n value and k value on exposure to shorter wavelengths, excellent etching resistance under conditions for etching substrates, and is promising for forming a bottom resist layer used for a multilayer-resist process such as a silicon-containing bilayer resist process or a trilayer resist process using a silicon-containing intermediate resist layer.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: June 29, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Jun Hatakeyama, Toshihiko Fujii, Takanobu Takeda
  • Patent number: 7723143
    Abstract: A method for manufacturing a cantilever structure of a probe card is disclosed. In accordance with the method of the present invention, a first sacrificial wafer is used as a mold to form a cantilever structure having various shapes, a microscopic pitch and a high aspect ratio. In accordance with the method of the present invention, a probe tip may be formed by using a second sacrificial substrate and a bonding.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: May 25, 2010
    Assignee: Will Technology Co., Ltd.
    Inventors: Bong Hwan Kim, Jong Bok Kim
  • Patent number: 7718077
    Abstract: A method of fabricating an article usable in an imprint lithographic process is disclosed. The method includes patterning masking material layers on a substrate thereby forming a multi-layer mask and sequentially removing portions of the substrate based on the multi-layer mask to thereby forming a structure usable in an imprint lithographic process.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: May 18, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Han-Jun Kim, Carl P. Taussig
  • Patent number: 7709389
    Abstract: A method of fabricating a semiconductor device comprising a method of forming an etching mask used for etching a semiconductor base material is disclosed. The method of fabricating a semiconductor device comprises forming hard mask patterns on a semiconductor base material; forming material layers covering the lateral and top surfaces of the hard mask patterns to form openings between adjacent hard mask patterns, wherein the width of each opening is smaller than the distance between adjacent hard mask patterns; and etching the semiconductor base material using the hard mask patterns and material layers as an etching mask.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-chan Kim, Chang-jin Kang, Kyeong-koo Chi
  • Patent number: 7695632
    Abstract: A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: April 13, 2010
    Assignee: Lam Research Corporation
    Inventors: Sangheon Lee, Dae-Han Choi, Jisoo Kim, Peter Cirigliano, Zhisong Huang, Robert Charatan, S.M. Reza Sadjadi
  • Patent number: 7682516
    Abstract: A method for etching features in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have irregular profiles along depths of the photoresist features. The irregular profiles along the depths of the photoresist features of the sidewalls of the photoresist features are corrected comprising at least one cycle, where each cycle comprises a sidewall deposition phase and a profile shaping phase. Feature is etched into the etch layer through the photoresist features. The mask is removed.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: March 23, 2010
    Assignee: Lam Research Corporation
    Inventors: S. M. Reza Sadjadi, Peter Cirigliano, Jisoo Kim, Zhisong Huang, Eric A. Hudson
  • Patent number: 7676905
    Abstract: A magnetoresistive sensor having a pinned layer that extends beyond the stripe height defined by the free layer of the sensor. The extended pinned layer has a strong shape induced anisotropy that maintains pinning of the pinned layer moment. The extended portion of the pinned layer has sides beyond the stripe height that are perfectly aligned with the sides of the sensor within the stripe height. This perfect alignment is made possible by a manufacturing method that uses a mask structure for more than one manufacturing phase, eliminating the need for multiple mask alignments.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: March 16, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventor: Mustafa Michael Pinarbasi
  • Publication number: 20100055913
    Abstract: A method of forming a photoresist-comprising pattern on a substrate includes forming a patterned first photoresist having spaced first masking shields in at least one cross section over a substrate. The first masking shields are exposed to a fluorine-containing plasma effective to form a hydrogen and fluorine-containing organic polymer coating about outermost surfaces of the first masking shields. A second photoresist is deposited over and in direct physical touching contact with the hydrogen and fluorine-containing organic polymer coating. The second photoresist which is in direct physical touching contact with the hydrogen and fluorine-containing organic polymer coating is exposed to a pattern of actinic energy and thereafter spaced second masking shields are formed in the one cross section which comprise the second photoresist and correspond to the actinic energy pattern. The first and second masking shields together form at least a part of a photoresist-comprising pattern on the substrate.
    Type: Application
    Filed: August 29, 2008
    Publication date: March 4, 2010
    Inventors: Zishu Zhang, Hongbin Zhu, Anton deVilliers, Alex Schrinsky
  • Patent number: 7658858
    Abstract: A band filter using a film bulk acoustic resonator and a method of fabricating the same. The method includes the steps of forming a membrane layer on a substrate, forming a plurality of resonators on an upper surface of the membrane layer, depositing a mask layer on a lower surface of the membrane layer and patterning the mask layer to form a plurality of main windows and sub windows, and forming cavities along the main windows in the substrate and forming sub walls in the cavities in such a way that the sub walls are separated apart from the membrane layer by using the notch effect caused during a dry etching. It is possible to precisely form cavities with desired sizes even if the cavities have different sizes, to reduce the notched areas in the cavities, to reduce the total size of the filter by decreasing a distance between the cavities and to reduce the total length of wires.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: February 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seog-woo Hong, Byeong-ju Ha, In-sang Song, Kyu-sik Kim
  • Publication number: 20090315201
    Abstract: A method of fabricating micro-lenses is provided. A first layer is formed on a substrate. The first layer is comprised of a first material and the substrate is comprised of a second material. An opening is formed in the first layer and an etchant is provided in the opening to etch both the substrate and the first layer to form a first mold for a first micro-lens. The etchant etches the first layer at a different rate than the substrate. A lens material is added to the etched molds to form micro-lenses.
    Type: Application
    Filed: July 13, 2009
    Publication date: December 24, 2009
    Inventor: Jin Li
  • Patent number: 7607227
    Abstract: A method of manufacturing a printhead includes providing a polymeric substrate having a surface; providing a patterned material layer on the surface of the polymeric substrate; and removing at least some of the polymeric substrate not covered by the patterned material layer using an etching process.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: October 27, 2009
    Assignee: Eastman Kodak Company
    Inventors: Kathleen M. Vaeth, Constantine N. Anagnostopoulos, John A. Lebens
  • Patent number: 7592265
    Abstract: A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: September 22, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Meng-Jun Wang, Yi-Hsing Chen, Min-Chieh Yang, Jiunn-Hsiung Liao
  • Patent number: 7587810
    Abstract: A mask structure for fabricating a write pole for a perpendicular write head. The mask structure includes a first and second hard mask structures separated by an image transfer layer, such as DURAMIDE®. The first mask structure may be a bi-layer mask structure that functions as a CMP stop as well as a hard mask for ion milling. The first hard mask is chosen to have a desired resistance to removal by ion milling to maintain excellent track width control during an ion milling process used to form the write pole. Therefore, the first hard mask may be comprises of two layers selected from the group consisting of Rh, alumina, and diamond like carbon (DLC). The second hard mask is constructed of a material that functions as a bottom antireflective coating as well as a hard mask.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: September 15, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventor: Quang Le
  • Patent number: 7587809
    Abstract: A magnetoresistive reader having a sensor, current contacts with low parasitic resistance and a top shield with substantially planar topology is fabricated by first defining a stripe height back edge of the sensor. Next, a reader width of the sensor is defined. The current contacts are deposited to a thickness such that a top surface of the current contacts is substantially level with a top surface of the sensor. The top shield is deposited over the sensor and the current contacts. Defining the stripe height back edge prior to the reader width results in current contacts with low parasitic resistance and inhibits the formation of magnetic domains in the top shield.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: September 15, 2009
    Assignee: Seagate Technology LLC
    Inventors: Dimitar V. Dimitrov, Daniel P. Burbank, Paul E. Anderson, Richard P. Larson, Kenneth P. Naughton, Insik Jin
  • Patent number: 7589026
    Abstract: A method for fabricating a fine pattern in a semiconductor device includes forming a first polymer layer and a second polymer layer over an etch target layer. The second polymer layer is patterned at a first substrate temperature. The first polymer layer is etched at a second substrate temperature using an etch gas that does not include oxygen (O2). The first polymer layer is etched using the patterned second polymer layer as an etch mask. The etch target layer is then etched using the etched first polymer layer and the etched second polymer layer as an etch mask.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: September 15, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Kwon Lee, Jae-Young Lee
  • Patent number: 7585424
    Abstract: This invention provides a pattern reversal process for self aligned imprint lithography (SAIL). The method includes providing a substrate and depositing at least one layer of material upon the substrate. A pattern is then established upon the layer of material, the pattern providing at least one exposed area and at least one covered area of the layer of material. The exposed areas are treated to toughen the material and reverse the pattern. Subsequent etching removes the un-toughened material. A thin-film transistor device provided by the pattern reversal process is also provided.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: September 8, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Ping Mei
  • Patent number: 7585423
    Abstract: A liquid discharge head includes, on a same substrate, pressure generating chambers, nozzle apertures communicating with the pressure generating chambers through nozzle communicating pans, and a reservoir, wherein a cross-section area of the nozzle communicating part is larger, along a direction parallel to a nozzle aperture face of the substrate, than a cross-section area of the nozzle aperture, and the cross-section area of the nozzle aperture in such direction remains constant over the entire length of the nozzle aperture.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: September 8, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Koichiro Nakanishi
  • Patent number: RE41697
    Abstract: A method of forming a planarized photoresist coating on a substrate having holes with different duty ratios is described. A first photoresist preferably comprised of a Novolac resin and a diazonaphthoquinone photoactive compound is coated on a substrate and baked at or slightly above its Tg so that it reflows and fills the holes. The photoresist is exposed without a mask at a dose that allows the developer to thin the photoresist to a recessed depth within the holes. After the photoresist is hardened with a 250° C. bake, a second photoresist is coated on the substrate to form a planarized film with a thickness variation of less than 50 Angstroms between low and high duty ratio hole regions. One application is where the second photoresist is used to form a trench pattern in a via first dual damascene method. Secondly, the method is useful in fabricating MIM capacitors.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: September 14, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chia-Tung Ho, Feng-Jia Shih, Jieh-Jang Chen, Ching-Sen Kuo, Shih-Chi Fu, Gwo-Yuh Shiau, Chia-Shiung Tsai