Mask Is Multilayer Resist Patents (Class 216/47)
  • Patent number: 8470189
    Abstract: In the present invention, provided is a method of forming a mask pattern by which a fine thin film pattern may be formed more easily with higher resolution and precision. In the method of forming a mask pattern, a photoresist pattern having an opening is formed on a substrate, then, an inorganic film is formed so as to cover the upper surface of the photoresist pattern and the inside of the opening, then the inorganic film on the upper surface of the photoresist pattern is removed by a dry etching process. Subsequently, an inorganic mask pattern is formed by removing the photoresist pattern. The inorganic mask pattern thus formed hardly produces an issue of deformation such as physical displacement even when it is heated in the dry etching process.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: June 25, 2013
    Assignee: TDK Corporation
    Inventors: Akifumi Kamijima, Hideyuki Yatsu, Hitoshi Hatate
  • Patent number: 8461053
    Abstract: A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: June 11, 2013
    Assignee: Spansion LLC
    Inventors: Tung-Sheng Chen, Shenqing Fang
  • Patent number: 8454847
    Abstract: A method of lifting off includes forming a first material layer on a substrate; forming a photoresist pattern including first and second holes and on the first material layer; patterning the first material layer using the photoresist pattern as a patterning mask to form a material pattern having first and second grooves within the material pattern, the first and second grooves corresponding to the first and second holes, respectively; forming a second material layer on an entire surface of the substrate including the photoresist pattern and the first and second grooves; and removing the photoresist pattern and the second material layer on the photoresist pattern at the same time, wherein a portion of the material pattern between the first and second grooves and portions of the material pattern at sides of the first and second grooves constitute a line as a whole.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: June 4, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Hee-Young Kwack, Hyun-Seok Hong, Joo-Soo Lim, Hong-Sik Kim
  • Publication number: 20130126472
    Abstract: Disclosed is a substrate with an adhesive auxiliary layer having an organic compound layer provided on a substrate, with an adhesive auxiliary layer to be interposed between the substrate and the organic compound layer wherein one molecule of a compound contained in the adhesive auxiliary layer includes an adsorption functional group and an adhesion promoting functional group, the adsorption functional group is composed of a modified silane group which is mainly bonded to the substrate, and the adhesion promoting functional group promotes and increases adhesion mainly to the organic compound layer.
    Type: Application
    Filed: June 10, 2011
    Publication date: May 23, 2013
    Applicant: HOYA CORPORATION
    Inventor: Kota Suzuki
  • Patent number: 8444867
    Abstract: A method for forming patterns on a wafer includes forming a fence having a sloped face in an edge portion of the wafer. The sloped face is direct to an inside of the wafer. A first photoresist layer is formed which extends to cover the fence on the wafer. First photoresist patterns are formed by performing a first exposure and development on the first photoresist layer. An etch process is performed using the first photoresist patterns and the fence as an etch mask. The fence is formed by selectively exposing a negative resist using a light shielding blade, and at this time, the first photoresist layer is formed including a positive resist.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: May 21, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyun Jo Yang
  • Publication number: 20130105441
    Abstract: Provided is a mask blank which is used for manufacturing an imprinting mold and which may form a fine mold pattern with high pattern accuracy. A mask blank (10) includes a transparent substrate (1) and a thin film (2) contacted with a surface of the substrate. The thin film (2) includes a laminated film including an upper layer (4) which is composed of a material containing silicon (Si) or a material containing tantalum (Ta), and a lower layer (3) which is composed of a material containing at least one of hafnium (Hf) and zirconium (Zr) and containing substantially no oxygen.
    Type: Application
    Filed: April 4, 2011
    Publication date: May 2, 2013
    Applicant: HOYA CORPORATION
    Inventors: Osamu Nozawa, Masahiro Hashimoto
  • Publication number: 20130108833
    Abstract: A stack of a hard mask layer, a soft mask layer, and a photoresist is formed on a substrate. The photoresist is patterned to include at least one opening. The pattern is transferred into the soft mask layer by an anisotropic etch, which forms a carbon-rich polymer that includes more carbon than fluorine. The carbon-rich polymer can be formed by employing a fluorohydrocarbon-containing plasma generated with fluorohydrocarbon molecules including more hydrogen than fluorine. The carbon-rich polymer coats the sidewalls of the soft mask layer, and prevents widening of the pattern transferred into the soft mask. The photoresist is subsequently removed, and the pattern in the soft mask layer is transferred into the hard mask layer. Sidewalls of the hard mask layer are coated with the carbon-rich polymer to prevent widening of the pattern transferred into the hard mask.
    Type: Application
    Filed: October 26, 2011
    Publication date: May 2, 2013
    Applicants: ZEON CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Sebastian U. Engelmann, Nicholas C. M. Fuller, Michael A. Guillorn, Hiroyuki Miyazoe, Masahiro Nakamura
  • Publication number: 20130087529
    Abstract: There is disclosed A resist underlayer film composition, the resist underlayer film composition contains a truxene compound having a substituted or an unsubstituted naphthol group as shown by the following general formula (1). There can be provided a resist underlayer film composition to form a resist underlayer film being capable of reducing reflectance and having high etching resistance, heat resistance.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 11, 2013
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Shin-Etsu Chemical Co., Ltd.
  • Patent number: 8404600
    Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: March 26, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej Sandhu
  • Patent number: 8394280
    Abstract: Methods of patterning a material are disclosed. A first resist pattern is formed on a field. A protective layer is formed over the first resist pattern and at least a portion of the field. A second resist pattern is formed over a portion of the protective layer. A portion of a material to be patterned deposited adjacent to the first and second resist patterns is removed.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: March 12, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Dujiang Wan, Hai Sun, Hongping Yuan, Ling Wang, Xianzhong Zeng
  • Patent number: 8394722
    Abstract: A method for controlling critical dimension (CD) of etch features in an etch layer disposed below a functionalized organic mask layer disposed below an intermediate mask layer, disposed below a patterned photoresist mask, which forms a stack is provided. The intermediate mask layer is opened by selectively etching the intermediate mask layer with respect to the patterned photoresist mask. The functionalized organic mask layer is opened. The functionalized organic mask layer opening comprises flowing an open gas comprising COS, forming a plasma, and stopping the flowing of the open gas. The etch layer is etched.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: March 12, 2013
    Assignee: Lam Research Corporation
    Inventors: Gerardo A. Delgadino, Robert C. Hefty
  • Patent number: 8379311
    Abstract: A micro-lens array and a method for fabricating a micro-lens includes forming a first lens formation material layer on and/or over a micro-lens formation area of a semiconductor substrate, and then forming a portion of the lens formation material layer as a first micro-lens using a first mask. A second lens formation material layer is formed adjacent to the first micro-lens on and/or over the micro-lens formation area. The second lens formation material layer is also formed as a second micro-lens using a second mask which is a different type from that of the first mask.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: February 19, 2013
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Young Je Yun, Jin Ho Park
  • Publication number: 20130032569
    Abstract: Disclosed herein is a method of fabricating a cliché capable of preventing a printing roller from touching a bottom surface of the cliché. The method of fabricating the cliché includes forming a mask thin film pattern having a multilayer structure and a photoresist pattern on a base substrate, forming a resistant reinforcement inducing layer to cover the photoresist pattern, thereby transforming the photoresist pattern into a resistant reinforced photoresist pattern, and forming groove patterns having different depths from each other by etching the base substrate using the resistant reinforced photoresist pattern and the mask thin film pattern having the multilayer structure as masks.
    Type: Application
    Filed: July 23, 2012
    Publication date: February 7, 2013
    Inventors: Jun-Hee Lee, Jeong-Hoon Lee
  • Publication number: 20130026133
    Abstract: Techniques for minimizing or eliminating pattern deformation during lithographic pattern transfer to inorganic substrates are provided. In one aspect, a method for pattern transfer into an inorganic substrate is provided. The method includes the following steps. The inorganic substrate is provided. An organic planarizing layer is spin-coated on the inorganic substrate. The organic planarizing layer is baked. A hardmask is deposited onto the organic planarizing layer. A photoresist layer is spin-coated onto the hardmask. The photoresist layer is patterned. The hardmask is etched through the patterned photoresist layer using reactive ion etching (RIE). The organic planarizing layer is etched through the etched hardmask using RIE. A high-temperature anneal is performed in the absence of oxygen. The inorganic substrate is etched through the etched organic planarizing layer using reactive ion etching.
    Type: Application
    Filed: July 27, 2011
    Publication date: January 31, 2013
    Applicant: International Business Machines Corporation
    Inventors: Sebastian Ulrich Engelmann, Martin Glodde, Michael A. Guillorn
  • Patent number: 8358010
    Abstract: A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer; realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: January 22, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Danilo Mascolo, Gianfranco Cerofolini
  • Patent number: 8349200
    Abstract: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: January 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shi-Yong Yi, Myeong-Cheol Kim, Dong-Ki Yoon, Kyung-Yub Jeon, Ji-Hoon Cha
  • Patent number: 8349195
    Abstract: A method and system provide a magnetoresistive structure from a magnetoresistive stack that includes a plurality of layers. The method and system include providing a mask that exposes a portion of the magnetoresistive stack. The mask has at least one side, a top, and a base at least as wide as the top. The method and system also include removing the portion of the magnetoresistive stack to define the magnetoresistive structure. The method and system further include providing an insulating layer. A portion of the insulating layer resides on the at least one side of the mask. The method and system further include removing the portion of the insulating layer on the at least one side of the mask and removing the mask.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: January 8, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Weimin Si, Liubo Hong, Honglin Zhu, Winnie Yu, Rowena Schmidt
  • Patent number: 8343364
    Abstract: A method of forming a near field transducer (NFT) for energy assisted magnetic recording is disclosed. A structure comprising an NFT metal layer and a first hardmask layer over the NFT metal layer is provided A first patterned hardmask is formed from the first hardmask layer, the first patterned hardmask disposed over a disk section and a pin section of the NFT to be formed. An etch process is performed on the NFT metal layer via the first patterned hardmask, the etch process forming the NFT having the disk section and the pin section.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: January 1, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Wei Gao, Guanxiong Li, Zhongyan Wang, Yufeng Hu, Ge Yi
  • Patent number: 8337712
    Abstract: A method for forming an etching mask comprises irradiating a focused ion beam onto a surface of a substrate and forming an etching mask used for oblique etching including an ion containing portion in the irradiated region. A method for fabricating a three-dimensional structure comprises preparing a substrate, irradiating a focused ion beam onto a surface of the substrate and forming an etching mask including an ion-containing portion in the irradiated region, and dry-etching the substrate from a diagonal direction using the etching mask and forming a plurality of holes.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: December 25, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Tamamori, Masahiko Okunuki, Shinan Wang, Taiko Motoi, Haruhito Ono, Toshiaki Aiba
  • Patent number: 8329051
    Abstract: A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: December 11, 2012
    Assignee: Lam Research Corporation
    Inventors: Qian Fu, Hyun-Yong Yu
  • Patent number: 8308966
    Abstract: A method for performing a double pattering process of a semiconductor device is provided. The method includes forming a hard mask layer having a stack structure of a first layer, a second layer and a third layer in sequence, forming a first photoresist pattern over the hard mask layer, etching the third layer to form third layer patterns by using the first photoresist pattern as an etch barrier, forming a second photoresist pattern over the third layer patterns, etching the second layer to form second layer patterns by using the second photoresist pattern and the third layer patterns as an etch barrier, removing the second photoresist pattern, and etching the first layer to form first layer patterns by using the second layer patterns as an etch barrier.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: November 13, 2012
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Jun-Hyeub Sun, Shi-Young Lee, Jong-Sik Bang, Sang-Min Ju
  • Patent number: 8298430
    Abstract: This etching method comprises the steps of forming first and second hard masks made of materials different from each other successively on a magnetoresistive film; forming a resist having a lower face opposing a front face of the second hard mask, a space being interposed between the front face and lower face; dry-etching the second hard mask by using the resist as a mask; etching the first hard mask by using the etched second hard mask; and etching the magnetoresistive film by using the first hard mask.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: October 30, 2012
    Assignee: TDK Corporation
    Inventor: Kosuke Tanaka
  • Patent number: 8298960
    Abstract: A plasma etching method, for plasma-etching a target substrate including at least a film to be etched, an organic film to become a mask of the to-be-etched film, and a Si-containing film which are stacked in order from bottom, includes the first organic film etching step, the treatment step and the second organic film etching step when the organic film is etched to form a mask pattern of the to-be-etched film. In the first organic film etching step, a portion of the organic film is etched. In the treatment step, the Si-containing film and the organic film are exposed to plasma of a rare gas after the first organic film etching step. In the second organic film etching step, the remaining portion of the organic film is etched after the treatment step.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: October 30, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Masahiro Ogasawara, Sungtae Lee
  • Patent number: 8282847
    Abstract: A method for etching an etch layer formed on a substrate is provided. A first photoresist (PR) mask with first mask features is provided on the etch layer. A protective coating is provided on the first PR mask by a process including at least one cycle. Each cycle includes (a) a deposition phase for depositing a deposition layer over the surface of the first mask features using a deposition gas, and (b) a profile shaping phase for shaping the profile of the deposition layer using a profile shaping gas. A liquid PR material is applied over the first PR mask having the protective coating. The PR material is patterned into a second mask features, where the first and second mask features form a second PR mask. The etch layer is etched though the second PR mask.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: October 9, 2012
    Assignee: Lam Research Corporation
    Inventors: Andrew R. Romano, S. M. Reza Sadjadi
  • Patent number: 8273258
    Abstract: A disclosed fine pattern forming method includes steps of: forming patterns made of a first photoresist film, arranged at a first pitch on a film; trimming the patterns made of the first photoresist film; depositing a protection film on the patterns made of the first photoresist film on the trimmed patterns made of the first photoresist film, the protection film being made of reaction products of an etching gas, thereby obtaining first patterns; forming other patterns made of a second photoresist film, arranged at a second pitch, on the protection film, the other patterns made of the second photoresist film being shifted by half of the first pitch from the corresponding patterns made of the first photoresist film; trimming the other patterns made of the second photoresist film into second patterns; and etching the film using the first patterns and the second patterns.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: September 25, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Takashi Sone, Eiichi Nishimura
  • Patent number: 8252192
    Abstract: A method of pattern etching a thin film on a substrate is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a dielectric layer formed on the substrate and a mask layer formed above the dielectric layer. A pattern is created in the mask layer, and the pattern is transferred from the mask layer to the dielectric layer by performing a plasma etching process. While transferring the pattern to the dielectric layer, the mask layer is substantially removed using the plasma etching process. The plasma etching process can use a process gas comprising a first gaseous component that etches the dielectric layer at a greater rate than the mask layer, and a second gaseous component that etches the dielectric layer at a lesser rate than the mask layer.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: August 28, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Yao-Sheng Lee, Vaidyanathan Balasubramaniam, Masaru Nishino, Kelvin Zin
  • Patent number: 8241512
    Abstract: A method of forming an ion implantation mask includes forming a field area on a semiconductor substrate, forming an amorphous carbon layer on the semiconductor substrate, forming a hard mask layer on the amorphous carbon layer, forming an etching mask pattern on the hard mask layer, and etching the hard mask layer and the amorphous carbon layer to expose the field area through the etching mask pattern, wherein etching the hard mask layer and the amorphous carbon layer forms a hard mask layer pattern and an amorphous carbon layer pattern.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: August 14, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Woo Lee, Young-Mi Lee, Min-Chul Chae, Dae-Joung Kim, Jae-Seung Hwang
  • Patent number: 8236700
    Abstract: A method of pattern etching a Si-containing anti-reflective coating (ARC) layer is described. The method comprises etching a feature pattern into the silicon-containing ARC layer using plasma formed from a process gas containing SF6 and a hydrocarbon gas. The method further comprises adjusting a flow rate of the hydrocarbon gas relative to a flow rate of the SF6 to reduce a CD bias between a final CD for nested structures in the feature pattern and a final CD for isolated structures in the feature pattern.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: August 7, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Christopher Cole, Akiteru Ko
  • Patent number: 8221636
    Abstract: A magnetic head includes a pole layer, and an encasing layer having a groove that accommodates the pole layer. A manufacturing method for the magnetic head includes the steps of forming a nonmagnetic layer that will later undergo formation of the groove therein and will thereby become the encasing layer; forming the groove in the nonmagnetic layer so that the nonmagnetic layer becomes the encasing layer; and forming the pole layer such that the pole layer is accommodated in the groove of the encasing layer. The nonmagnetic layer is formed of Al2O3. The step of forming the groove in the nonmagnetic layer includes the step of taper-etching the nonmagnetic layer by reactive ion etching with an etching gas containing at least BCl3 and N2 among BCl3, Cl2 and N2.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: July 17, 2012
    Assignee: Headway Technologies, Inc.
    Inventors: Yoshitaka Sasaki, Hiroyuki Itoh, Hironori Araki, Shigeki Tanemura, Kazuo Ishizaki, Takehiro Horinaka
  • Patent number: 8216949
    Abstract: A method lor integrated circuit fabrication is disclosed. A spacer pattern is provided including a plurality ot spacers in an array region of a partially-fabricated integrated circuit. Each spacer is at least partly defined by opposing open volumes extending along lengths of the spacers. A pattern is subsequently defined in a periphery region of the partially-fabricated integrated circuit. A consolidated pattern is formed by concurrently transferring the spacer pattern and the pattern in the periphery region into an underlying masking layer. The consolidated pattern is transferred to an underlying substrate.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: July 10, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Mirzafer K Abatchev, Gurtej Sandhu, Luan Tran, William T Rericha, D. Mark Durcan
  • Patent number: 8216483
    Abstract: A super water repellent surface is prepared by arranging plural spherical beads on a substrate surface to form a (N)-th bead layer, etching the substrate surface with the (N)-th bead layer as an etching mask, arranging plural spherical beads, which are larger than the (N)-th beads in diameter, on the substrate surface to form a (N+1)-th bead layer, etching the substrate surface with the (N+1)-th bead layer as an etching mask, removing the beads from the etched substrate surface and coating a fluorine compound on the substrate surface on which a hierarchical concavo-convex structure has been formed. The (N+1)-th bead layer forming step and the (N+1)-th etching step are repeated N times.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: July 10, 2012
    Assignee: Korea Institute of Machinery and Materials
    Inventors: Hyun Eui Lim, Dae Hwan Jung, Jung Hyun Noh, Wan Doo Kim
  • Patent number: 8216485
    Abstract: A plasma etching method etches an organic film formed on a target substrate by using a plasma of a processing gas via a silicon-containing mask. The processing gas is a gaseous mixture of an oxygen-containing gas, a rare gas and a carbon fluoride gas. A computer-executable control program controls a plasma etching apparatus to perform the plasma etching method. A computer-readable storage medium stores therein a computer-executable control program.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: July 10, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Yoshimitsu Kon, Yoshinobu Hayakawa
  • Patent number: 8206605
    Abstract: A substrate processing method capable of preventing a reduction in productivity of the fabrication of a semiconductor device from a substrate. An HF gas is supplied toward a wafer having a thermally-oxidized film, a BPSG film, and a deposit film, to thereby selectively etch the BPSG film and the deposit film using fluorinated acid. A residual matter of H2SiF6 produced at the time of etching is decomposed into HF and SiF4 by being heated.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: June 26, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Daisuke Hayashi
  • Publication number: 20120125848
    Abstract: A mechanical particle filter comprises a membrane having a plurality of pores. At least one partial region of the surface of the membrane, that is accessible for the medium to be filtered, includes a carbon material having a diamond structure.
    Type: Application
    Filed: July 22, 2009
    Publication date: May 24, 2012
    Applicant: EADS DEUTSCHLAND GMBH
    Inventors: Alois Friedberger, Peter Gluche, Helmut Seidel
  • Publication number: 20120111832
    Abstract: Methods for forming an imprint lithography template are provided. Materials for forming the imprint lithography template may be etched at different rates based on physical properties of the layers. Additionally, reflectance of the materials may be monitored to provide substantially uniform erosion of the materials.
    Type: Application
    Filed: January 18, 2012
    Publication date: May 10, 2012
    Applicant: MOLECULAR IMPRINTS, INC.
    Inventors: Gary F. Doyle, Gerard M. Schmid, Michael N. Miller, Douglas J. Resnick, Dwayne L. LaBrake
  • Publication number: 20120112385
    Abstract: Methods of making nano-scale structures with geometric cross-sections, including convex or non-convex cross-sections, are described. The approach may be used to directly pattern substrates and/or create imprint lithography templates or molds that may be subsequently used to directly replicate nano-shaped patterns into other substrates, such as into a functional or sacrificial resist to form functional nanoparticles.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 10, 2012
    Applicants: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM, MOLECULAR IMPRINTS, INC.
    Inventors: Sidlgata V. Sreenivasan, Vikramjit Singh, Frank Y. Xu, Byung-Jin Choi
  • Patent number: 8173029
    Abstract: According to one embodiment, a cured first ultraviolet-curing resin material layer having a first three-dimensional pattern is formed on a first principal surface of a magnetic recording medium having a central hole. A cured second ultraviolet-curing resin material layer having a second three-dimensional pattern is formed on a second principal surface opposite to the first principal surface of the magnetic recording.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: May 8, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Morita, Shinobu Sugimura, Kazuyo Umezawa, Masatoshi Sakurai
  • Patent number: 8158528
    Abstract: A method for forming a pattern of a semiconductor device comprises: forming a stacked film including an underlying layer, an antireflection film and a photoresist film over a semiconductor substrate; coating an over-coating composition over the photoresist film to form an over-coating film; performing an exposing and developing process with a cell mask on the photoresist film where the over-coating film is formed to form a photoresist pattern; forming a silicon-containing-RELACS layer over the antireflection film including the photoresist pattern where the over-coating film is formed; removing the over-coating film and the silicon containing RELACS layer on the photoresist pattern to form a spacer of the silicon containing RELACS layer at sidewalls of the photoresist pattern; removing the photoresist pattern; and etching the antireflection film and the underlying layer with the spacer of the silicon containing RELACS layer as a mask to form an antireflection pattern and an underlying pattern.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: April 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Koo Lee
  • Patent number: 8137569
    Abstract: A method of fabricating a membrane having a tapered pore, a polymeric membrane having a tapered pore, and uses of such polymeric membrane are disclosed. The membrane includes apertures of increasing diameter which are aligned with each other to form the tapered pore.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: March 20, 2012
    Assignees: Sony Deutschland GmbH, Oxford Nanopore Technologies Limited
    Inventors: Oliver Harnack, Jurina Wessels, Akio Yasuda, James Clarke, Terry Reid
  • Patent number: 8137641
    Abstract: A method of making a microfluidic module is disclosed that includes forming a fluid flow channel in a self-bonding rebondable polyimide film to provide a channel sheet, the self-bonding rebondable polyimide film having a first mask layer self-bonded thereto; removing the first mask layer from the channel sheet after forming the fluid flow channel; and self-bonding the surface of the channel sheet exposed by removal of the first mask layer to a cover sheet.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: March 20, 2012
    Assignee: YSI Incorporated
    Inventor: Donald R. Moles
  • Patent number: 8133818
    Abstract: In a method of forming a hard mask pattern in a semiconductor device, only processes for forming patterns having a row directional line shape and a column directional line shape on a plane are performed so that the hard mask patterns can be formed to define densely disposed active regions. A pitch of the hard mask patterns is less than a resolution limit of an exposure apparatus.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: March 13, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Woo Yung Jung
  • Patent number: 8123968
    Abstract: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: February 28, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Jingyi Bai, Gurtej S Sandhu, Shuang Meng
  • Patent number: 8119528
    Abstract: A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state, whereby a reduced amount of current is employed, and wherein the plurality of nanoscale electrodes, when present, have substantially the same dimensions.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Alejandro G Schrott, Eric A Joseph, Mary Beth Rothwell, Matthew J Breitwisch, Chung H Lam, Bipin Rajendran, Sarunya Bangsaruntip
  • Patent number: 8105950
    Abstract: A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer and a second hard mask layer over an etch target layer, forming second hard mask patterns by etching the second hard mask layer, wherein an etching profile of the second hard mask layer has a positive slope, and etching the first hard mask layer and the etch target layer using the second hard mask patterns as an etch mask.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: January 31, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Yoon Cho, Hye-Ran Kang
  • Patent number: 8097177
    Abstract: Providing a piezoelectric vibrating reed which is capable of decreasing variation in the amount of etching residue as much as possible and suppressing influence of vibration loss on the vibration characteristics as much as possible.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: January 17, 2012
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Kobayashi
  • Patent number: 8097176
    Abstract: Methods, materials, and systems for texturizing mold surfaces is disclosed. In one method and system of the invention, a first step involves generating a graphics file of a desired texture pattern. The graphics file is subsequently output to an ink jet printer, which is configured to print using an acid-etch resist ink. The acid-etch resist ink is formulated to provide optimal properties for ink-jet printing, while also providing excellent acid-etch resist and superior handling properties. The acid-etch resist ink is printed onto a sheet of a carrier substrate that allows the acid-etch resist to be transferred to a mold surface, after which the mold surface is etched with a strong acid.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: January 17, 2012
    Assignee: Ikonics Corporation
    Inventors: Toshifumi Komatsu, Jeremy W. Peterson, Alexander S. Gybin
  • Patent number: 8083958
    Abstract: Disclosed are embodiments of a lithographic patterning method that incorporates a combination of photolithography and self-assembling copolymer lithography techniques in order to create, on a substrate, a grid-pattern mask having multiple cells, each with at least one sub-50 nm dimension. The combination of different lithographic techniques further allows for precise registration and overlay of the individual grid-pattern cells with corresponding structures within the substrate. The resulting grid-pattern mask can then be used, in conjunction with directional etch and other processes, to extend the cell patterns into the substrate and, thereby form openings, with at least one sub-50 nm dimension, landing on corresponding in-substrate structures. Once the openings are formed, additional structures can be formed within the openings.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wai-Kin Li, Haining S. Yang
  • Patent number: 8084366
    Abstract: A method of making a device includes forming a device layer, forming an organic hard mask layer over the device layer, forming a first oxide hard mask layer over the organic hard mask layer, forming a DARC layer over the first oxide hard mask layer, forming a photoresist layer over the DARC layer, patterning the photoresist layer to form a photoresist pattern, and transferring the photoresist pattern to the device layer using the DARC layer, the first oxide hard mask layer and the organic hard mask layer.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: December 27, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Michael Chan, Usha Raghuram
  • Patent number: 8070971
    Abstract: An improved method of etching a structure and a structure etched by the method is disclosed. The bottom side of a leadframe of an IC-package is an example of a structure, which advantageously may be etched with the disclosed method. The method includes the steps of providing an etch mask to the substrate to be etched. The etch mask comprising at least two sub-mask: a first sub-mask covering the area which substantially should remain after the etching process, and a second sub-mask covering an area to be removed in the etching process. The second sub-mask is a sacrificial mask in the form of a grid. The presence of the second sub-mask increases the etching speed in the area covered by it.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: December 6, 2011
    Assignee: NXP B.V.
    Inventors: Jan Kloosterman, Paul Dijkstra
  • Patent number: 8071484
    Abstract: There are provided a method of forming a fine pattern employing self-aligned double patterning. The method includes providing a substrate. First mask patterns are formed on the substrate. A reactive layer is formed on the substrate having the first mask patterns. The reactive layer adjacent to the first mask patterns is reacted using a chemical attachment process, thereby forming sacrificial layers along outer walls of the first mask patterns. The reactive layer that is not reacted is removed to expose the sacrificial layers. Second mask patterns are formed between the sacrificial layers adjacent to sidewalls of the first mask patterns facing each other. The sacrificial layers are removed to expose the first and second mask patterns and the substrate exposed between the first and second mask patterns. The substrate is etched using the first and second mask patterns as an etching mask.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: December 6, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Mi Kim, Jae-Ho Kim, Young-Ho Kim, Myung-Sun Kim, Youn-Kyung Wang, Mi-Ra Park