Abstract: Siloxane polymer compositions and methods of manufacturing a capacitor are described. In some embodiments, a mold layer pattern is formed on a substrate having a conductive structure, and the mold layer pattern has an opening to expose the conductive structure. A conductive layer is formed on the substrate. A buffer layer pattern is formed on the conductive layer formed in the opening. The buffer layer pattern includes a siloxane polymer represented by the following Chemical Formula 1. The conductive layer is selectively removed to form a lower electrode. The mold layer pattern and the buffer layer pattern are removed. A dielectric layer and an upper electrode are formed on the substrate to form a capacitor. The methods may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.

Abstract: In accordance with the present invention, a novel method to fabricate topological capacitors is provided. The fabrication method of the instant invention is based upon a reversed surface topology utilizing deep reactive ion etching to establish conductive capacitive elements and non-conductive capacitive element groups.

Abstract: The present invention discloses a micro-electro-mechanical system (MEMS) device, comprising: a mass including a main body and two capacitor plates located at the two sides of the main body and connected with the main body, the two capacitor plates being at different elevation levels; an upper electrode located above one of the two capacitor plates, forming one capacitor therewith; and a lower electrode located below the other of the two capacitor plates, forming another capacitor therewith, wherein the upper and lower electrodes are misaligned with each other in a horizontal direction.

Abstract: A method for manufacturing a wiring board which can simplify a manufacturing step. In a preparation step, a core board and an electronic component are prepared. In an insulating layer formation and fixing step, after accommodating the electronic component in an accommodation hole, a lowermost resin insulating layer is formed, and a gap between the electronic component and the core board is filled with a part of the lowermost resin insulating layer so as to fix the electronic component to the core board. In an opening portion formation step, a portion of the lowermost resin insulating layer located directly above the gap between the electronic component and the core board is removed so as to form an opening portion exposing a part of a core board main surface side conductor and a component main surface side electrode.

Abstract: A method of etching a foil for use in an electrolytic capacitor utilizes a nanoimprinted optic to control the etch pattern. The optic is formed by creating a self-assembled monolayer (SAM) of hemispheres onto the surface of an optical quartz substrate. A laser is directed onto the optic while the foil underlies the optic, and the concentrated light source is used to effectively image an array of submicron spots. The resulting spots allow for controlled initiation of etch tunnels during a subsequent electrochemical etch of the foil, with the purpose of ultimately increasing foil capacitance through the increased surface area.

Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.

Abstract: A multi-layer film-stack and method for forming the multilayer film-stack is given where a series of alternating layers of conducting and dielectric materials are deposited such that the conducting layers can be selectively addressed. The use of the method to form integratable high capacitance density capacitors and complete the formation of an integrated power system-on-a-chip device including transistors, conductors, inductors, and capacitors is also given.

Abstract: A chip carrier substrate includes a capacitor aperture and a laterally separated via aperture, each located within a substrate. The capacitor aperture is formed with a narrower linewidth and shallower depth than the via aperture incident to a microloading effect within a plasma etch method that is used for simultaneously etching the capacitor aperture and the via aperture within the substrate. Subsequently a capacitor is formed and located within the capacitor aperture and a via is formed and located within the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be contiguous with respect to the capacitor aperture and the via aperture.

Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.

Abstract: There are provided an upper electrode 18 and a lower electrode which are formed like flat plates, a dielectric layer interposed between the upper electrode and the lower electrode, and a covering portion which covers an external surface of at least one of the upper electrode and the lower electrode and is formed by an insulating resin. At least one of the upper electrode and the lower electrode is provided with at least one of opening holes having larger diameters than a via formed in a connection to a wiring pattern when a capacitor component is to be included in a substrate.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at % carbon. The method includes forming an opening through at least the support material where the opening has an aspect ratio of at least 20:1 within a thickness of the support material. After forming the opening, the method includes processing the support material to effect a reduction in conductivity, and forming a capacitor structure in the opening.

Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.

Abstract: The invention concerns a method for adjusting the operating gap of two mechanical elements of a substantially planar mechanical structure obtained by micro-etching. The method consists in attributing (A) to one of the elements (E) a fixed reference position (RF) in the direction of the residual gap separating said elements; connecting (C) the other element (OE) to the fixed reference position (RF) by an elastic link (S) and installing (D) between the fixed reference position (RF) and the other element (OE) at least a stop block defining an abutting gap, maximum displacement amplitude of the other element; subjecting (DE) the other element (OE) to a displacement antagonistic to the elastic link (S) up to the abutting position constituting the operating position, the residual gap being reduced to the difference between residual gap and abutting gap and less than the resolution of the micro-etching process. The invention is applicable to electromechanical resonators.

Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

Abstract: A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within the opening. The surface of the metal base is flush with the top surface of the semiconductor chip received in the opening. The resultant semiconductor device has a larger number of external pins and a smaller deformation without using a stiffener.

Abstract: A method of producing a highly etched electrode for a capacitor from a foil is disclosed. The method comprises first applying a composition to the foil to form a plurality of deposits on the foil surface. The method then includes heating the deposits to form micron-sized features and etching the foil. Preferably, the micron-sized features facilitate etching of the foil surface at the location of the micron-sized features. After etching, the foil is optionally further processed in a combination of optional steps such as widening, forming and finishing steps. The controlled application and heating of deposits on the foil surface allows for positional control of tunnel initiation during etching. Thus, the present invention relates to a method of controlling the etching of a foil, such that tunnel initiation density and the location of tunnel initiation is controlled.

Abstract: Disclosed is a PCB including an embedded capacitor and a method of fabricating the same. The long embedded capacitor is formed through an insulating layer, making a high capacitance and various capacitance designs possible.

Abstract: A method of producing a highly etched electrode for a capacitor from a foil is disclosed. The method comprises first applying a laser beam to the foil to form a plurality of marks on the foil surface and then etching the foil. Preferably, the laser marks facilitate etching of foil surface in areas near the marks and retard etching of foil surface inside the marks. After etching, the foil is further processed in a combination of optional steps such as forming and finishing steps. The laser marking of the foil allows for positional control of tunnel initiation, such that tunnel initiation density and the location of tunnel initiation is controlled. By controlling the position of tunnel initiation, foils are etched more uniformly and have optimum tunnel distributions, thus allows for the production of highly etched foils that maintain high strength and have high capacitance.

Abstract: There is provided a method for manufacturing a wiring board with built-in capacitors in which small high-frequency capacitors, decoupling capacitors, and EMI filter capacitors can be built with precision by using the same method.

Abstract: Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

Abstract: A method of preparing high capacity hydrous ruthenium oxide micro-ultracapacitors. A laser direct-write process deposits a film of hydrous ruthenium oxide in sulfuric acid under ambient temperature and atmospheric conditions. A dual laser process combining infrared and ultraviolet light is used for fabricating a complete wet electrochemical cell in a single processing step. Ultraviolet laser micromachining is used to tailor the shape and size of the deposited material into planar electrodes. The micro-ultracapacitors have improved size, weight, and cost efficiency and exhibit high specific power and high specific energy.

Abstract: In a method of forming a pattern and a method of forming a capacitor, an oxide layer pattern having an opening is formed on a substrate. A conductive layer is formed on the oxide layer pattern and the bottom and sidewalls of the opening. A buffer layer pattern is formed in the opening having the conductive layer, the buffer layer pattern including a siloxane polymer. The conductive layer on the oxide layer pattern is selectively removed using the buffer layer pattern as an etching mask. A conductive pattern having a cylindrical shape can be formed on the substrate. The method of forming a pattern may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.

Abstract: In a method of forming a pattern and a method of manufacturing a capacitor using the same, a conductive layer is formed on a mold layer having an opening. A first buffer layer pattern including a polymer having a repeating unit of anthracene-methyl methacrylate and a repeating unit of alkoxyl-vinyl benzene is formed on the conductive layer in the opening. The first buffer layer pattern is baked to cross-link the polymers and form a second buffer layer pattern that is insoluble in a developing solution. The conductive layer on a top portion of the mold layer is selectively removed by using the second buffer layer pattern as an etching mask. Accordingly, a conductive pattern for a semiconductor device is formed. The method of forming a pattern may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.

Abstract: In a method of forming a pattern, a mold layer having an opening is formed on a substrate. A conductive layer is formed on the mold layer having the opening, the conductive layer having a substantially uniform thickness. A buffer layer pattern is formed in the opening having the conductive layer, the buffer layer pattern having a cross-linked structure of water-soluble copolymers including a repeating unit of N-vinyl-2-pyrrolidone and a repeating unit of acrylate. An upper portion of the conductive layer exposed over the buffer layer pattern is etched. Accordingly, a conductive pattern for a semiconductor device is formed on the substrate. The method of forming a pattern may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.

Abstract: Capacitor foil includes a core layer, at least one porous layer and a porous surface layer, and a method for producing the same and an electrolytic capacitor. The at least one porous layer and the porous surface layer are porous as a result of a first DC-pulse etching process step. The method includes at least one further etching step in which the etching fluid of the first etching process step in the at least one porous layer and the porous surface layer is modified into or replaced by a filling substance having a low etching capability, at least the porous surface layer of the foil is further etched to increase the porosity of the porous surface layer, and the filling substance is removed from the foil.

Abstract: The present application is directed to novel electrostatic actuators and methods of making the electrostatic actuators. In one embodiment, the electrostatic actuator comprises a substrate, an electrode formed on the substrate and a deflectable member positioned in proximity to the electrode so as to provide a gap between the electrode and the deflectable member. The deflectable member is anchored on the substrate via one or more anchors. The gap comprises at least one first region having a first gap height positioned near the one or more anchors and at least one second region having a second gap height positioned farther from the anchors than the first region. The first gap height is smaller than the second gap height.

Abstract: A capacitive pressure sensing device comprising, a base member, a diaphragm member deflectable under an external pressure, a cantilever member disposed between the base member and the diaphragm member and supported on a support structure, wherein the base member and the cantilever member form a capacitor structure of the device and wherein deflection of the diaphragm member beyond a threshold value causes the cantilever member to deflect to cause a capacitive change in the capacitor structure.

Abstract: A micro-electro mechanical system (MEMS) device and a method of forming comb electrodes of the MEMS device are provided.

Abstract: A pixel electrode employs a transparent electrode made from indium-zinc-oxide (IZO) that is capable of preventing damage and bending thereof. In a liquid crystal display device containing pixel electrodes, the transparent electrode is made from indium-zinc-oxide (IZO) having an amorphous structure so that it can be etched within a short period of time with a low concentration of etchant. Accordingly, it is possible to prevent damage and bending of the transparent electrode upon the patterning thereof.

Abstract: One aspect of the invention relates to a method of cleaning high density capacitors. According to the method, the capacitors are cleaned with a plasma that includes fluorine-containing radicals. The plasma removes a small layer from the capacitors, including their sidewalls, and thereby removes surface contaminants. The method is effective even when the capacitors include hard-to-etch dielectric materials, such as tantalum and hafnium oxides. In a preferred embodiment, the plasma clean is combined with a solvent clean.

Abstract: The electrode configuration includes at least one structured layer. A mask is produced on the layer to be structured and the layer is dry etched. The mask is at least slightly etchable by dry etching. The mask contains a metal silicide, a metal nitride or a metal oxide.

Abstract: A method is disclosed of fabricating a MIMCAP (a capacitor (CAP) formed by successive layers of metal, insulator, metal (MIM)) and a thin film resistor at the same level. A method is also disclosed of fabricating a MIMCAP and a thin film resistor at the same level, and a novel integration scheme for BEOL (back-end-of-line processing) thin film resistors which positions them closer to FEOL (front-end-of-line processing) devices.

Abstract: According to a flexible thin film capacitor of the present invention, an adhesive film is formed on a substrate composed of at least one selected from the group consisting of an organic polymer and a metal foil, and an inorganic high dielectric film and metal electrode films are formed thereon. A metal oxide adhesive film can be used as the adhesive film. The adhesive film is formed in contact with the inorganic high dielectric film and at least one of the metal electrode films.

Abstract: A method of etching high dielectric constant materials (a material with a dielectric constant greater than 4) using a halogen gas, reducing gas, and passivating gas chemistry. An embodiment of the method is accomplished using chlorine, carbon monoxide, and nitrogen to etch and passivate a hafnium dioxide layer.

Abstract: In one aspect, a method of manufacturing a capacitor includes disposing one or more conductive layers of a first electrode stack in a recess of an alignment mechanism, where the recess is positioned relative to two or more alignment elements. The method further includes placing a separator over the one or more conductive layers where an outer edge of the separator contacts the two or more alignment elements. In one embodiment, a capacitor includes anode and cathode foils having offsetting edge portions. In one embodiment, a multiple tab cathode for a flat capacitor. A plurality of cathode tabs are portioned into a plurality of cathode tab groups positioned in different locations along the edge of the capacitor stack to reduce the amount of space required for connecting and routing the cathode tabs.

Abstract: A method for treating the surface of a stainless steel product for a fuel cell containing, in wt %, 0.15% or less of C, 17 to 36% of Cr, 0.005 to 3.5% of B, which comprises the first step of forming in advance a passive film with an oxidizing acid on the surface of the stainless steel product, the second step of allowing an aqueous acid solution to corrode the passive film, to thereby project one or more of a M23C6 type carbide, a M23(C, B)6 type borocarbide and M2B type boride, which are inclusions having good electroconductivity, the third step of forming a passive coating film with an oxidizing acid on the surface of the steel product except that of the inclusion above projected, and the fourth step of washing with water and drying.

Abstract: A ferroelectric capacitor configuration is configured with at least two different coercitive voltages. A first electrode structure having a surface which forms at least two levels is firstly produced. A layer of ferroelectric material of varying thickness is deposited over the first electrode by spin coating. A second electrode structure is subsequently formed on the layer of ferroelectric material.

Abstract: A dielectric film is formed on a free-standing conductive metal layer to form a multi-layer foil comprising a conductive metal layer, a barrier layer and a dielectric oxide layer. Such multi-layer foils are mechanically flexible, and useful for the manufacture of capacitors. Examples of barrier layers include Ni—P or Ni—Cr alloys. After a second layer of conductive metal is deposited on a dielectric oxide surface opposing the first conductive metal layer, the resulting capacitor foil is processed into a capacitor. The resulting capacitor is a surface mounted capacitor or is formed as a integrated or embedded capacitor within a circuit board.

Abstract: The invention includes semiconductor processing methods, including methods of forming capacitors. In one implementation, a semiconductor processing method includes providing a semiconductor substrate comprising a layer comprising at least one metal in elemental or metal alloy form. The metal comprises an element selected from the group consisting of platinum, ruthenium, rhodium, palladium, iridium, and mixtures thereof. At least a portion of the layer is etched in a halogenide, ozone and H2O comprising ambient.

Abstract: A thermal transfer sheet is equipped with an approval information of being approved as applicable to the predetermined printer. The thermal transfer sheet is set on a printer and, when a determinator determines that the approval information is correct for the printer, the printer is interlocked with the determinator to work the printer in the state where the thermal transfer sheet is set thereon. In the particularly preferable aspect, a recording part of thermal transfer are worked together with the printer and an approval information is destructed by the heating. A mark of an approval information can be formed of a material which can be detected by the light in a visible light region or an invisible region light, a magnetic material, an electrically-conductive material or a resonance circuit. The resonance circuit is preferably formed by thermally transferring an electrically-conductive layer in a predetermined pattern.

Abstract: The invention relates to a method for trench etching, in particular a method for anisotropic deep trench (DT) etching in an Si substrate by plasma dry etching, such as reactive ion etching (RIE), magnetically enhanced RIE or inductively coupled plasma etching (ICP), and sidewall passivation of the etched trenches in the Si substrate, the Si substrate being provided with an etching mask before the beginning of the etching operation. The invention is intended to provide a method for depth etching which, with a low outlay, makes it possible to achieve a significantly larger etching depth at higher speed and which enables a further reduction of the structure widths without any difficulty.

Abstract: In one aspect, a method of manufacturing a capacitor includes disposing one or more conductive layers of a first electrode stack in a recess of an alignment mechanism, where the recess is positioned relative to two or more alignment elements. The method further includes placing a separator over the one or more conductive layers where an outer edge of the separator contacts the two or more alignment elements. In one embodiment, a capacitor includes anode and cathode foils having offsetting edge portions. In one embodiment, a multiple tab cathode for a flat capacitor. A plurality of cathode tabs are portioned into a plurality of cathode tab groups positioned in different locations along the edge of the capacitor stack to reduce the amount of space required for connecting and routing the cathode tabs.

Abstract: A metal collector foil for an electric double layer capacitor has etched upper and lower surface layers and an unetched central layer disposed between the etched upper and lower surface layers. The etched upper and lower surface layers have a total thickness sufficient to provide the metal collector foil with a capacitance per unit area that corresponds to a capacitance value obtained when the etched metal collector foil is subjected to an anodic formation process with application of a withstanding voltage of 65.6 volts, the capacitance value being not less than 1.7 &mgr;F/cm2. The unetched central layer has a thickness sufficient to provide the metal collector foil with a tensile strength not less than 9,000 N/cm2. A method of producing the metal collector foil and an electric double layer capacitor incorporating therein the metal collector foil are also disclosed.

Abstract: A pixel electrode employs a transparent electrode made from indium-zinc-oxide (IZO) that is capable of preventing damage and bending thereof. In a liquid crystal display device containing pixel electrodes, the transparent electrode is made from indium-zinc-oxide (IZO) having an amorphous structure so that it can be etched within a short period of time with a low concentration of etchant. Accordingly, it is possible to prevent damage and bending of the transparent electrode upon the patterning thereof.

Abstract: In one aspect, a method of manufacturing a capacitor includes disposing one or more conductive layers of a first electrode stack in a recess of an alignment mechanism, where the recess is positioned relative to two or more alignment elements. The method further includes placing a separator over the one or more conductive layers where an outer edge of the separator contacts the two or more alignment elements. In one embodiment, a capacitor includes anode and cathode foils having offsetting edge portions. In one embodiment, a multiple tab cathode for a flat capacitor. A plurality of cathode tabs are portioned into a plurality of cathode tab groups positioned in different locations along the edge of the capacitor stack to reduce the amount of space required for connecting and routing the cathode tabs.

Abstract: In one aspect, a method of manufacturing a capacitor includes disposing one or more conductive layers of a first electrode stack in a recess of an alignment mechanism, where the recess is positioned relative to two or more alignment elements. The method further includes placing a separator over the one or more conductive layers where an outer edge of the separator contacts the two or more alignment elements. In one embodiment, a capacitor includes anode and cathode foils having offsetting edge portions. In one embodiment, a multiple tab cathode for a flat capacitor. A plurality of cathode tabs are portioned into a plurality of cathode tab groups positioned in different locations along the edge of the capacitor stack to reduce the amount of space required for connecting and routing the cathode tabs.

Abstract: A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication, employing a plasma activated reactive gas mixture, with layer material etch rate, etch rate ratio and pattern aspect ratio controlled by controlling the gas composition. There is provided a silicon substrate formed upon it a patterned microelectronics layer over which is formed a silicon containing dielectric layer. There is placed the silicon substrate within a reactor chamber equipped with electrodes which is evacuated. There is then filled the reactor chamber with a reactive gas mixture consisting of an oxidizing gas and two reactive gases. There may be optionally included in the reactive gas mixture nitrogen and inert gases for control purposes, but excluded from the reactive gas mixture are oxidizing gases containing carbon and oxygen.

Abstract: A reaction byproduct which is generated when a ferro-dielectric material film is etched is removed without giving adverse effect on the semiconductor element. After the etching of the ferro-dielectric material film, a wetting process may performed using an aqueous solution of phosphoric acid. After the ferro-dielectric material film is etched using the resist as the mask, the wetting process is also performed using the aqueous solution of phosphoric acid before and after the ashing of resist.

Abstract: An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The present invention develops the container capacitor by etching an opening (or contact opening) into a low etch rate oxide. The contact opening is used as a form for deposited polysilicon that conforms to the sides of the opening walls. Within the thin poly lining of the oxide container a high etch-rate oxide, such as ozone TEOS, is deposited over the entire structure thereby bridging across the top of the oxide container. The high etch-rate oxide is planarized back to the thin poly and the resulting exposed poly is then removed to separate neighboring containers. The two oxides, having different etch rates, are then etched thereby leaving a free-standing poly container cell with 100% (or all) of the higher etch rate oxide removed and a pre-determined oxide surrounding the container still intact.