Abstract: The processes allow structuring of a metal-containing layer. The metal-containing layer is etched, using an etching mask, in a plasma-assisted etching gas atmosphere at a temperature of over 130° C. and in the presence of at least one halogen compound and at least one oxidizing agent. The concentration of the oxidizing agent is thereby set higher than the concentration of the halogen compound.

Abstract: A method of forming a capacitor element is provided. After the barrier layer is formed on the dielectric layer, the lower electrode layer, the ferroelectric layer, and the upper electrode layer are formed on the barrier layer in this order. Thereafter, the etching mask having a pattern for a desired capacitor element is formed on the upper electrode layer. Using the etching mask, the upper electrode layer, the ferroelectric layer, the lower electric layer, and the barrier layer are selectively removed by dry etching. The etching gas containing fluorine (F) as one of its constituent elements is used in the step of selectively removing the barrier layer. The mask layer is etched back by an etching action in the same step, thereby eliminating the mask layer. The aspect ratio of the contact hole that exposes the upper capacitor electrode can be decreased by the thickness of the remaining mask layer. Therefore, a desired capacitor element can be formed by using a process (e.g.

Abstract: In the method of fabricating an inductor, at least first and second conductive segments are formed in a semiconductor layer spaced apart in a first direction. A first dielectric layer is formed over a portion of the semiconductor layer along the first direction such that the first dielectric layer crosses the first and second conductive segments. A conductive core is formed on the first dielectric layer, and a second dielectric layer is formed over the semiconductor layer. First and second contact holes are formed in the second dielectric layer such that the first contact hole exposes a portion of the first conductive segment on a first side of the first dielectric layer and the second contact hole exposes a portion of the second conductive segment on a second side of the first dielectric layer.

Abstract: A method for forming rough surface: first, provide a substrate; then, immerse a surface layer of substrate in a solution which is able to etch surface layer; next, form numerous bubbles in solution such that part of bubbles are located on a surface of surface layer, where surface is contacted with solution; finally, remove solution. The method also could form bubbles in solution before surface layer is immersed in solution, and could perform a dry process after solution is removed. Significantly, this method at least could be used to enhance adhesion of photoresist and increases capacitance of capacitor.

Abstract: An object of the present invention is to provide a solid electrolytic capacitor with excellent electrostatic capacitance and reduced dispersion of capabilities by treating the surface of a chemically formed aluminum film to form a dielectric film which is in contact an electrically conducting substance provided thereon with sufficiently high adhesion. Another object of the present invention is to provide a method for producing the solid electrolytic capacitor, which includes providing an organic electrically conducting polymer as a solid electrolyte on a chemically formed aluminum substrate having thereon an aluminum oxide dielectric film, where a chemically formed aluminum substrate, which was cut into a predetermined shape, is treated with an aqueous acid solution to dissolve a part of the dielectric film on the substrate surface.

Abstract: A method for removing at least a portion of a structure, such as a layer, film, or deposit, including ruthenium metal and/or ruthenium dioxide includes contacting the structure with a material including ceric ammonium nitrate. A material for removing ruthenium metal and amorphous ruthenium dioxide includes ceric ammonium nitrate and may be in the form of an aqueous solution including ceric ammonium nitrate and, optionally, other solid or liquid solutes providing desired properties. In one application, the method and material may be utilized to etch, shape, or pattern layers or films of ruthenium metal and/or ruthenium dioxide in the fabrication of semiconductor systems and their elements, components, and devices, such as wires, electrical contacts, word lines, bit lines, interconnects, vias, electrodes, capacitors, transistors, diodes, and memory devices.

Abstract: A method for removing at least a portion of a structure, such as a layer, film, or deposit, including ruthenium metal and/or ruthenium dioxide includes contacting the structure with a material including ceric ammonium nitrate. A material for removing ruthenium metal and amorphous ruthenium dioxide includes ceric ammonium nitrate and may be in the form of an aqueous solution including ceric ammonium nitrate and, optionally, other solid or liquid solutes providing desired properties. In one application, the method and material may be utilized to etch, shape, or pattern layers or films of ruthenium metal and/or ruthenium dioxide in the fabrication of semiconductor systems and their elements, components, and devices, such as wires, electrical contacts, word lines, bit lines, interconnects, vias, electrodes, capacitors, transistors, diodes, and memory devices.

Abstract: Batch thin film capacitors and their methods of manufacture using semiconductor manufacturing techniques. A mask, photo mask or shadow mask, having a pattern is used to form a matrix of rows and columns of thin film capacitors in a wafer. Capacitor terminals are formed in a batch process by separation at column saw areas, depositing a conductive layer and vertically etching horizontal layers of the conductive layer. Capacitance of an individual batch processed thin film capacitor is increased by stacking wafers together prior to separation at the column saw areas and forming capacitor terminals thereafter to couple parallel thin film capacitors together.

Abstract: A method for producing a pinhole-free dielectric film comprising applying a photopolymer to a first dielectric surface of a dielectric film having pinholes, exposing a second and opposing surface to an amount of radiation effective to polymerize the photopolymer exposed by the pinholes, and removing unpolymerized photopolymer.

Abstract: A cleaning solution for use in removing a damaged portion of a ferroelectric layer, and a cleaning method using the solution. The cleaning solution includes a fluoride, an organic acid with carboxyl group, an alkaline pH adjusting agent and water.

Abstract: An object of the present invention is to provide a solid electrolytic capacitor with excellent electrostatic capacitance and reduced dispersion of capabilities by treating the surface of a chemically formed aluminum film to form a dielectric film which is in contact an electrically conducting substance provided thereon with sufficiently high adhesion. Another object of the present invention is to provide a method for producing the solid electrolytic capacitor, which includes providing an organic electrically conducting polymer as a solid electrolyte on a chemically formed aluminum substrate having thereon an aluminum oxide dielectric film, where a chemically formed aluminum substrate, which was cut into a predetermined shape, is treated with an aqueous acid solution to dissolve a part of the dielectric film on the substrate surface.

Abstract: In a process for forming a lower electrode of a cylindrical capacitor in a semiconductor memory, a polysilicon film is formed on an insulator film to cover an inner surface of a hole formed in the insulator film. An exposed surface of the polysilicon film is treated with a reaction accelerator which reacts with a positive photoresist to lower dissolubility of the positive photoresist to a developer liquid. The positive photoresist is deposited on the whole surface to fill up the hole. As a result, the positive photoresist filled up within the hole reacts with the reaction accelerator within the hole and becomes difficult to dissolve to the developer liquid even after the positive photoresist is exposed to light. The whole of the positive photoresist is exposed to light and then developed with the developer so that the positive photoresist remains only within the hole.

Abstract: A ferroelectric capacitor configuration is configured with at least two different coercitive voltages. A first electrode structure having a surface which forms at least two levels is firstly produced. A layer of ferroelectric material of varying thickness is deposited over the first electrode by spin coating. A second electrode structure is subsequently formed on the layer of ferroelectric material.

Abstract: A method for making a capacitor of a semiconductor memory device capable of providing increased capacitance without degraded resolution, as well as without the removal of any interlayer insulation layers upon formation of a lower electrode for the capacitor, wherein after formation of an access transistor on a semiconductor substrate, a first interlayer insulation layer for planarization of a surface of the semiconductor substrate and a second interlayer insulation layer for formation of the capacitor lower electrode are formed. After formation of an opening for exposing a part of an impurity diffusion region of the access transistor by etching a part of the first and second interlayer insulating layers, a spacer is formed within the opening. Further, after deposition of a conductive layer for the capacitor lower electrode onto a surface of the substrate, a planarization process is carried out until a part of the upper surface of the spacer is exposed.

Abstract: An etching gas mixture for a transition metal thin film, and an etching method using the etching gas mixture are provided. The etching gas mixture is composed of two gases. The first gas is one selected from the group consisting of halogen gas, halide gas, halogen gas mixture, halide gas mixture and gas mixture of halogen and halide. The second gas is one selected from the group consisting of carbon oxide gas, hydrocarbon gas, nitrogen oxide gas and nitrogen-containing gas. The etching gas mixture reacts with the transition metal thin film to form a highly volatile metal halide, so that a fine pattern can be formed with a high selectivity.

Abstract: A reaction byproduct which is generated when a ferro-dielectric material film is etched is removed without giving adverse effect on the semiconductor element. After the etching of the ferro-dielectric material film, a wetting process may performed using an aqueous solution of phosphoric acid. After the ferro-dielectric material film is etched using the resist as the mask, the wetting process is also performed using the aqueous solution of phosphoric acid before and after the ashing of resist.

Abstract: A fabrication technique for a test sample to characterize pyroelectric and erroelectric thin films for use in uncooled infrared focal plane arrays operated at a nominal 60 Hz. Most layers are patterned by a lift off technique, and those layers that are not lifted off are chemically etched or ion milled. The pyroelectric layer is thermally insulated from the substrate by a thick film layer of ZrO.sub.2. The pyroelectric layer is sandwiched between metal layers to form a capacitor. Direct measurement of the voltages between the capacitor plates, and of the temperature of these plates, results in a direct measurement of thin film temperature responsivity.

Abstract: A method of forming an etch stop layer 40 above a fuse 16 in a fuse opening (or window) 92 using a specialized 2 stage etch process. The invention has two important features: First, the etch stop layer 40 is formed from a polysilicon layer (P2 or P4) that is used to fabricate semiconductor devices on a substrate. The etch stop layer 40 is preferably formed of polysilicon layer to is used to from a contact to the substrate 10 (P2) or to form part of a capacitor (P4). Second, a specialized two stage etch process is used where the second stage etches the etch stop layer 40 while simultaneously forming a passivation layer 114 over a metal pad 85.

Abstract: A method and apparatus for coupling high speed data components using imbedded PCB AC coupling capacitors is disclosed. The capacitor comprises a first and a second conductive plate of polygonal shape coupled to surrounding circuitry at the polygonal vertices of the polygonal plates. This configuration results in improved capacitor performance, particularly with respect to capacitive impedance and reflected waves for high bandwidth signals at the frequency ranges of interest.

Abstract: Cathode and anode sides of a plurality of solid electrolytic capacitors are connected by simultaneous electric welding. The welding step is effected to connect an anode lead of a lead frame to the anode electrode of a capacitor body and simultaneously connect a cathode lead of the lead frame to the cathode conductor layer of an adjacent capacitor body. The welding electrode for the cathode lead exerts moderate force to the capacitor bodies using a spring function of the capacitor lead. The simultaneous welding for the adjacent capacitor bodies and the moderate force prevent electrical and mechanical damages of the insulator layer of the solid electrolytic capacitors during the welding.

Abstract: A region is formed in a semiconductor substrate and extends beyond the substrate surface. First and second interconnects each having a predetermined thickness and a surface approximately parallel to the substrate surface are formed on the region. The first and second interconnects define a trench therebetween. A third interconnect is formed on the substrate. The thicknesses of the first and second interconnects are reduced a first amount to improve the aspect ratio of the trench, to improve the cross-sectional profile of the trench, or both. The thickness of the third strip is reduced a second amount. The second amount may be smaller than the first amount.

Abstract: A method for making anode foil plates for use with layered electrolytic capacitors and capacitors made with such plates. A high purity aluminum foil is provided for generation of anode foil plates. Sheets of the foil are highly etched to provide a very high surface area. Following the etch process, the foil is partially cut or punched into plates from the etched sheets in the general shape of the finished capacitor housing with a portion remaining connected to the supporting foil. The supporting foil with the partially punched-out etched plates are subjected to a forming process by applying a voltage to the plates in the presence of an electrolyte to provide formed anode foil plates with edges which do not have to be reformed during capacitor aging and which do not have any particulates at cut edges. The formed anode plates are layered with cathode plates and separators in a capacitor housing with an electrolyte to provide a finished capacitor.

Abstract: An electrochemical cell for etching a metal workpiece such as an aluminum foil, a method for etching the foil using the electrochemical cell, and foil thus produced is provided. The cell includes an etch tank having an etch electrolyte disposed therein and containing at least a first and a second compartment each containing (i)an etch electrolyte, (ii) a cathode plate, and (iii) an ion exchange membrane separator portion having an ion exchange polymeric material effective to substantially retard or prevent reduction of the oxidizing agent or agents present in the etch electrolyte, the first and second compartments being arranged in the etch tank with the ion exchange membrane separator portions in facing relationship one to the other; and a metal workpiece such as an aluminum foil anode present in the etch tank and disposed between each said first and second compartments.

Abstract: The present invention discloses a noel method for anchoring a via/contact or the forming of a capacitor having increasing capacitance in a semiconductor device by utilizing alternating layers of BPTEOS oxide and TEOS oxide and a deep UV photoresist such that toroidal-shaped cavities can be formed at the interfaces between the BPTEOS oxide layers and the TEOS oxide layers during the formation of the via/contact opening or the capacitor opening by a plasma etching process. The number of cavities formed, i.e., the number of anchors formed on the via/contact or capacitor, can be suitably adjusted by the number of BPTEOS oxide layer deposited on the semiconductor structure. Each BPTEOS oxide layer produces two anchors on the via/contact or the capacitor. The deep UV photoresist layer should contain a photo-acid-generator such that hydrogen ions are emitted when the photoresist layer is subjected to UV radiation and heating which accelerates the hydrogen ion generation process.

Abstract: A semiconductor device capacitor fabrication method comprises forming a first insulation film on a substrate and an undoped semiconductor layer on the first insulation film, patterning the undoped semiconductor layer to a desired shape, forming a second insulation film on the undoped semiconductor layer, forming contact holes by selectively etching the second insulation film, the undoped semiconductor layer and the first insulation respectively for exposing a portion of the undoped semiconductor layer therethrough, forming a first electrode film on the bottom of each of the contact holes, the undoped semiconductor layer and side walls of the second insulation film, removing the second insulation film, and forming a dielectric thin film and a second electrode film sequentially on the first electrode film. The fabrication method realizes a high dielectric constant in a large scale integration semiconductor memory device by employing new materials for a dielectric thin film and an electrode.

Abstract: A method of fabricating a dielectric material useful in advanced memory applications which comprises a metal oxide such as TiO.sub.2 or Ta.sub.2 O.sub.5 interdiffused into a Si.sub.3 N.sub.4 film is provided.

Abstract: A device insulating film, a lower-layer platinum film, a ferroelectric film, an upper-layer platinum film, and a titanium film are sequentially formed on a semiconductor substrate in this order. On the titanium film, a photoresist mask is further formed in a desired pattern. The thickness of the titanium film is adjusted to be 1/10 or more of the total thickness of a multilayer film consisting of the upper-layer platinum film, the ferroelectric film, and the lower-layer platinum film. The titanium film is then subjected to dry etching and the photoresist film is removed by ashing process. The titanium film thus patterned is used as a mask in etching the upper-layer platinum film, the ferroelectric film, and the lower-layer platinum film by a dry-etching method using a plasma of a gas mixture of chlorine and oxygen in which the volume concentration of oxygen gas is adjusted to be 40%. During the dry-etching process, the titanium film is oxidized to provide a high etching selectivity.

Abstract: A method of forming a capacitor that has improved charge storage capacity in a high density memory device that has shallow trench isolation regions and a capacitor produced by the method are provided. The method includes the step of forming an oxide spacer that consists of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a contact hole is first etched by a plasma etching technique, the hole is again decoratively etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a corrugated side-wall of the contact hole is formed which affords the capacitor cell with an increased surface area leading to an improved charge storage capacity.

Abstract: A method of fabricating a metal-ferroelectric-metal ("MFM") capacitor includes the steps of depositing a silicon dioxide layer on a silicon or other substrate, a lower platinum or other noble metal electrode, a PZT or other ferroelectric material dielectric layer, and an upper platinum or other noble metal electrode. The upper electrode and ferroelectric dielectric layer are patterned and etched according to a first pattern corresponding to the final dimensions of the ferroelectric dielectric layer. The upper electrode and lower electrode are subsequently patterned and etched according to a second pattern corresponding to the final dimensions of one or more upper electrodes and the final extent of the lower electrode. The second etching step leaves a benign vestigial upper electrode feature. An oxide layer is finally deposited over the entire surface of the MFM capacitor structure, which is etched and metalized over desired upper and lower electrode contacts.

Abstract: A method of improving the breakdown strength of polymer multi-layer (PML) capacitors is provided. The method comprises removing metal, specifically, aluminum, from the cut edge. This is done by either etching back the metal electrode layers in either basic or acidic solution or by anodizing the metal to cover that portion of the metal at the edge with an oxide. Removing the metal from the cut edge increases the breakdown strength of the PML capacitors by a factor of two or more.

Abstract: An electrochemical cell for etching a metal workpiece such as an aluminum foil, a method for etching the foil using the electrochemical cell, and foil thus produced is provided. The cell includes an etch tank having an etch electrolyte disposed therein and containing at least a first and a second compartment each containing (i)an etch electrolyte, (ii) a cathode plate, and (iii) an ion exchange membrane separator portion comprising an ion exchange polymeric material effective to substantially retard or prevent reduction of the oxidizing agent or agents present in the etch electrolyte, the first and second compartments being arranged in the etch tank with the ion exchange membrane separator portions in facing relationship one to the other; and a metal workpiece such asan aluminum foil anode present in the etch tank and disposed between each said first and second compartments.

Abstract: The invention discloses a process for formation of a capacitor for a semiconductor device. The upper node electrode is supported by side wall spacers and a central pole, so that the supporting strength may be reinforced and the surface area may be increased. During the formation of a contact hole, a first side wall spacer is formed, and, by utilizing the first side wall spacer, a contact hole is opened with a greater margin. The upper and lower node electrodes are of a tunnel structure. The central pole of the node electrodes is provided with a hole in it, so that a conductive material may be filled into the hole to form a connecting portion. This connecting portion connects the node electrodes of the capacitor to a source/drain region which is formed on a semiconductor substrate. A thin dielectric film is deposited on the surface of the node electrode, and a plate electrode is formed thereupon, thereby completing the formation of the capacitor.

Abstract: A resonant tag has one electrode plate of a capacitor and an electric circuit, which is electrically connected to the capacitor, formed on one surface of the insulating film composing the resonant circuit. On the other surface of the insulating film, the other electrode plate of the capacitor, which is electrically connected to the electric circuit, is formed. Heat pressing is performed on the insulating film existing between the two electrode plates with a predetermined pressure and at a predetermined temperature to shorten a distance between these electrode plates, and a crystal structure of the insulating film is destroyed to form a penetrating hole which penetrates through both the electrode plates.

Abstract: An improved electrolytic capacitor is provided by producing an anode foil which has areas which are not subject to stress during manufacturing being highly etched and those areas which are subject to stress during manufacturing being lightly etched or not etched at all. The process of the invention provides an etch mask to cover during the etch process those portions of the anode foil which will be subjected to stress during construction of the capacitor. The highly etched areas, which are very brittle, provide increased capacitance and thus improved energy density. For layered or stacked capacitors, a weld tab is covered with the etch mask to allow connection of the anode layers. Additionally, strong edges may be maintained thereby reducing the possibility of cracking that would normally occur during the stamping and assembly operations.

Abstract: Micro-structures comprising at least a structural member, which is liable to be bent under an external force and formed so as to leave a space between the member and another member liable to be bent and/or other rigid component, are successfully treated using a treating liquid, without suffering permanent deformation resulting from the use of the treating liquid, by removing the micro-structures from the liquid to an environment having a pressure less than the atmospheric pressure; or displacing the micro-structures from the treating liquid to another treating liquid having a smaller surface tension than that of the former liquid, and then removing the micro-structures from the latter liquid; or drying the micro-structures removed from the treating liquid by exposing the same to vapor of a liquid having a smaller surface tension than that of the treating liquid; or removing the micro-structures from the treating liquid to the atmosphere, and drying them using an energy beam of high intensity or an ultrasonic

Abstract: Disclosed herein is a method of manufacturing a multilayer ceramic electronic component by forming external electrodes on a pair of opposite side surfaces of a sintered body (1) obtained by sintering a laminate prepared by stacking a plurality of ceramic green sheets through internal electrodes to be electrically connected with prescribed ones of the internal electrodes. The method of manufacturing a multilayer ceramic electronic component comprises a step of forming the internal electrodes on single major surfaces of the ceramic green sheets by a thin film forming method, a step of electrochemically etching the opposite side surfaces (1a', 1b) of the sintered body (1) for forming gap regions between the internal electrodes and those of the external electrodes which must not be electrically connected with the internal electrodes and a step of filling up clearance portions (A) defined by dissolution/removing of the internal electrodes by the etching with an insulating material.

Abstract: A resonant tag is manufactured in the manner described below: a conductive thin film is formed to a predetermined thickness on two surfaces of an insulating thin film. Thereafter, a conductive pattern, composed of an inductor element and a capacitor element corresponding to a resonant frequency of a resonant circuit, is printed on a surface of one of the conductive thin films, and a conductive pattern, composed of a capacitor element corresponding to the resonant frequency of the resonant circuit, is printed on a surface of the other insulating thin film at a position which faces the capacitor element formed on one of the conductive thin films using an ink which resists etching. A non-printed portion of the conductive thin films is removed by etching to form a resonant circuit pattern.

Abstract: A method of etching an aluminum foil for electrolytic capacitors, comprising the steps of electrolytically etching an aluminum foil for electrolytic capacitors that has a high cubic texture in an electrolyte containing a chloride to form pits, and enlarging the pits formed in the above step by etching, in which step of forming pits the current density is increased from 0 to a maximum value quickly and then is decreased gradually.

Abstract: A method of manufacturing a semiconductor device, where on top of a substrate having already-completed circuit elements and wiring, etc., an insulation underlayer a, Pt layer for a bottom electrode, a dielectric film and a Pt layer for a top electrode are shaped.A top electrode, capacitance insulation film and bottom electrode are formed by etching the Pt layer for the top electrode or the Pt layer for the bottom electrode using an etching gas contained an S component while composing a Pt and S compound. Alternatively the Pt and S compound can be composed first, and then the compound can be etched.

Abstract: According to a method of fabricating a memory cell for a semiconductor integrated circuit, a lower electrode having a predetermined shape is formed on a semiconductor layer. A first insulating interlayer is formed on an entire surface of the semiconductor layer such that only a top surface of the lower electrode is exposed. A dielectric having a high dielectric constant is formed on the lower electrode and on the semiconductor layer. An upper electrode is formed on the dielectric having a high dielectric constant. The upper electrode constitutes a capacitor with the lower electrode through the dielectric.

Abstract: A method of reactive ion etching both a lead zirconate titanate ferroelectric dielectric and a RuO.sub.2 electrode, and a semiconductor device produced in accordance with such process. The dielectric and electrode are etched in an etching gas of O.sub.2 mixed with either CClF.sub.2 or CHClFCF.sub.3.

Abstract: A method of manufacturing a semiconductor device, where on top of a substrate having already-completed circuit elements and wiring, etc., an insulation underlayer a, Pt layer for a bottom electrode, a dielectric film and a Pt layer for a top electrode are shaped. A top electrode, capacitance insulation film and bottom electrode are formed by etching the Pt layer for the top electrode or the Pt layer for the bottom electrode using an etching gas contained a S component while composing a Pt and S compound. Alternatively the Pt and S compound can be composed first, and then the compound can be etched.

Abstract: A high performance capacitor fabricated from nano-structure multilayer materials, such as by controlled, reactive sputtering, and having very high energy-density, high specific energy and high voltage breakdown. The multilayer capacitors, for example, may be fabricated in a "notepad" configuration composed of 200-300 alternating layers of conductive and dielectric materials so as to have a thickness of 1 mm, width of 200 mm, and length of 300 mm, with terminals at each end of the layers suitable for brazing, thereby guaranteeing low contact resistance and high durability. The "notepad" capacitors may be stacked in single or multiple rows (series-parallel banks) to increase the voltage and energy density.

Abstract: A method for making of a charge storage electrode in a semiconductor device is disclosed.The method comprises the steps of forming a first silicon film into a second protruded silicon film which is aslant at its both sides, forming a first thin insulating film over the second silicon film, and applying an anisotropic dry etching to the first insulating film and the second silicon film to form a vertical structure of a third silicon film, said anisotropic dry etching allowing the upper first insulating film to be removed prior to the side first insulating film, which subsequently remains in a thinner thickness to act as an obstacle to the anisotropic dry etching for the side portions of the protruded second silicon film, so that the central portion of the protruded second silicon film is etched in a larger quantity than the side portions.

Abstract: A resonant tag is manufactured in the manner described below: a conductive thin film is formed to a predetermined thickness on two surfaces of an insulating thin film. Thereafter, a conductive pattern, composed of an inductor element and a capacitor element corresponding to a resonant frequency of a resonant circuit, is printed on a surface of one of the conductive thin films, and a conductive pattern, composed of a capacitor element corresponding to the resonant frequency of the resonant circuit, is printed on a surface of the other insulating thin film at a position which faces the capacitor element formed on one of the conductive thin films using an ink which resists etching. A non-printed portion of the conductive thin films is removed by etching to form a resonant circuit pattern.