Substrate Is Multilayered Patents (Class 216/95)
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Patent number: 6391137Abstract: An object of the present invention is to provide a method for producing a display device by which a substrate is thinned efficiently. Onto one original substrate having an area for a plurality of display devices, the other original substrate is bonded via a sealing resin layer, the pair of bonded original substrates is divided and separated into a plurality of pairs of substrates of a size of each individual display device, and thereafter a substrate thinning process of thinning the substrates is performed in a state where the substrates are held by substrate holding means.Type: GrantFiled: September 30, 1999Date of Patent: May 21, 2002Assignee: Sharp Kabushiki KaishaInventor: Yasuhiro Matsushima
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Publication number: 20020056697Abstract: A method for removing at least a portion of a structure, such as a layer, film, or deposit, including ruthenium metal and/or ruthenium dioxide includes contacting the structure with a material including ceric ammonium nitrate. A material for removing ruthenium metal and amorphous ruthenium dioxide includes ceric ammonium nitrate and may be in the form of an aqueous solution including ceric ammonium nitrate and, optionally, other solid or liquid solutes providing desired properties. In one application, the method and material may be utilized to etch, shape, or pattern layers or films of ruthenium metal and/or ruthenium dioxide in the fabrication of semiconductor systems and their elements, components, and devices, such as wires, electrical contacts, word lines, bit lines, interconnects, vias, electrodes, capacitors, transistors, diodes, and memory devices.Type: ApplicationFiled: November 16, 2001Publication date: May 16, 2002Inventor: Donald L. Westmoreland
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Patent number: 6383332Abstract: A method of planarizing a semiconductor wafer having a polishing endpoint layer that includes a ligand is disclosed. One step of the method includes polishing a first side of the wafer in order to remove the ligand from the wafer. Another step of the method includes determining that a chelating agent has bound the ligand due to the polishing step removing the ligand of the polishing endpoint layer. The method also includes the step of terminating the polishing step in response to determining that the chelating agent has bound the ligand. A polishing system is also disclosed which detects a polishing endpoint based upon a chelating agent binding a ligand of a polishing endpoint layer of a semiconductor device.Type: GrantFiled: May 31, 2000Date of Patent: May 7, 2002Assignee: LSI Logic CorporationInventors: Gail D. Shelton, Gayle W. Miller
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Patent number: 6379577Abstract: A process and solution for selectively wet etching a titanium based perovskite material disposed on a silicon oxide or silicon nitride substrate is disclosed herein. The solution is composed of hydrogen peroxide, an acid and deionized water. The solution is heated to a temperature between 25 and 90 degrees Celsius. The titanium based perovskite material may be barium strontium titanate, barium titanate, strontium titanate or a lead titanate. The solution selectively etches the perovskite material while the substrate is only minimally etched, if at all. The process and solution allows for an etching rate up to thirty times greater than conventional etching rates for similar perovskite materials selective to various substrate, barrier and mask layers, including SiO2.Type: GrantFiled: June 10, 1999Date of Patent: April 30, 2002Assignee: International Business Machines CorporationInventors: Hiroyuki Akatsu, David E. Kotecki, Jingyu Jenny Lian, Hua Shen
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Publication number: 20020018964Abstract: The method of fabricating a suspended microstructure with a sloped support, comprises the steps of (a) providing a member having three stacked up layers including a first substrate layer, a second temporary layer and a third photoresist layer; (b) photolithographically transferring a sloped pattern to the third photoresist layer by means of a grey scale mask; (c) etching the second layer through the third layer resulting from step (b) to obtain a surface with at least one continuous slope with a predetermined angle with respect to the first surface layer; (d) depositing a fourth layer on the previous layers; (e) etching the fourth layer to obtain the sloped support; and (f) removing the second layer to obtain the microstructure with the sloped support. The invention is also concerned with a suspended microstructure fabricated by the method.Type: ApplicationFiled: June 25, 2001Publication date: February 14, 2002Inventor: Hubert Jerominek
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Publication number: 20020003127Abstract: A method of manufacturing a wireless suspension blank is a method of manufacturing a wireless blank in which three-layered laminate formed of a metallic layer having the spring property and a conductive layer laminated on the metallic layer through an electrically insulating layer are used, wherein as the laminate used is a laminate in which an insulating layer is formed of core-insulating layer and adhesive layers laminated on both sides of the core-insulating layer, and the ratio of higher etching rate to lower etching rate of the respective layers of the insulating layer is between 6:1 and 1:1. By the photo etching method processed are the metallic layer and the conductive layer. The insulating layer is processed by the wet etching method.Type: ApplicationFiled: July 6, 2001Publication date: January 10, 2002Inventors: Katsuya Sakayori, Shigeki Kawano, Hiroko Amasaki, Kazuo Umeda, Satoshi Sasaki, Hiroshi Yagi
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Patent number: 6329302Abstract: A top IC die is removed from a bottom IC die in a multichip IC package while substantially preserving interconnect of the bottom IC die for proper fault isolation during testing of the multichip IC package. The top IC die is attached to the bottom IC die with a die attach material within the multichip IC package. The top IC die has a first area that is smaller than a second area of the bottom IC die, and the top IC die is disposed inward from any edge of the bottom IC die such that a perimeter area of the bottom IC die is outside the top IC die. A predetermined area of the top IC die is exposed with the predetermined area being smaller than the first area of the top IC die. The predetermined area is disposed inward from any edge of the top IC die. The first area of the top IC die outside the predetermined area remains covered, and the perimeter area of the bottom IC die remains covered.Type: GrantFiled: June 26, 2000Date of Patent: December 11, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Caroline M. Francis
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Patent number: 6328796Abstract: A method for making a multilayered structure with a single crystal film bonded to a polycrystalline substrate has the steps of: bonding a single crystal film to a polycrystalline substrate; and growing an epitaxial layer on said single crystal film bonded to said polycrystalline substrate.Type: GrantFiled: February 1, 1999Date of Patent: December 11, 2001Assignee: The United States of America as represented by the Secretary of the NavyInventors: Francis J. Kub, Karl D. Hobart
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Publication number: 20010045408Abstract: A method for manufacturing a dielectric waveguide at a low manufacturing cost, the dielectric waveguide comprising a pair of conductor plates approximately parallel to each other and the dielectric strip provided therebetween, which can form a dielectric strip having accurate individual dimensions without generating cracks and chips during processing. The method comprises the steps of forming a resist pattern on a green sheet containing at least a powdered inorganic material and an organic binder, removing a predetermined amount of the green sheet corresponding to an opening in the resist pattern by the use of a mask, removing the resist pattern, and firing the green sheet. In the step of removing the predetermined amount of the green sheet, the rate of removal is continuously or intermittently changed along the depth direction of the green sheet.Type: ApplicationFiled: April 26, 2001Publication date: November 29, 2001Applicant: Murata Manufacturing Co., Ltd.Inventor: Toshikazu Takeda
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Patent number: 6322712Abstract: In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fabrication steps. This aluminum oxide barrier layer is preferably formed either by: (1) partially or completely anodizing an aluminum layer formed over the ITO layer, or (2) an in situ process forming aluminum oxide either over the ITO layer or over an aluminum layer formed on the ITO layer. After either of these processes, an aluminum layer is then formed over the aluminum oxide layer.Type: GrantFiled: September 1, 1999Date of Patent: November 27, 2001Assignee: Micron Technology, Inc.Inventors: Robert J. Hanson, Won-Joo Kim, Mike E. Pugh
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Publication number: 20010024883Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch which produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.Type: ApplicationFiled: March 23, 2001Publication date: September 27, 2001Applicant: Micron Technology, Inc.Inventors: Karen Huang, Christophe Pierrat
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Publication number: 20010020517Abstract: A dry etching step during the manufacturing of a substrate for a liquid crystal display (LCD) device is improved by placing the substrate at a predetermined distance away from the lower electrode to prevent damage of the substrate due to electrostatic formed therebetween. An insulating tape attached on the lower electrode provides electrostatic protection between the substrate and the lower electrode, so that the substrate is properly lifted off the lower electrode via the lifting pins of the lower electrode without electrostatic interference.Type: ApplicationFiled: December 27, 2000Publication date: September 13, 2001Inventor: Byung-Young Ahn
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Publication number: 20010008224Abstract: A method of manufacturing electronic components includes disposing a top metal layer (502) comprised of solder over a bottom metal layer (201, 202) comprised of titanium or tungsten, and selectively etching the bottom metal layer (201, 202) over the top metal layer (502) with an etchant mixture (601) comprised of an etchant, an additive to control the temperature of the etchant mixture (601), and another additive to reduce the redeposition of the top layer (502).Type: ApplicationFiled: July 30, 1998Publication date: July 19, 2001Inventors: ERIC J. WOOLSEY, DOUGLAS G. MITCHELL, GEORGE F. CARNEY, FRANCIS J. CARNEY, CARY B. POWELL
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Patent number: 6261735Abstract: A composition and method for removing probing ink and negative photoresist from a substrate with reduced metal corrosion, low toxicity and rapid removal rates. The composition includes a mixture of anisole, an alkylarylsulfonic acid, and aliphatic hydrocarbons containing 9 to 13 carbon atoms.Type: GrantFiled: November 24, 1998Date of Patent: July 17, 2001Assignee: Silicon Valley Chemlabs, Inc.Inventor: Javad J. Sahbari
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Patent number: 6258205Abstract: An apparatus for planarizing a semiconductor wafer having a polishing endpoint layer that includes a catalyst material is disclosed. The apparatus is operable to detect the endpoint based upon the chemical slurry whether a catalytic reaction has occurred due to the polishing platen removing a portion of the catalyst material from the wafer.Type: GrantFiled: March 24, 2000Date of Patent: July 10, 2001Assignee: LSI Logic CorporationInventors: Brynne K. Chisholm, Gayle W. Miller, Gail D. Shelton
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Patent number: 6254791Abstract: A method of making an illuminate, multicolored panel, comprising the steps of fixing together an opaque layer to a clear layer to form a panel, etching a well into the opaque layer of the panel, and depositing tinted translucent material into the well.Type: GrantFiled: February 19, 1999Date of Patent: July 3, 2001Assignee: Harnischfeger Technologies, Inc.Inventor: James W. Boyd
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Patent number: 6254794Abstract: A method for preparing a semiconductor member comprises: forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer; bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; and etching to remove the porous silicon layer by immersing in an etching solution.Type: GrantFiled: April 22, 1999Date of Patent: July 3, 2001Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuhiko Sato
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Patent number: 6238586Abstract: A method for preparing a semiconductor member comprises: forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer; bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; and etching to remove the porous silicon layer by immersing in an etching solution.Type: GrantFiled: April 22, 1999Date of Patent: May 29, 2001Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuhiko Sato
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Patent number: 6235638Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch which produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.Type: GrantFiled: February 16, 1999Date of Patent: May 22, 2001Assignee: Micron Technology, Inc.Inventors: Karen Huang, Christophe Pierrat
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Patent number: 6214245Abstract: A method for forming an ink jet nozzle plate includes providing a buried layer over a bottom substrate layer; providing and patterning a top substrate layer over the buried layer and having openings having inclined walls; providing an ink jet nozzle plate layer over the patterned top substrate layer and into the openings formed in the patterned top substrate layer, the ink jet nozzle plate layer contacting the buried layer; attaching the ink jet nozzle plate layer to a base having ink delivery channels; removing by etching the bottom substrate layer; and providing bore regions into the ink jet nozzle plate layer with each bore region corresponding to a delivery channel.Type: GrantFiled: March 2, 1999Date of Patent: April 10, 2001Assignee: Eastman Kodak CompanyInventors: Gilbert A. Hawkins, Xin Wen
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Patent number: 6187216Abstract: A wet etch bath (61) holds a wet etchant (52) for etching a dielectric over a semiconductor substrate. The wet etch bath (61) has a tub (63) separated from a reservoir (64) by a wall (65). The tub (63) is filled with the wet etchant (52) to a height of the wall (65). The reservoir (64) is filled with the wet etchant (52) to a height less than the height of the wall. A pump (66) coupled to the reservoir (64) pumps the wet etchant (52) through an osmotic membrane degasifier (69) to the tub (63). Adding the wet etchant (52) to the tub (63) causes the wet etchant (52) to cascade over the wall (65) back to the reservoir (64). The osmotic membrane degasifier (69) reduces a concentration of a reactive agent in the wet etchant (52).Type: GrantFiled: August 27, 1997Date of Patent: February 13, 2001Assignee: Motorola, Inc.Inventors: Paul William Dryer, Michael J. Davison, Ralph A. Dyrsten
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Patent number: 6171512Abstract: A method for preparing a semiconductor member comprises: forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer; bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; and etching to remove the porous silicon layer by immersing in an etching solution.Type: GrantFiled: June 7, 1995Date of Patent: January 9, 2001Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuhiko Sato
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Patent number: 6146543Abstract: A micromachined multi-layered microbellows-style actuator capable of delivering larger deflections compared to a single layered flat membrane of comparable size. Anchor structures are disclosed that improve the strength of the microbellows membrane. A characterization apparatus is used to measure microbellows membrane performance. Thermopneumatic actuators having a resistive heater chip are also disclosed. The microbellows membrane is manufactured by alternating deposition of structural layers and sacrificial layers on a substrate. The structural layers can be made of silicon nitride and the sacrificial layers can be made of polysilicon. The substrate is etched from the back to form an opening exposing the sacrificial layers, and then the membrane is released by etching away the sacrificial layers.Type: GrantFiled: October 26, 1999Date of Patent: November 14, 2000Assignee: California Institute of TechnologyInventors: Yu-Chong Tai, Xing Yang
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Patent number: 6117351Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a second dielectric layer overlying a first dielectric layer, contacting the substrate at a first temperature with a first acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with a second acid solution exhibiting a positive etch selectivity at the second temperature. The first and second dielectric layers exhibit different etch rates in the first and second acid solutions. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175.degree. C. and the second temperature may be about 155.degree. C.Type: GrantFiled: April 6, 1998Date of Patent: September 12, 2000Assignee: Micron Technology, Inc.Inventors: Li Li, Don L. Yates
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Patent number: 6093331Abstract: A method for the precise removal of the backside silicon on face down semiconductor devices to obtain a planar surface to allow electron beam microprobe analysis of the semiconductor device. The backside silicon is removed by plasma etching in a fluorocarbon based chemical plasma. The epitaxial layer in a CMOS device acts as an etch stop and the buried oxide layer in an SOI device acts as an etch stop.Type: GrantFiled: December 11, 1997Date of Patent: July 25, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Donald L. Wollesen
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Patent number: 6086775Abstract: A method for preparing coated optical fibers wherein an outer coating is a colored ink coating, and an inner coating is a protective coating, which removes the ink coating while minimizing damage to the protective coating. The method includes uimersing the fiber in a dilute acid bath at a predetermined length of time, removing the fiber from the bath and neutralizing the acid thereon, wiping the remnant ink coating off, and removing the protective coating.Type: GrantFiled: March 13, 1998Date of Patent: July 11, 2000Assignee: Lucent Technologies Inc.Inventors: Louis Ray Pritchett, Jr., Shahabuddin Siddiqui, John Russell Szwec
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Patent number: 6022751Abstract: A process for producing an electronic device having a silicon nitride film on a substrate is provided which comprises steps of forming a silicon nitride film and a silicon oxide film on a first face and a second face reverse to the first face of the substrate respectively, removing the silicon oxide film on the first face by wet etching, removing the silicon nitride film on the first face by wet etching, and removing the silicon oxide film on the second face by wet etching.Type: GrantFiled: October 22, 1997Date of Patent: February 8, 2000Assignee: Canon Kabushiki KaishaInventors: Hitoshi Shindo, Akira Okita
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Patent number: 6007695Abstract: Material of a given chemical type is selectively electrochemically removed from a structure by subjecting portions of the structure to an electrolytic bath. The characteristics of certain parts of the structure are chosen to have electrochemical reduction half-cell potentials that enable removal of the undesired material to be achieved in the bath without applying external potential to any part of the structure. The electrolytic bath can be implemented with liquid that is inherently corrosive to, or inherently benign to, material of the chemical type being selectively removed.Type: GrantFiled: September 30, 1997Date of Patent: December 28, 1999Assignee: Candescent Technologies CorporationInventors: N. Johan Knall, John D. Porter, Christopher J. Spindt
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Patent number: 5996212Abstract: Method of manufacturing a multilayer structure, in which method gold is deposited on a basic layer (3, 11) for forming a gold layer (7, 13), whereafter aluminium oxide is deposited on the gold layer for forming an aluminium oxide layer (9, 15). Silicon oxide is deposited on the aluminium oxide layer by means of PE-CVD for forming a silicon oxide layer (11, 13), and the aluminium oxide layer constitutes an adhesive layer between the gold layer and the silicon oxide layer. Together with the aluminium oxide layer, the silicon oxide layer constitutes an insulating and/or protective cladding layer for the gold layer.Type: GrantFiled: March 18, 1998Date of Patent: December 7, 1999Assignee: U.S. Philips CorporationInventor: Peter S. A. Knapen
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Patent number: 5951880Abstract: A wet etching method for making calibration bump disks for use in providing quality control of production run magnetic hard disks is disclosed. It includes the steps of: (a) coating a layer of bump material on a substrate; (b) coating a photoresist layer on the layer of bump material; (c) exposing the photoresist layer to a light source under a photomask; (d) developing the photoresist layer using a developer solution to form an undeveloped photoresist layer; (e) etching the substrate containing the layer of bump material and the undeveloped photoresist layer to remove portions of the layer of bump material not covered by the undeveloped photoresist layer; and (f) stripping the undeveloped photoresist layer to leave at least a bump on the substrate which was originally covered by the undeveloped photoresist layer. The wet etching method eliminates many of the problems observed from the conventional metal mask method, including the elimination of the convex-shaped bump surface.Type: GrantFiled: May 26, 1997Date of Patent: September 14, 1999Assignee: Trace Storage Tech. Corp.Inventors: Chun-Jen Chen, Ming-Hung Su, Joseph C-C Hung, James Hsi-Tang Lee
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Patent number: 5932114Abstract: An optical module includes support substrate, an optical waveguide on the support substrate, a photoreception device on the support substrate, an optical path conversion part for converting an optical path of an optical beam guided through the optical waveguide from a first optical path to a second optical path that leads to a photodetection area of said photoreception device, wherein the optical path conversion part is provided on the photodetection device as a part thereof, such that the optical beam emitted from the optical waveguide impinges upon the photodetection area of the photoreception device.Type: GrantFiled: September 12, 1997Date of Patent: August 3, 1999Assignee: Fujitsu LimitedInventor: Masao Makiuchi
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Patent number: 5928529Abstract: A composition and method for stripping tin or tin-lead alloys, and any underlying copper-tin intermetallic, from a copper surface. The composition includes an aqueous solution of approximately 5-60% nitric acid by weight, approximately 0.5-30% ferric nitrate by weight, and a nitric acid stabilizer selected from the group consisting of an amino-triazole, an amino-isoxazole, and a linear amino sulfone in the form H.sub.2 N-SO.sub.2 -R, where R is any alkyl or benzene group, wherein the stabilizer is present at a concentration sufficient to inhibit exothermic conditions, emission of toxic NOx gas, and copper attack. A soluble source of halogen ion, such as hydrochloric acid, can be added to the composition to yield a uniform, reflective, bright pink copper appearance, and to further reduce sludge formation. In addition, sludge formation can be eliminated by adding a soluble source of sulfate ion (SO.sub.4.sup.-2) to the composition.Type: GrantFiled: May 11, 1998Date of Patent: July 27, 1999Assignee: Morton International, Inc.Inventor: Scott Campbell
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Patent number: 5919379Abstract: Copper foil having a matte surface and an opposite shiny surface, the shiny surface having thereon a protective metallic coating comprised of a first protective metallic layer, preferably iron, electrodeposited on the shiny surface and a second metallic layer, preferably zinc, electrodeposited on the first layer, the metallic coating be chemically removable without damage to the copper foil and the second metallic layer being softer than the first metallic layer. The matte surface of the copper foil can be bonded to a dielectric material, and the protective metallic coating can be removed from the shiny surface by etching.Type: GrantFiled: December 22, 1997Date of Patent: July 6, 1999Assignee: Foil Technology Development CorporationInventor: John E. Thorpe
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Patent number: 5904545Abstract: Apparatus for assembling microstructures onto a substrate through fluid transport. The apparatus includes a vessel that contains the substrate, a fluid, and microstructures. The substrate has at least one recessed region thereon. The microstructures being shaped blocks self-align into the recessed regions located on the substrate such that the microstructure becomes integral with the substrate. The apparatus also includes a pump that circulates the microstructures within the vessel at a rate where at least one of the microstructures is disposed into the recessed region.Type: GrantFiled: June 7, 1995Date of Patent: May 18, 1999Assignee: The Regents of the University of CaliforniaInventors: John Stephen Smith, Hsi-Jen J. Yeh, Mark A. Hadley, Ashish K. Verma
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Patent number: 5904859Abstract: The specification describes techniques for applying under bump metallization (UBM) for solder bump interconnections on interconnection substrates. The UBM of the invention comprises a Cu, Cu/Cr, Cr multilayer structure. Problems in etching the Cu/Cr layer are overcome using a high pH etchant containing a copper complexing ingredient to prevent passivation of the copper constituent by the chromium etchant solution. With the availability of this etchant the UBM multilayer can be formed using subtractive techniques.Type: GrantFiled: April 2, 1997Date of Patent: May 18, 1999Assignee: Lucent Technologies Inc.Inventor: Yinon Degani
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Patent number: 5879577Abstract: A method is described for selectively etching photoresist on a semiconductor substrate having one or more layers of a spin on glass, including an edge bead that was formed when the glass was originally applied. First the wafer is coated with a layer of unexposed, undeveloped negative photoresist. Then, while spinning the wafer, a vertical jet of photoresist EBR solvent is directed to a point just inside the edge so that photoresist gets removed from an annular area extending inwards from the perimeter. The edge bead is then removed using a liquid etchant and integrated circuit processing can now proceed, making use of the unexposed, undeveloped layer of photoresist in the usual way; that is, exposing it through a mask and then developing and baking it before using it as an etch mask. The method is general and may be used in other situations where selective removal of photoresist along the periphery is required and where the remaining resist is to be used for other purposes.Type: GrantFiled: January 13, 1997Date of Patent: March 9, 1999Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Kuo-Yao Weng, Yeh-Jye Wann
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Patent number: 5863838Abstract: A method of manufacturing a semiconductor device includes providing (51) a substrate (19), providing (52) a colloid (17) having particles held in suspension, providing (53) a reagent (18), disposing (54) the substrate (19) in a processing tool (10), combining (55) the colloid (17) and the reagent (18) to form a slurry (28), decomposing (56) the reagent (18) into a surfactant and an oxidizer, using (57) the slurry (28) to process the substrate (19) in the processing tool (10), and removing (58) the substrate (19) from the processing tool (10).Type: GrantFiled: July 22, 1996Date of Patent: January 26, 1999Assignee: Motorola, Inc.Inventors: Janos Farkas, Melissa Freeman
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Patent number: 5849208Abstract: Miniaturized, self-contained apparatus for conducting bio-chemical reactions and analyses is formed in a compact structure made from a substrate which includes a plurality of reaction chambers and a plurality of analysis chambers which are in fluid communication with the reaction chambers. Independently controllable heaters and coolers are positioned in thermal contact with the reaction chambers to permit parallel processing of biological samples at different temperature cycles. The apparatus is especially useful for performing and analyzing the results of a polymerase chain reaction.Type: GrantFiled: September 7, 1995Date of Patent: December 15, 1998Assignee: MicroFab Technoologies, Inc.Inventors: Donald J. Hayes, David B. Wallace, Christopher J. Frederickson
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Patent number: 5840205Abstract: A method of fabricating a specimen for analyzing defects of a semiconductor device is disclosed. The method includes the steps of: cutting a wafer to be adjacent to a defective portion that exists in a patterned layer formed on a substrate; molding the first specimen with a resin; grinding the substrate of the first specimen with a predetermined slope; and etching the ground face to expose the defective layer, wherein the wafer includes a semiconductor substrate and patterned layers where memory devices are formed on the semiconductor substrate.Type: GrantFiled: July 19, 1996Date of Patent: November 24, 1998Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Jeong-Hoi Koo, Doo-Jin Park
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Patent number: 5840204Abstract: A method for patterning an oxide superconductor thin film, comprising a step of forming a SiO.sub.2 layer on the oxide superconductor thin film, patterning the SiO.sub.2 layer so as to form the same pattern as that of the oxide superconductor thin film which will be patterned, etching the oxide superconductor thin film by using the patterned SiO.sub.2 layer as a mask, and removing the SiO.sub.2 layer by using a weak HF solution, a buffer solution including HF or a mixture including HF.Type: GrantFiled: April 5, 1995Date of Patent: November 24, 1998Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hiroshi Inada, So Tanaka, Michitomo Iiyama
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Patent number: 5804083Abstract: Method of forming a complex, minute three-dimensional structure, known as micromachining, which includes forming a plurality of thin films at least one of which is provided as a temporary layer composed of a lower layer made of an organic material and an upper layer made of an amphoteric metal material which is formed on the lower layer; and selectively removing the temporary layer to provide a three-dimensional structure. The temporary layer may comprise a composite sacrificial layer of photoresist and aluminum.Type: GrantFiled: May 28, 1996Date of Patent: September 8, 1998Assignee: Sharp Kabushiki KaishaInventors: Yorishige Ishii, Tetsuya Inui, Hirotsugu Matoba, Susumu Hirata, Masaharu Kimura, Hajime Horinaka, Shingo Abe, Hiroshi Onda
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Patent number: 5785879Abstract: An object is to densify an internal conductor of a multilayer ceramic part to thereby reduce a line loss, improve operating properties such as Q value, and reduce a variation thereof. To this end, an internal conductor paste which is composed of conductor powder, preferably silver or copper powder and optionally, a glass frit is stacked with dielectric ceramic material layers and co-fired at or above the melting point of the conductor.Type: GrantFiled: January 23, 1997Date of Patent: July 28, 1998Assignee: TDK CorporationInventors: Keizou Kawamura, Makoto Kobayashi, Akira Nakamura, Norikazu Yasuda, Suguru Kondoh, Taro Miura, Shinya Nakai, Tadao Fujii
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Patent number: 5785876Abstract: A layer construction with an organic layer and a transparent cover layer which covers the organic layer and which is harder than the organic layer, and a process for producing such a layer construction in which the cover layer is deposited on the surface of the organic layer from a precursor material present in the gas phase. In order to improve the optical quality of the layer construction, the cover layer, at least in a transition region between the organic layer and the cover layer, is deposited with an index of refraction which differs by a maximum of 20%, in particular by a maximum of 10%, from the index of refraction of the underlying organic layer.Type: GrantFiled: April 22, 1997Date of Patent: July 28, 1998Assignee: Daimler-Benz AGInventors: Hans-Juergen Fuesser, Karl Holdik, Klaus Rohwer, Martin Hartweg
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Patent number: 5779929Abstract: The specification describes a metallization system for barium nanotitanate substrates that provides a combination of high dielectric properties and excellent metal adhesion. It comprises Ti, Pd or Ti/Pd alloy, and copper.Type: GrantFiled: October 7, 1996Date of Patent: July 14, 1998Assignee: Lucent Technologies Inc.Inventors: Tae Yong Kim, Dennis Lyle Krause, Trac Nguyen
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Patent number: 5707538Abstract: A magnetoresitive transducer has an insulating gap layer of variable thickness. The transducer includes a magnetoresistive layer disposed in an active region, and a first magnetic shield layer disposed in the active region and a field region. An insulating layer is spaced between the magnetoresistive layer and the magnetic shield layer. The insulating layer is thinner in the active region than in the field region. The probability of other layers bridging through the insulating layer in the field region is substantially reduced. The method of forming the transducer includes depositing a first insulating layer above the magnetic layer, and then selectively etching the first insulating layer by forming an opening in the active region having a cross-sectional profile sloping inwardly toward the magnetic shield layer. Thereafter, an insulating layer is deposited atop the first insulating layer having the opening.Type: GrantFiled: July 28, 1995Date of Patent: January 13, 1998Assignee: Read-Rite CorporationInventors: Yong Shen, T. C. Chuang
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Patent number: 5705082Abstract: A process for roughening a metal surface is provided comprising applying a coating to the metal surface wherein the coating is a temporary barrier to an etchant attacking the metal surface and the coating is susceptible to the etchant gradually removing the coating, and then etching the coated metal surface with an aqueous bath containing the etchant effective to produce a roughened metal surface.Type: GrantFiled: January 26, 1995Date of Patent: January 6, 1998Assignee: Chromalloy Gas Turbine CorporationInventor: David Hinson
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Patent number: 5676850Abstract: The present invention pertains to a method for making a plurality of barbs. The method is comprised of the steps of first forming a substrate of a first material with a layer of a second material thereon, and at predetermined discrete locations on the layer a third material. Next, there is the step of removing portions of the layer and the substrate such that a frustrum shape is formed on the surface of the substrate. Next, there is the step of removing the third material but leaving the first and second materials essentially untouched. Then, there is the step of reforming the layer made of the second material on the frustrum surface of the substrate. Next, there is the step of removing portions of the layer at essentially the center of the lowest points of the frustrum. There is then the step of removing portions of the substrate but not the second material such that a plurality of barbs is created.Type: GrantFiled: June 7, 1995Date of Patent: October 14, 1997Assignee: Carnegie Mellon UniversityInventors: Michael L. Reed, Lee E. Weiss
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Patent number: 5670062Abstract: In accordance with the invention a metal film structure having tapered sidewalls is made by the steps of applying a first layer of metal on a substrate, applying a second layer of a different material over the first layer, forming a pattern of resist on the second layer and etching the first and second layers in an etchant. The material of the second layer is chosen to interact with the metal of the first layer to increase the lateral etch rate of the second layer, thereby producing a metal film structure having tapered sidewalls. In preferred embodiments, the first layer is Cr, the material of the second layer is Mo, and the etchant is ceric ammonium nitrate. The preferred application of the method is to make conductive thin film lines for thin film transistor arrays used in active matrix liquid crystal displays.Type: GrantFiled: June 7, 1996Date of Patent: September 23, 1997Assignee: Lucent Technologies Inc.Inventors: Cheng-yih Lin, Paul Patrick Mulgrew
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Patent number: 5662818Abstract: A pyroelectric infrared radiation detector for detecting the intensity of infrared radiation with a pyroelectric element is provided. The pyroelectric infrared radiation detector comprises a substrate made of a single crystal material such as (100) magnesium oxide and an infrared radiation detecting structure which comprises a first electrode disposed on the substrate, a pyroelectric thin film disposed on the first electrode, and a second electrode disposed on the pyroelectric thin film for absorption of infrared radiation. The substrate has a recess provided in the upper surface thereof where the infrared radiation detecting structure is seated.Type: GrantFiled: July 31, 1995Date of Patent: September 2, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Nomura, Tutomu Nakanishi, Tokumi Kotani, Keizaburo Kuramasu
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Patent number: 5646064Abstract: A portion of the surface of the first structure is protected by an oxide deposit, and the non-protective layers are etched down to a stop layer. The layers in the etched zone are then built up by molecular beam epitaxy, and one of the built-up layers is given a composition that is different from the composition of the corresponding adjacent layer in the first structure. The method is applicable to fabricating an integrated semiconductor comprising both a laser and a modulator.Type: GrantFiled: January 20, 1995Date of Patent: July 8, 1997Assignee: Alcatel N.V.Inventors: Elisabeth Gaumont-Goarin, Christine Labourie, Jean-Yves Emery