Abstract: A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage.

Abstract: A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions.

Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.

Abstract: A diode is defined on a die. The diode includes a substrate of P conductivity having an upper surface and a lower surface, the substrate having first and second ends corresponding to first and second edges of the die. An anode contacts the lower surface of the substrate. A layer of N conductivity is provided on the upper surface of the substrate, the layer having an upper surface and a lower surface. A doped region of N conductivity is formed at an upper portion of the layer. A cathode contacts the doped region. A passivation layer is provided on the upper surface of the layer and proximate to the cathode.

Abstract: A semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes first and second regions. The first region is provided between the first trenches. The second region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer. The second region has less second conductivity type impurities than the first region.

Abstract: A Shockley diode including: a vertical stack of first to fourth layers of alternated conductivity types between first and second electrodes; a recess formed in the fourth layer and extending vertically to penetrate into the second layer; a first region of same conductivity type as the second layer but of greater doping level, extending at the bottom of the recess in the second layer; and a second region of same conductivity type as the third layer but of greater doping level, extending along the lateral walls of the recess and connecting the first region to the fourth layer.

Abstract: A bi-directional triode thyristor (TRIAC) device for high voltage electrostatic discharge (ESD) protection may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates. The portion of the N-type well region that is interposed between the two P-type well regions may comprise one or more P-type portions, such as a P+ doped plate or a P-type implant.

Abstract: A bidirectional protection component formed in a semiconductor substrate of a first conductivity type including a first implanted area of the first conductivity type, an epitaxial layer of the second conductivity type on the substrate and the first implanted area, a second area of the first conductivity type on the external side of the epitaxial layer, in front of the first area, and implanted with the same dose as the first area, a first metallization covering the entire lower surface of the substrate, and a second metallization covering the second area.

Abstract: An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed.

Abstract: A mesa-type bidirectional Shockley diode including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; a region of the first conductivity type in each of the layers of the second conductivity type; a buried region of the first conductivity type under each of said regions of the first conductivity type, each buried region being complementary in projection with the other; and a groove arranged in the vicinity of the periphery of the component on each of its surfaces, the component portion external to the groove comprising, under the external portion of the upper and lower regions of the second conductivity type, regions of the first conductivity type of same doping profile as said buried regions.

Abstract: An SCR includes a first doped region of a first type having a first doping concentration. A first well of the first type and a first well of a second type are disposed in upper areas of the first doped region of the first type such that the first well of the second type is laterally spaced from the first well of the first type by a non-zero distance. A second doped region of the first type has a second doping concentration that is greater than the first doping concentration and is disposed in the first well of the second type to form an anode of the SCR. A first doped region of the second type is disposed in the first well of the first type and forms a cathode of the SCR.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first trench and a second trench in an n-type substrate surface, the first trenches being spaced apart from each other, the second trench surrounding the first trenches, the second trench being wider than the first trench. The method also includes forming a gate oxide film on the inner surfaces of the first and second trenches, and depositing an electrically conductive material to the thickness a half or more as large as the first trench width. The method further includes removing the electrically conductive material using the gate oxide film as a stopper layer, forming an insulator film thicker than the gate oxide film, and polishing the insulator film by CMP for exposing the n-type substrate and the electrically conductive material in the first trench.

Abstract: A semiconductor device includes a semiconductor layer; a first type of a first semiconductor element that is arranged in a first element region of the semiconductor layer, has first and second main electrodes, and switches current; and a second type of a second semiconductor element that is arranged in a second element region of the semiconductor layer, has third and fourth main electrodes, and freewheels the current. The first and second element regions are adjacent in a direction orthogonal to a direction in which current flows, and are formed in a loop shape over the entire element region when the semiconductor layer is viewed from above. The first main electrode is electrically connected to the third main electrode, and the second main electrode is electrically connected to the fourth main electrode.

Abstract: The present invention provides an ESD protection device comprising a SCR structure that is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation in an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal for the resistor, and the two leading-out terminals are connected by the resistor.

Abstract: One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.

Abstract: Electrostatic discharge (ESD) protection is provided for discharging current between input and output nodes. In accordance with various embodiments, an ESD protection device includes an open-base transistor having an emitter connected to the input node and a collector connected to pass current to the output node via a resistor in response to a voltage at the input node exceeding a threshold that causes the transistor to break down. The resistor is coupled across emitter and collector regions of a second open-base transistor that is configured to turn on for passing current in response to the current across the resistor exceeding a threshold that applies a threshold breakdown voltage across the second transistor. In some implementations, an emitter and/or base of the second transistor are connected to, or are respectively the same region as, a base and a collector of the first transistor.

Abstract: A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions.

Abstract: A manufacturing method and a structure of a surface-mounting type diode co-constructed from a silicon wafer and a base plate, in the method, a diffused wafer is stacked with a high temperature durable high strength base plate to have them sintered and molten together for connecting with each other to form a co-constructure; then the diffused wafer is processed by etching and ditching for filling with insulation material, electrodes of the diffused wafer are metalized and all on an identical plane, then production of all functional lines is completed; and then the co-constructure is cut to form a plurality of separated individuals which each forms a surface-mounting type diode to be applied straight. In comparison with the conventional techniques, manufacturing of the present invention is simplified and economic in reducing working hours, size and cost of production and the wafer is not subjected to breaking during manufacturing.

Abstract: A fast recovery diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. A p-doped anode layer is arranged on the anode side. The anode layer has a doping profile and includes at least two sublayers. A first one of the sublayers has a first maximum doping concentration, which is between 2*1016 cm?3 and 2*1017 cm?3 and which is higher than the maximum doping concentration of any other sublayer. A last one of the sublayers has a last sublayer depth, which is larger than any other sublayer depth. The last sublayer depth is between 90 to 120 ?m. The doping profile of the anode layer declines such that a doping concentration in a range of 5*1014 cm?3 and 1*1015 cm?3 is reached between a first depth, which is at least 20 ?m, and a second depth, which is at maximum 50 ?m. Such a profile of the doping concentration is achieved by using aluminum diffused layers as the at least two sublayers.

Abstract: Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.

Abstract: A transient voltage suppressor (TVS) device includes a semiconductor substrate of a first conductivity type, and a first and a second semiconductor regions of a second conductivity type overlying the semiconductor substrate. A semiconductor layer of the second conductivity type overlies the first and the second semiconductor regions. The TVS device has a first trench extending through the semiconductor layer and the first semiconductor region and into the semiconductor substrate, and a fill material of the second conductivity type disposed in the first trench. A clamping diode in the TVS device has a junction between an out-diffused region from the fill material and a portion of the semiconductor substrate. The TVS device also includes a first P-N diode formed in a first portion of the semiconductor layer, and a second P-N diode having a junction between the second semiconductor region and the semiconductor substrate.

Abstract: Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

Abstract: A structure for starting a semiconductor component including a porous silicon layer in the upper surface of a semiconductor substrate. This porous silicon layer is contacted, on its upper surface side, by a metallization and, on its lower surface side, by a heavily-doped semiconductor region.

Abstract: This disclosure discloses a light-emitting device comprising a substrate; and a plurality of rectifying units, comprising a first rectifying unit and a second rectifying unit, formed on the substrate for receiving and regulating an alternating current signal into a direct current signal. Each of the rectifying units comprises a contact layer and a schottky metal layer. The light-emitting device further comprises a plurality of light-emitting diodes receiving the direct current signal; and a first terminal provided on the substrate and covering the contact layer of the first rectifying unit and the schottky metal layer of the second rectifying unit.

Abstract: Disclosed is a semiconductor component that includes a semiconductor body, a first emitter region of a first conductivity type in the semiconductor body, a second emitter region of a second conductivity type spaced apart from the first emitter region in a vertical direction of the semiconductor body, a base region of one conductivity type arranged between the first emitter region and the second emitter region, and at least two higher doped regions of the same conductivity type as the base region and arranged in the base region. The at least two higher doped regions are spaced apart from one another in a lateral direction of the semiconductor body and separated from one another only by sections of the base region.

Abstract: A semiconductor manufacturing process for wafer-to-wafer stacking of a reconstituted wafer with a second wafer creates a stacked (3D) IC. The reconstituted wafer includes dies, die interconnects and mold compound. When stacked, the die interconnects of the reconstituted wafer correspond to die interconnects on the second wafer. Wafer-to-wafer stacking improves throughput of the manufacturing process. The reconstituted wafer may include dies of different sizes than those in the second wafer. Also, the dies of the reconstituted wafer may be singulated from a wafer having a different size than the second wafer. Thus, this wafer-to-wafer manufacturing process may combine dies and/or wafers of dissimilar sizes.

Abstract: In one general aspect, an apparatus can include a barrier diode including a refractory metal layer coupled to a semiconductor substrate including at least a portion of a PN junction and the apparatus can include an overcurrent protection device operably coupled to the barrier diode.

Abstract: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side of the device. Both the anode and the cathode contacts of the diode are placed on a single side, while a layer of laser treated semiconductor is placed on the opposite side for enhanced cost-effectiveness, photon detection, and fill factor.

Abstract: A mesa-type bidirectional Shockley diode including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; a region of the first conductivity type in each of the layers of the second conductivity type; a buried region of the first conductivity type under each of said regions of the first conductivity type, each buried region being complementary in projection with the other; and a groove arranged in the vicinity of the periphery of the component on each of its surfaces, the component portion external to the groove comprising, under the external portion of the upper and lower regions of the second conductivity type, regions of the first conductivity type of same doping profile as said buried regions.

Abstract: A mesa-type bidirectional Shockley diode delimited on its two surfaces by a peripheral groove filled with a glassivation including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; a region of the first conductivity type in each of the layers of the second conductivity type; a buried region of the first conductivity type under each of the regions of the first conductivity type, at the interface between the substrate and the corresponding layer of the second conductivity type, each buried region being complementary in projection with the other; and a peripheral ring under the external periphery of each of the glassivations, of same doping profile as the buried regions.

Abstract: A mesa-type bidirectional vertical power component, including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; first regions of the first conductivity type in each of the layers of the second conductivity type; and, at the periphery of each of its surfaces, two successive grooves, the internal groove crossing the layers of the second conductivity type, second doped regions of the first conductivity type being formed under the surface of the external grooves and having the same doping profile as the first regions.

Abstract: A diode having a reference voltage electrode, a variable voltage electrode, and a diode material between the electrodes. The diode material is formed of at least one high-K dielectric material and has an asymmetric energy barrier between the reference voltage electrode and the variable voltage electrode, with the energy barrier having a relatively maximum energy barrier level proximate the reference voltage electrode and a minimum energy barrier level proximate the variable voltage electrode.

Abstract: A III-nitride power device that includes a Schottky electrode surrounding one of the power electrodes of the device.

Abstract: A fast recovery rectifier structure with the combination of Schottky structure to relieve the minority carriers during the forward bias condition for the further reduction of the reverse recovery time during switching in addition to the lifetime killer such as Pt, Au, and/or irradiation. This fast recovery rectifier uses unpolished substrates and thick impurity diffusion for low cost production. A reduced p-n junction structure with a heavily p-type doped thin film is provided to terminate and shorten the p-n junction space charge region. This reduced p-n junction with less total charge in the p-n junction to further improve the reverse recovery time. This reduced p-n junction can be used alone, with the traditional lifetime killer method, with the Schottky structure and/or with the epitaxial substrate.

Abstract: In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.

Abstract: The objective of this invention is to provide a semiconductor device having a thyristor that can shorten the turn-off time. A first electroconductive type first semiconductor region 20 is formed on a substrate, and a second electroconductive type second semiconductor region 22, a second electroconductive type third semiconductor region 23, designated as an anode, and a first electroconductive type fourth semiconductor region 24, designated as an anode gate, are formed on the surface layer part of the first semiconductor region. Also, a first electroconductive type fifth semiconductor region 26, designated as a cathode, and a second electroconductive type sixth semiconductor region 25, designated as a cathode gate, are formed on the surface layer part of the second semiconductor region.

Abstract: A Shockley diode including: a vertical stack of first to fourth layers of alternated conductivity types between first and second electrodes; a recess formed in the fourth layer and extending vertically to penetrate into the second layer; a first region of same conductivity type as the second layer but of greater doping level, extending at the bottom of the recess in the second layer; and a second region of same conductivity type as the third layer but of greater doping level, extending along the lateral walls of the recess and connecting the first region to the fourth layer.

Abstract: The present invention provides an ESD protection device comprising a SCR structure that is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation in an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal for the resistor, and the two leading-out terminals are connected by the resistor.

Abstract: In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes. In another embodiment, the ESD devices has an asymmetrical characteristic.

Abstract: A power semiconductor device is provided that includes a depletion mode (normally ON) main switching device cascoded with a higher speed switching device, resulting in an enhancement mode (normally OFF) FET device for switching power applications. The main switching device comprises a depletion mode GaN-based HEMT (High Electron Mobility Transistor) FET that does not include an intrinsic body diode. In one or more embodiments, the higher speed switching device comprises a high speed FET semiconductor switch arranged or connected in parallel with a Schottky diode. The high speed FET semiconductor switch may comprise a Si FET, GaN FET or any other type of FET which possesses higher speed switching capabilities and a lower voltage than that of the GaN-based HEMT FET. In some embodiments, the GaN-based HEMT FET and the higher speed switching device (i.e., the FET and Schottky diode) may be monolithically integrated on the same substrate.

Abstract: A manufacturing method and a structure of a surface-mounting type diode co-constructed from a silicon wafer and a base plate, in the method, a diffused wafer is stacked with a high temperature durable high strength base plate to have them sintered and molten together for connecting with each other to form a co-constructure; then the diffused wafer is processed by etching and ditching for filling with insulation material, electrodes of the diffused wafer are metalized and all on an identical plane, then production of all functional lines is completed; and then the co-constructure is cut to form a plurality of separated individuals which each forms a surface-mounting type diode to be applied straight. In comparison with the conventional techniques, manufacturing of the present invention is simplified and economic in reducing working hours, size and cost of production and the wafer is not subjected to breaking during manufacturing.

Abstract: A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.

Abstract: A transient voltage suppressor (TVS) device includes a semiconductor substrate of a first conductivity type, and a first and a second semiconductor regions of a second conductivity type overlying the semiconductor substrate. A semiconductor layer of the second conductivity type overlies the first and the second semiconductor regions. The TVS device has a first trench extending through the semiconductor layer and the first semiconductor region and into the semiconductor substrate, and a fill material of the second conductivity type disposed in the first trench. A clamping diode in the TVS device has a junction between an out-diffused region from the fill material and a portion of the semiconductor substrate. The TVS device also includes a first P-N diode formed in a first portion of the semiconductor layer, and a second P-N diode having a junction between the second semiconductor region and the semiconductor substrate.

Abstract: A nitride semiconductor laser device uses a substrate with low defect density, contains reduced strains inside a nitride semiconductor film, and thus offers a satisfactorily long useful life. On a GaN substrate (10) with a defect density as low as 106 cm?2 or less, a stripe-shaped depressed portion (16) is formed by etching. On this substrate (10), a nitride semiconductor film (11) is grown, and a laser stripe (12) is formed off the area right above the depressed portion (16). With this structure, the laser stripe (12) is free from strains, and the semiconductor laser device offers a long useful life. Moreover, the nitride semiconductor film (11) develops reduced cracks, resulting in a greatly increased yield rate.

Abstract: A fast injection optical switch is disclosed. The optical switch includes a thyristor having a plurality of layers including an outer doped layer and a switching layer. An area of the thyristor is configured to receive a light beam to be directed through at least one of the plurality of layers and exit the thyristor at a predetermined angle. At least two electrodes are coupled to the thyristor and configured to enable a voltage to be applied to facilitate carriers from the outer doped layer to be directed to the switching layer. Sufficient carriers can be directed to the switching layer to provide a change in refractive index of the switching layer to redirect at least a portion of the light beam to exit the thyristor at a deflection angle different from the predetermined angle.

Abstract: In an embodiment, a integrated semiconductor device includes a first Vertical Junction Field Effect Transistor (VJFET) having a source, and a gate disposed on each side of the first VJFET source, and a second VJFET transistor having a source, and a gate disposed on each side of the second VJFET source. At least one gate of the first VJFET is separated from at least one gate of the second VJFET by a channel. The integrated semiconductor device also includes a Junction Barrier Schottky (JBS) diode positioned between the first and second VJFETs. The JBS diode comprises a metal contact that forms a rectifying contact to the channel and a non-rectifying contact to at least one gate of the first and second VJFETs, and the metal contact is an anode of the JBS diode.

Abstract: A Schottky or PN diode is formed where a first cathode portion is an N epitaxial layer that is relatively lightly doped. An N+ buried layer is formed beneath the cathode for conducting the cathode current to a cathode contact. A more highly doped N-well is formed, as a second cathode portion, in the epitaxial layer so that the complete cathode comprises the N-well surrounded by the more lightly doped first cathode portion. An anode covers the upper areas of the first and second cathode portions so both portions conduct current when the diode is forward biased. When the diode is reverse biased, the depletion region in the central N-well will be relatively shallow but substantially planar so will have a relatively high breakdown voltage. The weak link for breakdown voltage will be the curved edge of the deeper depletion region in the lightly doped first cathode portion under the outer edges of the anode. Therefore, the N-well lowers the on-resistance without lowering the breakdown voltage.

Abstract: Embodiments of the present invention are directed to reconfigurable two-terminal electronic switch devices (100) comprising a compound (102) sandwiched between two electrodes (104,106). These devices are configured so that the two electrode/compound interface regions can be either rectifying or conductive, depending on the concentration of dopants at the respective interface, which provides four different device operating characteristics. By forcing charged dopants into or out of the interface regions with an applied electric field pulse, a circuit element can be switched from one type of stable operation to another in at least three different ways. A family of devices built to express these properties display behaviors that provide new opportunities for nanoscale electronic devices.

Abstract: An ESD protection structure includes a structure to be protected disposed in a semiconductor body. A region of a first conductivity type is disposed within the semiconductor body and a channel is disposed in the semiconductor body and extends through the region of the first conductivity type. A semiconductor of a second conductivity type is disposed within the channel adjacent the region of the first conductivity type such that the region of the first conductivity type and the semiconductor of the second conductivity type form a diode. At least one of the region of the first conductivity type and the semiconductor of the second conductivity type is electrically coupled to the structure to be protected.

Abstract: An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed.