Abstract: A micro electron gun that is capable of extracting electrons from a semiconductor utilizing a quantum size effect and that can be mounted individually for each of pixels is disclosed, as well as a picture display apparatus using such electron guns which is high in quantum efficiency, of high brightness and thin, as well as methods of manufacture thereof. Conduction electrons from a n-type semiconductor substrate (2) are accelerated under an electric field through a layer or layers (4) of quantum size effect micro particles (3) formed on surfaces of the n-type semiconductor substrate (2) and passed therethrough without undergoing phonon scattering, so that they when arriving at an electrode (5) may possess an amount of energy not less than the work function of the electrode (5) and are thus allowed to spring out into a vacuum.

Abstract: A CMOS image sensor for improving a characteristic of transmittance therein is provided by forming a convex-shaped color filter pattern that acts as a micro-lens. The CMOS image sensor includes a semiconductor structure having a photodiode and a peripheral circuit, an insulating layer that is formed on the semiconductor structure and that has a trench, and a convex-shaped color filter pattern formed on the insulating layer and covering the trench.

Abstract: A group III nitride film is formed on an epitaxial substrate having an underlayer film containing Al. According to the present invention, the change of the properties of the II nitride film may be reduced The properties of the semiconductor device may be thus reduced and the production yield may be improved. An underlayer 2 made of a group III nitride containing at least Al is formed on a substrate 1 made of a single crystal. An oxide film 3 is formed on the underlayer film 2 to produce an epitaxial substrate 10. The oxygen content of the oxide film 3 at the surface is not lower than 3 atomic percent and the thickness is not larger than 50 angstrom.

Abstract: A field emission display device (1) includes a cathode plate (20), a resistive buffer (30) in contact with the cathode plate, a plurality of electron emitters (40) formed on the buffer, and an anode plate (50) spaced from the electron emitters. Each electron emitter includes a rod-shaped first part (401) and a conical second part (402). The buffer and first parts are made from silicon oxide. The combined buffer and first parts has a gradient distribution of electrical resistivity such that highest electrical resistivity is nearest the cathode plate and lowest electrical resistivity is nearest the anode plate. The second parts are made from niobium. When emitting voltage is applied between the cathode and anode plates, electrons emitted from the electron emitters traverse an interspace region and are received by the anode plate. Because of the gradient distribution of electrical resistivity, only a very low emitting voltage is needed.

Abstract: Indium Nitride (InN) and Indium-rich Indium Gallium Nitride (InGaN) quantum dots embedded in single and multiple InxGa1−xN/InyGa1−yN quantum wells (QWs) are formed by using TMIn and/or Triethylindium (TEIn), Ethyldimethylindium (EDMIn) as antisurfactant during MOCVD growth, wherein the photoluminescence wavelength from these dots ranges from 480 nm to 530 nm. Controlled amounts of TMIn and/or other Indium precursors are important in triggering the formation of dislocation-free QDs, as are the subsequent flows of ammonia and TMIn. This method can be readily used for the growth of the active layers of blue and green light emitting diodes (LEDs).

Abstract: An emitter includes an electron supply layer, a dielectric layer on the electron supply layer defining an emission area, and a filled zeolite emission layer within the defined emission area and in contact with the electron supply layer. The filled zeolite emission layer holds a semiconductor material within the cage of the zeolite.

Abstract: A memory for an integrated circuit and method of fabricating same are provided, comprising providing an array of magnetic memory devices, preferably TMR junctions, that are configured as individual studs and protrude from a substrate. A layer of insulating spacer material is deposited over the array of magnetic memory devices, and a spacer etch is performed to remove the spacer material preferentially from the top surfaces of the magnetic memory devices and from substrate surface areas between the magnetic memory devices. Preferably, the insulating spacer material is low k and/or a barrier to outdiffusion of species from the TMR junctions. Examples include silicon carbide (BLOk™), low temperature silicon nitride or diamond-like carbon. In another embodiment, the insulating spacer material is also a magnetic material and may comprise magnesium-zinc ferrites or nickel-zinc ferrites.

Abstract: The present invention relates to the use of an electron source in a lithography system for producing a plurality of electron beams directed towards an object to be processed, said electron source comprising a plurality of field emitters, characterized in that said electron source comprises a semiconductor layer with a plurality of tips, said use including the steps of:

Abstract: The present invention is related to methods and apparatus to produce a memory cell or resistance variable material with improved data retention characteristics and higher switching speeds. In a memory cell according to an embodiment of the present invention, silver selenide and a chalcogenide glass, such as germanium selenide (GexSe(1−x)) are combined in an active layer, which supports the formation of conductive pathways in the presence of an electric potential applied between electrodes. Advantageously, embodiments of the present invention can be fabricated with relatively wide ranges for the thicknesses of the silver selenide and glass layers.

Abstract: A method for removing a surface protrusion projecting from a layer of a first material deposited on a surface of a substrate. In accordance with one embodiment of the invention, a layer of a second material is applied on the layer of first material. A sufficient quantity of the second material is removed to expose the surface protrusion. The first material exposed through the surface protrusion is then removed.

Abstract: A device isolation process flow for an atomic resolution storage (ARS) system inserts device isolation into a process flow of the ARS system so that diodes may be electrically insulated from one another to improve signal to noise ratio. In addition, since most harsh processing is done prior to depositing a phase change layer, which stores data bits, process damage to the phase change layer may be minimized.

Abstract: An alicyclic epoxy resin is used as a material for forming a member for sealing a Group III nitride compound semiconductor light-emitting device.

Abstract: An EPROM-like memory includes a substrate having a source region, a drain region, and a channel. The memory includes a gate stack formed by a gate oxide, a storage electrode, a second gate oxide and a gate electrode. The gate oxide is configured on the substrate above the channel. The storage electrode is configured on the gate oxide. The second gate oxide is configured on the storage electrode. The gate electrode is configured on the second gate oxide. The memory includes an interspace that is configured between the drain region and the storage electrode. The interspace is filled with a gas or contains a vacuum. The memory includes an outer spacing web that is configured laterally beside the gate stack. The outer spacing web is also configured on the drain region. The outer spacing web is made of doped polycrystalline silicon.

Abstract: In order to provide a thin-film electron emitter device of a structure wherein electric connection between a top electrode and top electrode busline can be secured and also to provide a display apparatus using the thin-film electron emitter device, the top electrode busline thin on its connection side with the top electrode is formed on a field insulator which is thicker than an insulator forming electron emission areas and which is formed around the insulator, and the top electrode covers the top electrode busline to be connected with said thin part of said top electrode busline.

Abstract: An image display device using transistors each having a polycrystalline semiconductor layer constructed so that drain and source regions are fully activated, and a manufacturing method thereof. The polycrystalline semiconductor layer is so provided that impurity concentrations are easy to control in LDD regions . The image display device further uses transistors having a gate electrode on an upper surface of the semiconductor layer with an insulating film therebetween, a drain region formed on one side of the gate electrode, and a source region formed on another side of the gate electrode. An activated P-type impurity is added to the area underlying the gate electrode, and an activated N-type impurity is added to the area excluding the area underlying the gate electrode.

Abstract: An integrated inductor is formed on an integrated circuit or other substrate. The inductor is formed of a stack of almost totally enclosed rings of conductive material in which each ring has a single gap. Vias connect adjacent rings on opposite sides of their gaps so as to form a coil shaped structure. The inductor has applications in filtering, in an oscillator, in an antenna, combined with an active detection circuit, combined with an electron source, in a microelectromechanial systems or MEMS, or the like. The inductor may be formed in a vertical orientation or in a horizontal orientation. Chemical mechanical polishing may be used for planarizing layers.

Abstract: An emitter has a rapid thermal process (RTP) formed emission layer of SiO2, SiOxNy or combinations thereof. The emission layer formed by rapid thermal processing does not require electroforming to stabilize the film. The RTP grown films are stable and exhibit uniform characteristics from device to device.

Abstract: A light emitting element suitable for a blue light lamp in a signal light apparatus is provided. The group III nitride compound semiconductor light emitting element includes a first light emitting layer for emitting a first light having a blue light and a second light emitting layer for emitting a second light having a green light. The first light and the second light are combined to provide a third light having a blue-green light synthesized from the first light and the second light.

Abstract: A field emission display device and a method of fabricating the same are provided. The field emission display device includes a substrate, a transparent cathode layer, an insulation layer, a gate electrode, a resistance layer, and carbon nanotubes. The transparent cathode layer is deposited on the substrate. The insulation layer is formed on the cathode layer and has a well exposing the cathode layer. The gate electrode is formed on the insulation layer and has an opening corresponding to the well. The resistance layer is formed to surround the surface of the gate electrode and the inner walls of the opening and the well so as to block ultraviolet rays. The carbon nanotube field emitting source is positioned on the exposed cathode layer. An alignment error between the gate electrode and the cathode is removed, and carbon nanotube paste is prevented from remaining during development, thereby preventing current leakage and short circuit between the electrodes and diode emission.

Abstract: An emitter includes an electron source and a cathode. The cathode has an emissive surface. The emitter further includes a continuous anisotropic conductivity layer disposed between the electron source and the emissive surface of the cathode. The anisotropic conductivity layer has an anisotropic sheet resistivity profile and provides for substantially uniform emissions over the emissive surface of the emitter.

Abstract: A controllable source of few photons at predetermined wavelength. According to the invention, said source comprises a solid material (10) having a dilute concentration of elements (11) implanted therein that emit light at said predetermined wavelength, an excitation device (20) for exciting said light-emitting elements, and a probe (30) suitable for capturing, by near field coupling, at least one photon emitted by one of the light-emitting elements. The source is applicable to optical telecommunications.

Abstract: An improved FED driving method, which uses a voltage control different from the prior FED, to turn an electron beam on/off and increase the resolution. The improved FED driving method is characterized in increasing a positive voltage applied to the FED's anode, grounding the FED's emitter and applying a negative voltage to the FED's gate. When driving the FED, the anode can pull electron beam out of the cathode with high accelerate voltage and the applied negative voltage on the gate can turn the electron beam on/off. As such, this allows a higher resolution because the electron beam is not influenced by the gate's lateral attraction and high lighting efficiency with high anode accelerate voltage.

Abstract: The present invention provides a field emission device driven with a high voltage. The field emission device of the present invention includes a resistor connected between a gate electrode and an external terminal to prevent a leakage current by an electrical connection between the gate electrode and the emitter. Therefore, the power consumption of the device is decreased and the operating characteristic of the device is improved.

Abstract: A semiconductor light-emitting device has a lower clad layer, an active layer, a p-type GaP layer and an upper clad layer, which are successively formed on an n-type GaAs substrate. The p-type GaP layer has a higher energy position by 0.10 eV than the upper clad layer in the conduction band, which makes it more difficult to let electrons escape from the active layer. This contributes to increase of the probability of radiative recombination between electrons and holes in the active layer, and thereby, luminance of the semiconductor light-emitting device is improved. The p-type GaP layer is effective in a semiconductor light-emitting device having a short wavelength in particular.

Abstract: Certain embodiments relate to semiconductor devices having an improved dielectric strength and methods for manufacturing the same. A semiconductor device 1000 may have a field effect transistor 100. The field effect transistor 100 includes a gate dielectric layer 30, a source region 32 and a drain region 34. A semi-recessed LOCOS layer 40 may be provided between the gate dielectric layer 30 and the drain region 34. An offset impurity layer 42 may be provided below the semi-recessed LOCOS layer 40.

Abstract: A cold electron emitter may include a heavily n+ doped wide band gap (WBG) substrate, a p-doped WBG region, and a low work function metallic layer (n+-p-M structure). A modification of this structure includes heavily p+ doped region between p region and M metallic layer (n+-p-p+-M structure). These structures make it possible to combine high current emission with stable (durable) operation. The high current density is possible because the p-doped (or p+ heavily doped) WBG region acts as a negative electron affinity material when in contact with low work function metals. The injection emitters with the n+-p-M and n+-p-p+-M structures are stable since the emitters make use of relatively low extracting electric field and are not affected by contamination and/or absorption from accelerated ions. In addition, the structures may be fabricated with current state-of-the-art technology.

Abstract: A single electron tunneling transistor which has a multi-layer structure exhibiting a single electron tunneling effect even with processing accuracy of not greater than 0.1 &mgr;m. The multi-layer structure of the single electron tunneling transistor is characterized by alternately growing an electrically conductive layer and a tunneling barrier layer. The number of layers is 50 or more. The structure has a minute tunneling junction having an area on the order of 1 &mgr;m square.

Abstract: The invention concerns a light emitting and guiding device comprising at least one active region (22) in silicon and the means for creating photons in the said active region. In accordance with the invention, the means for creating the photons comprise a diode (22c, 22d) formed in the active region. In addition, the device includes the means for confining the carriers injected by the diode, and the silicon in the active region is mono-crystalline.

Abstract: An n-GaN layer is provided as an emitter layer for supplying electrons. A non-doped (intrinsic) AlxGa1−xN layer (0≦x≦1) having a compositionally graded Al content ratio x is provided as an electron transfer layer for transferring electrons toward the surface. A non-doped AlN layer having a negative electron affinity (NEA) is provided as a surface layer. Above the AlN layer, a control electrode and a collecting electrode are provided. An insulating layer formed of a material having a larger electron affinity than that of the AlN layer is interposed between the control electrode and the collecting electrode. This provides a junction transistor which allows electrons injected from the AlN layer to conduct through the conduction band of the insulating layer and then reach the collecting electrode.

Abstract: An emitter has an electron supply and a porous cathode layer having nanohole openings. The emitter also has a tunneling layer disposed between the electron supply and the cathode layer.

Abstract: This photocathode comprises: InP substrate 1; InAsx2P1−x2(0<x2<1) buffer layer 2; Inx1Ga1−x1As (1>x1>0.53) light-absorbing layer 3; InAsx3P1−x3 (0<x3<1) electron-emitting layer 4; InAsx3P1−x3 contact layer 5 formed on the electron-emitting layer 4; active layer 8 of an alkali metal or its oxide or fluoride formed on the exposed surface of electron-emitting layer 4; and electrodes 6 and 7.

Abstract: A method and a system for static timing analysis of a latch-based circuit. A netlist data structure represents the latch-based circuit. The method statically analyzes the netlist data structure and produces timing information for signal paths within the latch-based circuit. The signal paths are filtered using path termination information, which specifies where paths end. The path termination information distinguishes a first signal path that terminates at a latch from a second signal path that flows through that same latch.

Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the tunneling layer is formed. A cathode layer is formed on the tunneling layer. A conductive layer is partially disposed on the cathode layer and partially on the insulator layer if present. The conductive layer defines an opening to provide a surface for energy emissions of electrons and/or photons. Preferably but optionally, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: There are provided a semiconductor laser, a semiconductor light emitting device, and methods of manufacturing the same wherein a threshold current density in a short wavelength semiconductor laser using a nitride compound semiconductor can be reduced. An active layer is composed of a single gain layer having a thickness of more than 3 nm, and optical guiding layers are provided between the active layer and cladding layers respectively.

Abstract: A dynamic semiconductor memory device includes memory cells each having a one-transistor/one-capacitor. The memory cells are arranged at their respective intersections of bit lines and word lines. Bit-line precharge circuits are provided at bit line pairs, respectively, to precharge and equalize the bit line pairs. An output potential of a plate potential generator is applied to the power supply terminals of the bit-line precharge circuits. The memory cells have a plurality of capacitors. A plate electrode of the capacitors are connected in common. An insulation film is formed on the plate electrode and a wiring layer is formed on the insulation film. The wiring layer is electrically connected to the plate electrode through a via hole formed in the insulation film and connected in common to the power supply terminals of the bit-line precharge circuits through a contact hole formed in the insulation film, thereby transmitting a potential in proportion to variations in plate potential.

Abstract: A cold electron emitter may include a heavily a p-doped semiconductor, and dielectric layer, and a metallic layer (p-D-M structure). A modification of this structure includes a heavily n+ doped region below the p region (n+-p-D-M structure). These structures make it possible to combine high current emission with stable (durable) operation. The high current density is possible since under certain voltage drop across the dielectric layer, effective negative electron affinity is realized for the quasi-equilibrium “cold” electrons accumulated in the depletion layer in the p-region next to the dielectric layer. These electrons are generated as a result of the avalanche in the p-D-M structure or injection processes in the n+-p-D-M structure. These emitters are stable since they make use of relatively low extracting field in the vacuum region and are not affected by contamination and absorption from accelerated ions.

Abstract: A field emission display that is simple to manufacture in a large screen size and that provides improved display characteristics, includes first and second substrates provided opposing one another with a predetermined gap therebetween; a plurality of gate electrodes formed on a surface of the first substrate opposing the second substrate, the gate electrodes being formed in a striped pattern; an insulation layer formed on the first substrate covering the gate electrodes; a plurality of cathode electrodes formed on the insulation layer in a striped pattern to perpendicularly intersect the gate electrodes; a plurality of surface electron sources formed along one long edge of the cathode electrodes; focusing units provided on the cathode electrodes for controlling the emission of electron beams from the surface electron sources; an anode electrode formed on a surface of the second substrate opposing the first substrate; and a plurality of phosphor layers formed on the anode electrode.

Abstract: An electron emitter, such as for a display, has a substrate and regions of n-type material and p-type material on the substrate arranged such that there is an interface junction between the regions exposed directly to vacuum for the liberation of electrons. The p-type region may be a thin layer on top of the n-type region or the two regions may be layers on adjacent parts of the substrate with adjacent edges forming the interface junction. Alternatively, there many be multiple interface junctions formed by p-type particles or by both p-type and n-type particles. The particles may be deposited on the substrate by an ink-jet printing technique. The p-type material is preferably diamond, which may be activated to exhibit negative electron affinity.

Abstract: A memory for an integrated circuit and method of fabricating same are provided, comprising providing an array of magnetic memory devices, preferably TMR junctions, that are configured as individual studs and protrude from a substrate. A layer of insulating spacer material is deposited over the array of magnetic memory devices, and a spacer etch is performed to remove the spacer material preferentially from the top surfaces of the magnetic memory devices and from substrate surface areas between the magnetic memory devices. Preferably, the insulating spacer material is low k and/or a barrier to outdiffusion of species from the TMR junctions. Examples include silicon carbide (BLOk™), low temperature silicon nitride or diamond-like carbon. In another embodiment, the insulating spacer material is also a magnetic material and may comprise magnesium-zinc ferrites or nickel-zinc ferrites.

Abstract: A method for promoting the passage of elementary particles at or through a potential barrier comprising providing a potential barrier having a geometrical shape for causing de Broglie interference between said elementary particles is disclosed. In another embodiment, the invention provides an elementary particle-emitting surface having a series of indents. The depth of the indents is chosen so that the probability wave of the elementary particle reflected from the bottom of the indent interferes destructively with the probability wave of the elementary particle reflected from the surface. This results in the increase of tunneling through the potential barrier. When the elementary particle is an electron, then electrons tunnel through the potential barrier, thereby leading to a reduction in the effective work function of the surface.

Abstract: The subject of the disclosed technique is as follows: a structure in a ridge type semiconductor optical device having both high operation speed and high reliability together is attained.

Abstract: The present invention is for a method of preparing a surface of niobium. The preparation method includes polishing, cleaning, baking and irradiating the niobium surface whereby the resulting niobium surface has a high quantum efficiency.

Abstract: An image forming apparatus includes an electron source having a substrate on which a plurality of electron emitting devices are arranged, and a face plate provided with striped fluorescent substances for emitting light of different colors and serving to form a color image upon irradiation of electrons by the electron source. Rectangular spacers are arranged between the substrate and the face plate, and are fixed to the substrate and contact the face plate. A longitudinal direction of the spacers crosses a longitudinal direction of the striped fluorescent substances at a substantially right angle.

Abstract: Field emission transistors where either N type or P type devices are made with an insulated gate isolated from both the emitter and the collector. Such devices have input voltage levels that match the output levels, and as such are fully cascadable and integrable. Emitter and collector functions are combined in combinations to make complimentary pairs, NAND gates and NOR gates.

Abstract: In a field emission-type electron source (10), lower electrodes (8) made of an electroconductive layer, a strong field drift layer (6) including drift portions (6a) made of an oxidized or nitrided porous semiconductor, and surface electrodes (7) made of a metal layer are provided on an upper side of a dielectric substrate (11) made of glass. When voltage is applied to cause the surface electrodes (7) to be anodic with respect to the lower electrodes (8), electrons injected from the lower electrodes (8) to the strong field drift layer (6) are led to drift through the strong field drift layer (6) and are emitted outside through the surface electrodes (7). A pn-junction semiconductor layer composed of an n-layer (21) and a p-layer (22) is provided between the lower electrode (8) and the strong field drift layer (6) to prevent a leakage current from flowing to the surface electrode (7) from the lower electrode (8), thereby reducing amount of power consumption.

Abstract: A field emission display has electron emitters that are current-limited by implanting in a silicon layer only enough ions to produce a desired current, and then forming emitters from the silicon layer by isotropic etching.

Abstract: The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field effect transistor includes a semiconductive layer configured to form a channel region; a pair of spaced conductively doped semiconductive regions in electrical connection with the channel region of the semiconductive layer; a gate intermediate the semiconductive regions; and a gate dielectric layer intermediate the semiconductive layer and the gate, the gate dielectric layer being configured to align the gate with the channel region of the semiconductive layer. In one aspect, chemical-mechanical polishing self-aligns the gate with the channel region. According to another aspect, a field emission device, includes a transistor configured to control the emission of electrons from an emitter.

Abstract: The invention relates to discrete, spaced-apart ferroelectric polymer memory device embodiments. The ferroelectric polymer memory device is fabricated by spin-on polymer processing and etching using photolithographic technology. The size of the discrete, spaced-apart ferroelectric polymer structures may be tied to a specific photolithography minimum feature dimension.

Abstract: An emitter substructure and methods for manufacturing the substructure are described. A substrate has a p-region formed at a surface of the substrate. A n-tank is formed such that the p-region surrounds a periphery of the n-tank. An emitter is formed on and electrically coupled to the n-tank. A dielectric layer is formed on the substrate that includes an opening surrounding the emitter. An extraction grid is formed on the dielectric layer. The extraction grid includes an opening surrounding and in close proximity to a tip of the emitter. An insulating region is formed at a lower boundary of the n-tank. The insulating region electrically isolates the emitter and the n-tank along at least a portion of the lower boundary beneath the opening. The insulating region thus functions to displace a depletion region associated with a boundary between the p-region and the n-tank from an area that can be illuminated by photons traveling through the extraction grid or openings in the extraction grid.

Abstract: A field emission array (FEA) using carbon nanotubes having characteristics of low work function, durability and thermal stability, and a method for fabricating the same are provided. The field emission array uses carbon nanotubes as electron emission sources, thereby lowering a work function and dropping driving voltage. Accordingly, a device can be driven at low voltage. In addition, resistance to gases, which are generated during the operation of a device, is improved, thereby increasing the life span of an emitter. The method prints a mixed paste using extrusion or screen printing and performs sintering, thereby fusing carbon nanotubes such that the carbon nanotubes are aligned in a single direction.