Lateral Patents (Class 257/122)
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Patent number: 10854456Abstract: Methods for fabricating a transistor and an electro-static discharge (ESD) device are provided. In a method, a first well area doped with a first well ion is formed in a base substrate. A second well area is doped with a second well ion in the base substrate. The second well area includes a first region adjacent to the first well area. A first ion doping region doped with first ions is formed in the first well area and the first region. A type of the first ions is the same as a type of the first well ion and opposite to a type of the second well ion. A gate structure is formed on a part of the first well area and at least a part of the first region.Type: GrantFiled: July 11, 2019Date of Patent: December 1, 2020Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Yong Li, Cheng Qing Wei
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Patent number: 10784369Abstract: A high-voltage semiconductor device includes a semiconductor substrate having a first conductivity type, a source region and a drain region disposed on the semiconductor substrate. The drain region has a second conductivity type that is the opposite of the first conductivity type, and the source region includes a part having the first conductivity type and another part having the second conductivity type. The device includes a first and a second isolation structures disposed on two opposite sides of the drain region. The first isolation structure is between the source and the drain region. The device includes a first well region disposed below the second isolation structure. The top surface of the first well region is adjacent to the bottom surface of the second isolation structure. In addition, the device includes a first buried layer disposed in the semiconductor substrate and that overlaps the first well region.Type: GrantFiled: April 9, 2019Date of Patent: September 22, 2020Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Vivek Ningaraju, Vinay Suresh, Po-An Chen
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Patent number: 10505012Abstract: An insulated gate bipolar transistor (IGBT) includes a substrate, including a device region and a collection region, arranged into a bilayer structure. The device region includes a plurality of control regions and a plurality of turn-off regions. The IGBT also includes a drift region formed in the control regions and the turn-off regions, and electrically connected to the collection region; a well region formed in the control regions and the turn-off regions, and in contact with the drift region; a plurality of first gate structures formed in the control regions, and in contact with the drift region and the well region; and a plurality of emission regions formed in the well region of the control regions, and on at least one side of each first gate structure. The emission regions are isolated from the drift region, and are electrically connected to the well region of the turn-off regions.Type: GrantFiled: January 29, 2018Date of Patent: December 10, 2019Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconducor Manufacturing International (Beijing) CorporationInventor: Lei Bing Yuan
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Patent number: 10395931Abstract: A method is provided for fabricating an LDMOS transistor. The method includes providing a base substrate. The method also includes forming a first well area doped with a first well ion in the base substrate. In addition, the method includes forming a second well area doped with a second well ion in the base substrate, where the second well area includes a first region adjacent to the first well area. Moreover, the method includes forming a first ion doping region doped with first ions in the first well area and the first region, where a type of the first ions is the same as a type of the first well ion and opposite to a type of the second well ion. Further, the method includes forming a gate structure on part of the first well area and part of the first region.Type: GrantFiled: March 28, 2017Date of Patent: August 27, 2019Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Yong Li, Cheng Qing Wei
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Patent number: 10211200Abstract: The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.Type: GrantFiled: January 30, 2018Date of Patent: February 19, 2019Assignee: INDIAN INSTITUTE OF SCIENCEInventors: Mayank Shrivastava, Milova Paul, Christian Russ, Harald Gossner
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Patent number: 10033177Abstract: An electrostatic protection circuit includes a trigger circuit that is connected between a first power line and a second power line. The trigger circuit is configured to output a trigger signal in response to a voltage fluctuation between the first and second power lines. A shunt element has a main current path between the first power line and the second power line and is controllable to be on and off using the trigger signal. A control circuit is configured to supply a control signal to turn off the shunt element when a current value of the main current path of the shunt element exceeds a predetermined threshold value.Type: GrantFiled: February 9, 2016Date of Patent: July 24, 2018Assignee: Kabushiki Kaisha ToshibaInventor: Kazuhiro Kato
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Patent number: 9537002Abstract: A base layer is used that has an N-type SiC layer formed in a surface layer on the front surface side of an N-type SiC substrate, and a P-type region is formed on a surface of the N-type SiC layer with an N-type source region selectively formed in a surface layer of the P-type region. A source electrode is formed on a surface of the N-type source region and a drain electrode is formed on the back surface side of the N-type SiC substrate. Additionally, the gate electrode is formed via a gate insulation film only on a surface of the P-type region. In this way, high electric field is no longer applied to the gate insulation film on the surface of the N-type SiC layer due to stoppage of voltage application to the gate electrode.Type: GrantFiled: March 18, 2013Date of Patent: January 3, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yuichi Harada, Noriyuki Iwamuro, Yasuyuki Hoshi, Shinsuke Harada
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Patent number: 9461035Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.Type: GrantFiled: December 19, 2013Date of Patent: October 4, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Derek W. Robinson, Amitava Chatterjee
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Patent number: 9419085Abstract: A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.Type: GrantFiled: November 9, 2015Date of Patent: August 16, 2016Assignee: MaxPower Semiconductor, Inc.Inventors: Mohamed N. Darwish, Amit Paul
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Patent number: 9196724Abstract: A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.Type: GrantFiled: January 20, 2015Date of Patent: November 24, 2015Assignee: MaxPower Semiconductor Inc.Inventors: Mohamed N. Darwish, Amit Paul
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Patent number: 9006863Abstract: A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated.Type: GrantFiled: December 23, 2011Date of Patent: April 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Peng Hsieh, Jaw-Juinn Horng
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Patent number: 8952418Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.Type: GrantFiled: March 1, 2011Date of Patent: February 10, 2015Assignee: Micron Technology, Inc.Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
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Patent number: 8946769Abstract: A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.Type: GrantFiled: January 30, 2014Date of Patent: February 3, 2015Assignee: MaxPower Semiconductor Inc.Inventors: Mohamed N. Darwish, Amit Paul
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Patent number: 8709929Abstract: Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion regions in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of the one or more diffusion regions being less than about 40% greater than the first width.Type: GrantFiled: September 5, 2012Date of Patent: April 29, 2014Assignee: Micron Technology, Inc.Inventors: Lequn Liu, Yongjun Jeff Hu, Anish A. Khandekar
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Patent number: 8711535Abstract: The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.Type: GrantFiled: May 10, 2013Date of Patent: April 29, 2014Assignee: United Microelectronics Corp.Inventors: Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su
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Patent number: 8674403Abstract: A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.Type: GrantFiled: December 4, 2012Date of Patent: March 18, 2014Assignee: MaxPower Semiconductor, Inc.Inventors: Mohamed N. Darwish, Amit Paul
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Publication number: 20140034996Abstract: In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V characteristics are adjusted by including P+ regions to define SCR structures that are operable to sink positive and negative ESD pulses, and adjusting the layout and distances between regions and the number of regions.Type: ApplicationFiled: October 9, 2013Publication date: February 6, 2014Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventor: Vladislav Vashchenko
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Patent number: 8519432Abstract: A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.Type: GrantFiled: March 27, 2008Date of Patent: August 27, 2013Assignee: Analog Devices, Inc.Inventors: Jeffrey G. Barrow, Javier A. Salcedo, A. Paul Brokaw
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Patent number: 8497526Abstract: In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.Type: GrantFiled: October 18, 2010Date of Patent: July 30, 2013Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Antonio Gallerano, Peter J. Hopper
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Patent number: 8476673Abstract: A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.Type: GrantFiled: November 15, 2011Date of Patent: July 2, 2013Assignee: DENSO CORPORATIONInventors: Norihito Tokura, Satoshi Shiraki, Shigeki Takahashi, Shinya Sakurai, Takashi Suzuki
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Patent number: 8330186Abstract: A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.Type: GrantFiled: April 30, 2009Date of Patent: December 11, 2012Assignee: MaxPower Semiconductor, Inc.Inventors: Mohamed N. Darwish, Amit Paul
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Patent number: 8283708Abstract: Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of the one or more diffusion regions being less than about 40% greater than the first width.Type: GrantFiled: September 18, 2009Date of Patent: October 9, 2012Assignee: Micron Technology, Inc.Inventors: Lequn Liu, Yongjun Jeff Hu, Anish A. Khandekar
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Patent number: 8232617Abstract: Flexible lateral p-i-n (“PIN”) diodes, arrays of flexible PIN diodes and imaging devices incorporating arrays of PIN diodes are provided. The flexible lateral PIN diodes are fabricated from thin, flexible layers of single-crystalline semiconductor. A plurality of the PIN diodes can be patterned into a single semiconductor layer to provide a flexible photodetector array that can be formed into a three-dimensional imaging device.Type: GrantFiled: June 4, 2009Date of Patent: July 31, 2012Assignee: Wisconsin Alumni Research FoundationInventors: Zhenqiang Ma, Max G. Lagally, Hao-Chih Yuan
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Publication number: 20120153347Abstract: In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V characteristics are adjusted by including P+ regions to define SCR structures that are operable to sink positive and negative ESD pulses, and adjusting the layout and distances between regions and the number of regions.Type: ApplicationFiled: December 17, 2010Publication date: June 21, 2012Inventor: Vladislav Vashchenko
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Patent number: 8164110Abstract: The present invention relates to integration of lateral high-voltage devices, such as a lateral high-voltage diode (LHVD) or a lateral high-voltage thyristor, with other circuitry on a semiconductor wafer, which may be fabricated using low-voltage foundry technology, such as a low-voltage complementary metal oxide semiconductor (LV-CMOS) process. The other circuitry may include low-voltage devices, such as switching transistors used in logic circuits, computer circuitry, or the like, or other high-voltage devices, such as a microelectromechanical system (MEMS) switch. The reverse breakdown voltage capability of the LHVD may be increased by using an intrinsic material between the anode and the cathode. Similarly, in a lateral high-voltage thyristor, such as a lateral high-voltage Silicon-controlled rectifier (LHV-SCR), the withstand voltage capability of the LHV-SCR may be increased by using an intrinsic material between the anode and the cathode.Type: GrantFiled: November 18, 2010Date of Patent: April 24, 2012Assignee: RF Micro Devices, Inc.Inventors: Daniel Charles Kerr, David C. Dening, Julio Costa
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Patent number: 8134177Abstract: A switching element includes a first electrode having a first surface; a second electrode having a second surface which stands off from the first surface; and a channel region constituted by a plurality of unit channels, each unit channel having opposite ends thereof being in contact with the first electrode and the second electrode, and including fine particles which are aligned in lines in a first direction from the first surface of the first electrode to the second surface of the second electrode, and the unit channels being separated from one another in a second direction across the first direction.Type: GrantFiled: December 5, 2006Date of Patent: March 13, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Kenichi Murooka
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Patent number: 7973333Abstract: A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.Type: GrantFiled: April 2, 2007Date of Patent: July 5, 2011Assignee: Telefunken Semiconductors GmbH & Co. KGInventors: Franz Dietz, Volker Dudek, Thomas Hoffmann, Michael Graf, Stefan Schwantes
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Patent number: 7968940Abstract: Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n? drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.Type: GrantFiled: September 27, 2007Date of Patent: June 28, 2011Assignee: Anpec Electronics CorporationInventor: Florin Udrea
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Patent number: 7943957Abstract: A diode 10 comprises an SOI substrate in which are stacked a semiconductor substrate 20, an insulator film 30, and a semiconductor layer 40. A bottom semiconductor region 60, an intermediate semiconductor region 53, and a surface semiconductor region 54 are formed in the semiconductor layer 40. The bottom semiconductor region 60 includes a high concentration of n-type impurity. The intermediate semiconductor region 53 includes a low concentration of n-type impurity. The surface semiconductor region 54 includes p-type impurity.Type: GrantFiled: November 17, 2006Date of Patent: May 17, 2011Assignee: Toyota Jidosha Kabushiki KaishaInventors: Masato Taki, Masahiro Kawakami, Kiyoharu Hayakawa, Masayasu Ishiko
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Patent number: 7936020Abstract: A two-terminal ESD protection structure formed by an arrangement of five adjacent semiconductor regions (112, 114, 116, 118, and 120) of alternating conductivity type provides protection against both positive and negative ESD voltages. The middle semiconductor region electrically floats. When the two terminals (A and K) of the ESD protection structure are subjected to an ESD voltage, the structure goes into operation by triggering one of its two inherent thyristors (170 and 180) into a snap-back mode that provides a low impedance path through the structure for discharging the ESD current.Type: GrantFiled: August 2, 2007Date of Patent: May 3, 2011Assignee: National Semiconductor CorporationInventors: Albert Z. H. Wang, Chen H. Tsay, Peter Deane
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Patent number: 7915678Abstract: In an NLDMOS, DMOS and NMOS device, the ability is provided for withstanding snapback conditions by providing one or more p+ emitter regions interdigitated between drain regions having drain contacts and electrically connecting the drain contacts to contacts of the emitter regions.Type: GrantFiled: June 17, 2005Date of Patent: March 29, 2011Assignee: National Semiconductor CorporationInventor: Vladislav Vashchenko
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Patent number: 7859009Abstract: The present invention relates to integration of lateral high-voltage devices, such as a lateral high-voltage diode (LHVD) or a lateral high-voltage thyristor, with other circuitry on a semiconductor wafer, which may be fabricated using low-voltage foundry technology, such as a low-voltage complementary metal oxide semiconductor (LV-CMOS) process. The other circuitry may include low-voltage devices, such as switching transistors used in logic circuits, computer circuitry, or the like, or other high-voltage devices, such as a microelectromechanical system (MEMS) switch. The reverse breakdown voltage capability of the LHVD may be increased by using an intrinsic material between the anode and the cathode. Similarly, in a lateral high-voltage thyristor, such as a lateral high-voltage Silicon-controlled rectifier (LHV-SCR), the withstand voltage capability of the LHV-SCR may be increased by using an intrinsic material between the anode and the cathode.Type: GrantFiled: June 17, 2008Date of Patent: December 28, 2010Assignee: RF Micro Devices, Inc.Inventors: Daniel Charles Kerr, David C. Dening, Julio Costa
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Patent number: 7843032Abstract: Apparatus, systems, and methods may include managing electrostatic discharge events in radio frequency identification (RFID) devices by using a semiconductor circuit having a non-aligned gate to implement a snap-back voltage protection mechanism. Such circuits may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit including an RFID circuit that is supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: December 27, 2007Date of Patent: November 30, 2010Assignee: Synopsis, Inc.Inventors: Cong Khieu, Yanjun Ma, Jaideep Mavoori
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Patent number: 7667241Abstract: An electrostatic discharge protection device for protecting a node includes a transistor, a silicon controlled rectifier, a second contact region laterally displaced from the first contact region, and a collection region adjacent the source region. The transistor includes a semiconductor substrate, a source region, a channel region adjacent the source region, a gate over the channel region, and a drain region laterally displaced from the channel. The silicon controlled rectifier includes the source region, a portion of the substrate, a doped well, and a first contact region in the well, laterally displaced from the drain region. The collection region, the source region and the gate, are metallically connected. The node, the first contact region, and the second contact region, are metallically connected, and the drain region is not metallically connected to the node.Type: GrantFiled: September 25, 2007Date of Patent: February 23, 2010Assignee: Cypress Semiconductor CorporationInventors: Andrew Walker, Helmut Puchner
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Patent number: 7538362Abstract: The invention relates to a lateral semiconductor diode, in which contact metal fillings (6, 7), which run in trenches (3, 4) in particular in a silicon carbide body (1, 2), are interdigitated at a distance from one another, and a rectifying Schottky or pn junction (18) is provided.Type: GrantFiled: August 29, 2005Date of Patent: May 26, 2009Assignee: Infineon Technologies AGInventors: Gabriel Konrad Dehlinger, Michael Treu
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Patent number: 7465964Abstract: A high voltage/power semiconductor device has a substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer. Low and high voltage terminals are connected to the semiconductor layer. The device has a control terminal. The semiconductor layer includes a drift region and a relatively highly doped injector region between the drift region and the high voltage terminal. The device has a relatively highly doped region in electrical contact with the highly doped injector region and the high voltage terminal and forming a semiconductor junction with the substrate. The combination of the insulating layer and the relatively highly doped region of the first conductivity type effectively isolate the highly doped injector region from the substrate.Type: GrantFiled: December 30, 2005Date of Patent: December 16, 2008Assignee: Cambridge Semiconductor LimitedInventor: Florin Udrea
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Patent number: 7414273Abstract: A two-dimensional silicon controlled rectifier (2DSCR) having the anode and cathode forming a checkerboard pattern. Such a pattern maximizes the anode to cathode contact length (the active area) within a given SCR area, i.e., effectively increasing the SCR width. Increasing the physical SCR area, increases the current handling capabilities of the SCR.Type: GrantFiled: July 7, 2005Date of Patent: August 19, 2008Assignees: Sarnoff Corporation, Sarnoff EuropeInventors: Russell Mohn, Cong-Son Trinh, Phillip Czeslaw Jozwiak, John Armer, Markus Paul Josef Mergens
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Patent number: 7387908Abstract: A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region of a CMOS imager photodiode are disclosed. The channel impurity gradient in the transfer gate provides a complete charge transfer between the charge collection region of the photodiode and a floating diffusion node. The dopant gradient region is formed by doping a region at one end of the channel with a low enhancement dopant and another region at the other end of the channel with a high enhancement dopant.Type: GrantFiled: March 30, 2005Date of Patent: June 17, 2008Assignee: Micron Technology, Inc.Inventor: Inna Patrick
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Patent number: 7365372Abstract: The present invention is to provide a semiconductor device including: a semiconductor layer that has a first-conductivity-type region, a second-conductivity-type region, a first-conductivity-type region, and a second-conductivity-type region that are adjacent to each other in that order; first and second electrodes that are connected to the first-conductivity-type region and the second-conductivity-type region, respectively, at both ends of the semiconductor layer; and a gate electrode that is coupled to the second-conductivity-type region or the first-conductivity-type region in an intermediate area of the semiconductor layer, the gate electrode being provided over a plurality of faces of a semiconductor layer portion serving as the second-conductivity-type region or the first-conductivity-type region in the intermediate area.Type: GrantFiled: July 10, 2006Date of Patent: April 29, 2008Assignee: Sony CorporationInventor: Taro Sugizaki
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Patent number: 7342282Abstract: A semiconductor device and method for electrostatic discharge protection. The semiconductor device includes a first semiconductor controlled rectifier and a second semiconductor controlled rectifier. The first semiconductor controlled rectifier includes a first semiconductor region and a second semiconductor region, and the second semiconductor controlled rectifier includes the first semiconductor region and the second semiconductor region. The first semiconductor region is associated with a first doping type, and the second semiconductor region is associated with a second doping type different from the first doping type. The second semiconductor region is located directly on an insulating layer.Type: GrantFiled: September 10, 2004Date of Patent: March 11, 2008Assignee: Altera CorporationInventors: Hugh Sungki O, Chih-Ching Shih, Cheng-Hsiung Huang, Yow-Juang Liu
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Patent number: 7288450Abstract: In an integrated circuit, a diode is interposed between the semiconductor substrate and the contact pad to an external bias voltage, and the substrate is biased at an internal voltage reference. Between each contact pad of the integrated circuit and semiconductor substrate, there is positioned a protection device against permanent overloads and a protection device against electrostatic discharges. By isolating the semiconductor substrate from the external voltages source and by placing a protection device between each contact pad and the substrate, a broad, general protection of the integrated circuit is obtained against all the destructive phenomena such as overloads, positive and negative overvoltages, polarity reversal and electrostatic discharges.Type: GrantFiled: November 30, 1999Date of Patent: October 30, 2007Assignee: STMicroelectronics S.A.Inventor: Francois Tailliet
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Patent number: 7285824Abstract: A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type provided on the semiconductor layer, the first semiconductor region being one of an anode region and a cathode region; a second semiconductor region of the first conductivity type provided on the first semiconductor region, the second semiconductor region being the other of the anode region and the cathode region; and a semiconductor buried region of the second conductivity type provided between the semiconductor layer and the first semiconductor region. The semiconductor buried region has an aperture where the first semiconductor region is in contact with the semiconductor layer.Type: GrantFiled: July 15, 2005Date of Patent: October 23, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Yasuto Sumi, Koichi Endo
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Patent number: 7262443Abstract: Method and apparatus for forming a semiconductor device. The method includes defining a plurality of rows in a semiconductor layer. Thereafter, on one or more of the plurality of rows, one or more bipolar junction devices are formed. Each of the bipolar junction devices has a first end region and a second end region. A quantity of a pre-amorphization ion is then implanted into at least one of the first end region and the second end region of a bipolar junction device for example. A silicide is formed in the semiconductor layer at the first end region and the second end region having implanted therein the quantity of the pre-amorphization ion. Additionally, laterally extending upper edges of the plurality of rows forming corners may be rounded prior to the implantation of the pre-amorphization.Type: GrantFiled: December 29, 2004Date of Patent: August 28, 2007Assignee: T-Ram Semiconductor Inc.Inventor: Kevin J. Yang
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Patent number: 7205629Abstract: A voltage booster transistor with an optimal conducting path formed in widebandgap semiconductors like Silicon Carbide and Diamond, is provided as a power transistor with a voltage rating >200V. Contrary to conventional vertical design of power transistors, a higher, optimum doping for a given thickness supports higher Source/Drain blocking voltage. A topside and backside gate region of the opposite conductivity type than the channel region providing control of source to drain current path through a small gate voltage. The backside gate and the Drain junction are able to support the rated blocking voltage of the device.Type: GrantFiled: June 3, 2004Date of Patent: April 17, 2007Assignee: WidebandGap LLCInventor: Ranbir Singh
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Patent number: 7196361Abstract: In a high voltage ESD protection solution, a plurality of DIACs are connected together to define a cascaded structure with isolation regions provided to prevent n-well and p-well punch through. An p-ring surrounds the DIACs and provides a ground for the substrate in which the DIACs are formed.Type: GrantFiled: December 12, 2003Date of Patent: March 27, 2007Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Willem Kindt, Peter J. Hopper
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Patent number: 7145185Abstract: The invention concerns a voltage-controlled triac-type component, formed in a N-type substrate (1) comprising first and second vertical thyristors (Th1, Th2), a first electrode (A2) of the first thyristor, on the front side of the component, corresponding to a first N-type region (6) formed in a first P-type box (5), the first box corresponding to a first electrode (A2) of the second thyristor, the first box containing a second N-type region (8); and a pilot structure comprising, above an extension of a second electrode region (4) of the second thyristor, a second P-type box (11) containing third and fourth N-type regions, the third region (12) and a portion of the second box (11) being connected to a gate terminal (G), the fourth region (13) being connected to the second region (8).Type: GrantFiled: December 27, 2002Date of Patent: December 5, 2006Assignee: STMicroelectronics S.A.Inventor: Jean-Michel Simmonet
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Patent number: 7050125Abstract: A method of manufacturing an active matrix substrate comprises forming a plurality of elements on an element formation substrate, forming wirings on a final substrate, transferring some elements selected from the elements, and selectively connecting some elements to the wirings on the final substrate. According to this method, it is possible to manufacture an active matrix substrate providing a high definition image on a large substrate or a non-glass substrate, at a low cost.Type: GrantFiled: April 29, 2004Date of Patent: May 23, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Masahiko Akiyama
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Patent number: 6963087Abstract: The invention concerns a pulsed bistable bidirectional electronic switch comprising a monolithic semiconductor circuit formed from a substrate (1) whereof the rear surface (A2) is coated with a metallization connected to earth. Said circuit comprises a vertical bidirectional switch (T1, T2) provided with a first gate terminal (M3), whereof the main electrode (A1) on the side of the front surface is connected to a load and an alternating current supply; a horizontal thyristor (T3) comprising an upper layer (4) of the vertical bidirectional switch, a first P-type region (11), and a second N-type region (12) formed in the first region; a second gate terminal (G1) connected to one of the first and second regions, the other being connected to earth. A capacitor (C) is connected to the first gate terminal (G3) and to the alternating current supply (VAC).Type: GrantFiled: December 28, 2001Date of Patent: November 8, 2005Assignee: STMicroelectronics S.A.Inventors: Sophie Gimonet, Franck Duclos
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Patent number: 6924531Abstract: A method of forming a LDMOS semiconductor device and structure for same. A preferred embodiment comprises forming a first guard ring around and proximate the drain of a LDMOS device, and forming a second guard ring around the first guard ring. The first guard ring comprises a P+ base guard ring, and the second guard ring comprises an N+ collector guard ring formed in a deep N-well, in one embodiment. The first guard ring and second guard ring prevent leakage current from flowing from the drain of the LDMOS device to the substrate.Type: GrantFiled: October 1, 2003Date of Patent: August 2, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Hsin Chen, Ruey-Hsin Liu
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Patent number: 6911679Abstract: In an ESD protection device making use of a LVTSCR, at least one contacted drain and at least one emitter are formed, and are arranged laterally next to each other to be substantially equidistant from the gate of the LVTSCR, to improve holding voltage and decrease size. The ratio of emitter width to contacted drain width is adjusted to achieve the desired characteristics.Type: GrantFiled: January 9, 2003Date of Patent: June 28, 2005Assignee: National Semiconductor Corp.Inventors: Vladislav Vashchenko, Ann Concannon, Marcel ter Beek, Peter J. Hopper