Abstract: The invention makes it possible to form thyristers and SCRs that show a good discharge efficiency upon application of static electricity in semiconductor devices using a SOI substrate. A semiconductor device is equipped with a connection terminal for connection with an external element, a dielectric substrate having a semiconductor layer formed therein, a first region of a first conductive type that is formed in the semiconductor layer and electrically connected to the connection terminal, a second region of a second conductive type that is formed in the semiconductor layer and electrically connected to the first region, a third region of the first conductive type that is formed adjacent to the second region in the semiconductor layer, and a fourth region of the second conductive type that is formed adjacent to the third region in the semiconductor layer.

Abstract: A pnpn thyristor element Thy1 and six pn diode elements D1, D2, D3, D4, D5, and D6 are formed in a semiconductor substrate of a first conductivity type, and separated into six regions by a diffusion layer of a second conductivity type which also functions as the anode of the thyristor element Thy1. A double isolation diffusion layer is disposed between the region of the thyristor element Thy1 and three pn diode elements D1 ·D2 and D6, and the region of the three remaining pn diodes D3, D4, and D5. Surface connection is performed to provide a balance type surge protection circuit.

Abstract: A bi-directional silicon controlled rectifier formed in a silicon layer and disposed over shallow trench isolations and therefore electrically isolated from the substrate to be insensitive to substrate noise for electrostatic discharge protection an electrostatic discharge protection device that includes a semiconductor substrate, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first p-type portion and the first n-type portion, a second n-type portion, a third p-type portion, a third n-type portion contiguous with the third p-type portion, and a fourth p-type portion contiguous with the third p-type portion and the third n-type portion, wherein at least one of the first p-type portion, second p-type portion, third p-type portion, fourth p-type portion, first n-type portion, second n-type portion, and third n-type portion overlaps the isolation structure.

Abstract: In order to provide a reliable surge protective component with a straightforward manufacturing process, first and second buried layers are diffused over the entire inside surfaces of a semiconductor substrate, and first and second base layers are then diffused over the entire inside surfaces of the first and second buried layers. First and second emitter layers are then partially diffused at the inside of the first and second base layers. The peripheries of the first and second emitter layers are then surrounded by first and second moats, the bottoms of which reach the first and second buried layers. A PN junction formed between the first and second base layers and first and second buried layers is then simply a planar junction.

Abstract: The present invention provides a novel ESD structure for protecting an integrated circuit (IC) from ESD damage and a method of fabricating the ESD structure on a semiconductor substrate. The ESD structure of the present invention has lower trigger voltage and lower capacitance, and takes smaller substrate area than prior art ESD structures. The low trigger voltage is provided by a small N+P diode or a P+N diode which has a PN junction with a much lower breakdown voltage than a PN junction between a N+ (or P+) source/drain region and a P-well (or N-well). All of the diffusion regions in the ESD device of the present invention can be formed using ordinary process steps for fabricating the MOS devices in the IC and does not require extra masking steps in addition to those required to fabricate the IC.

Abstract: It is an object to provide a lateral transistor which enables a current gain rate to change less, even if it is used over a long time.

Abstract: A high-voltage component and a method for its manufacture. The component functions to switch currents at high voltages. The component is composed of partial components that are connected in series and are laterally supported on a self-supporting semiconductor wafer. The partial components switch through, for example, at a given voltage applied between a first bridge cathode and an anodic metallization.

Abstract: The holding voltage (the minimum voltage required for operation) of a triac is increased to a value that is greater than a dc bias on to-be-protected nodes. The holding voltage is increased by inserting a voltage drop between each p+ region and a to-be-protected node. As a result, the triac can be utilized to provide ESD protection to power supply pins.

Abstract: The invention provides a PIN diode having a laterally extended I-region. The invention also provides a method of fabricating the inventive PIN diode compatible with modem RF technologies such as silicon-germanium BiCMOS processes.

Abstract: The present invention relates to a triac network wherein each triac includes an N-type semiconductor substrate, containing a first thyristor comprised of NPNP regions and a second thyristor comprised of PNPN regions, and surrounded with a P-type deep diffusion. A P-type well contains an N-type region, on the front surface side. A first metallization corresponds to a first main electrode, a second metallization corresponds to a second main electrode, a third metallization covers the N-type region and is connected to a gate terminal, and a fourth metallization connects the P-type well to the upper surface of the deep diffusion.

Abstract: Silicon carbide power devices include a semiconductor substrate of first conductivity type (e.g., N-type) having a face thereon and a blocking voltage supporting region of first conductivity type therein extending to the face. The voltage supporting region is designed to have a much lower majority carrier conductivity than an underlying and highly conductive "bypass" portion of the semiconductor substrate. This bypass portion of the substrate supports large lateral currents with low on-state voltage drop. First and second semiconductor devices are also provided having respective first and second active regions of first conductivity type therein. These first and second active regions extend on opposing sides of the voltage supporting region and are electrically coupled to the bypass portion of the semiconductor substrate which underlies and extends opposite the voltage supporting region relative to the face of the substrate.

Abstract: A monolithic component including, in an N-type lightly-doped substrate of a semiconductor wafer, two portions separated by a P-type insulating wall. A first portion of the two portions includes a high voltage lateral component, a layer of which substantially corresponds to the thickness of the wafer. The second portion includes logic circuit components. A rear surface of the substrate includes a P-type layer coated with a metallization. The insulating wall is in electrical contact with a low voltage terminal of the high voltage lateral component, such as the gate region of a thyristor. The logic portion includes at least one vertical component.

Abstract: A field relaxation region of the second conductivity type is formed between the base region and a drain electrode contact portion at which the drain region contacts with a drain electrode but distanced from both the base region and the drain electrode contact portion and the field relaxation region is also separated via the drain region from the laterally extending portion of the semiconductor isolation region to form a drain current channel region between the field relaxation region and the laterally extending portion of the semiconductor isolation region and further the field relaxation region is electrically connected via an interconnection to the source region and the vertically extending portion of the semiconductor isolation region so that the field relaxation region and the semiconductor isolation region have the same potential as the source region whereby if the lateral MOS field effect transistor is reverse-biased by a voltage, then a first space charge region is formed which extend from a first p-n

Abstract: A bidirectional lateral insulated gate bipolar transistor (IGBT) includes two gate electrodes. The IGBT can conduct current in two directions. The IGBT relies on a RESURF operation to provide high voltage blocking in both directions. The IGBT is symmetrical, having N-type drift region in contact with an oxide layer. A P-type region is provided above the N-type-drift region, having a portion more heavily doped with P-type dopants. The RESURF operation can be provided by a buried oxide layer or by a P substrate or by a horizontal PN junction. The IGBT can be utilized in various power operations, including a matrix switch or a voltage source converter.

Abstract: A voltage-controlled power monolithic bidirectional switch has two main terminals and includes a control electrode whose voltage is referenced to one of the main terminals. The switch includes a lateral P-channel MOS transistor; a vertical N-channel MOS transistor, the source well of the vertical N-channel MOS transistor also constituting the source of the lateral transistor; a lateral thyristor whose first three regions correspond to the source, drain and channel of the lateral MOS transistor; a first vertical thyristor disposed in parallel with the lateral thyristor; and a second vertical thyristor having a polarity opposite to the first polarity and disposed in parallel with the vertical MOS transistor.

Abstract: A semiconductor device includes an emitter region, a collector region provided directly under the emitter region, and a two-region base structure. The first base region is interposed between the emitter and collector regions, and the second base region supports the collector region. The aforementioned regions have a progressively higher impurity concentrations, with the collector region having an impurity concentration higher than that of the first base region, the second base region having an impurity concentration higher than that of the collector region, and the emitter region having an impurity concentration higher than that of the base region. Also included is a resistance region formed, in one embodiment, from a projecting end portion of one of the base layers. The projecting end portion of the base is fabricated so that both base portions contact one another in the resistance region, and consequently both base portions are of the same potential.

Abstract: A field-effect-controlled semiconductor device has a cathode, an anode, and a gate, and extends laterally on a first insulating layer covering a substrate. The device includes a main thyristor, a MOSFET switch and a diode which connects a highly doped region embedded in a first part of a second base region of the thyristor to the cathode of the device.

Abstract: A semiconductor controlled rectifier is disclosed herein. In a preferred embodiment, a first n-doped region 112 is formed in a p-doped semiconductor layer 126. A first n-well region 122 is formed within the first doped region 112. This well 122 extends through the region 112 and into the layer 126. A second n-doped region 114 is also formed in the layer 126. The second region 1114 is spaced from the first region 112. A second n-well 142 is formed in the layer 126 such that it partially overlaps the second region 114. A n-doped region 144 and a p-doped region 146 are each formed in the second n-well 142 and abut one another.

Abstract: The high-voltage semiconductor device includes a single chip having a plurality of semiconductor elements connected in series with each other which includes an insulating substrate (2); a monocrystalline semiconductor carrier (1) of a first conductivity type applied to the insulating substrate (2); at least two terminals (5,6) located on opposite sides of the chip; strip-like areas (3) of a second conductivity type formed in the monocrystalline semiconductor carrier (1), the strip-like areas (3) each extending across the semiconductor carrier (1) at right angles to a longitudinal direction between the at least two terminals, forming pn junctions in the semiconductor carrier (1), being spaced from each other in the longitudinal direction over the single chip and penetrating an entire thickness of the semiconductor carrier; at least one doped region (7) in the strip-like areas (3) forming an at least four layered component in the single chip; and a light responsive device for reducing a switching voltage of the

Abstract: An optically triggered silicon controlled rectifier (SCR) circuit (20) has a number of semiconductor layers diffused into an N- substrate (21). The layers form an SCR (50) having a P+ anode region (25), a P+ gate region (24), and an N+ cathode region (27). An adjustable base-shunt resistance, in the form of a P- channel depletion mode MOSFET (Q3), connects between the SCR gate region and the cathode region. The MOSFET includes a MOSFET gate region (35), a P+ drain region (24), a P-- channel (26), and a P+ source region (23). The substrate also accommodates a PN photodiode (22, D1) which connects to the MOSFET gate region for switching the MOSFET on and off in response to incident optical radiation (L) thereon. The SCR gate region also comprises photosensitive material. When sufficient optical radiation illuminates the photodiode and the SCR gate region, the MOSFET is turned off and the SCR is triggered, permitting anode-to-cathode current to flow.

Abstract: Disclosed is a semiconductor device comprising an output Triode AC switch with a vertical structure, which is provided in a silicon substrate and has a gate, a first output terminal and a second output terminal, and an input/driving photo Triode AC switch, which is provided in the substrate and has a light-receiving portion, a first terminal connected to the gate and a second terminal connected to the second output terminal. The output Triode AC switch with a vertical structure is turned on when light is input to the photo Triode AC switch.

Abstract: A GTO thyristor includes a p-type emitter layer, an n-type base layer, a p-type base layer and an n-type emitter layer. An additional n-type layer is formed on the p-type base layer next to the n-type emitter layer An additional p.sup.+ -type layer is formed on the additional n-type layer and stretches to the n-type emitter layer. An anode electrode and a cathode electrode are disposed respectively on the n-type emitter layer and the p-type base layer. The n-type emitter layer and the additional p.sup.+ -type layer are connected with each other by a floating electrode. A first gate electrode is disposed on the additional p.sup.+ -type layer, additional n-type layer and p-type base layer with an insulating film interposed therebetween so as to form a first FET. A second gate electrode is disposed on the n-type base layer, p-type base layer and n-type emitter layer with an insulating film interposed therebetween so as to form a second FET.

Abstract: A switching device includes a thyristor and a MOSFET, and a voltage clamp circuit. The voltage clamp circuit includes an N.sup.+ type contact region formed in a surface layer of a N type substrate and electrically connected to a gate electrode of a MOSFET, and a P type guard ring surrounding the contact region.