Abstract: An improved transient voltage suppression device includes a semiconductor substrate, a transient voltage suppressor, at least one first diode, at least one conductive pad, and at least one second diode. The transient voltage suppressor has an N-type heavily-doped clamping area. The first anode of the first diode is electrically connected to the N-type heavily-doped clamping area. The conductive pad is electrically connected to the first cathode of the first diode. The second anode of the second diode is electrically connected to the conductive pad and the second cathode of the second diode is electrically connected to the transient voltage suppressor. The first anode is closer to the N-type heavily-doped clamping area rather than the conductive pad. The conductive pad is closer to the N-type heavily-doped clamping area rather than the second anode.

Abstract: Disclosed herein are systems and methods for reducing intermodulation distortion (IMD) in switches using parallel distorter circuits. A switch circuit can include having a switch arm and a distorter arm that is configured to act as a compensation circuit to compensate for non-linearities in the switch arm. The switch circuit can include a plurality of FETs in the switch arm configured to provide switching functionality. The distorter arm is configured to compensate for a non-linearity effect generated by the FETs of the switch arm when it is in an ON state. The distorter arm is configured to compensate for the non-linearity effect generated by the switch arm independent of the frequency of the signal received by the switch arm. Various configurations of switch arms and distorter arms can be implemented to reduce harmonic distortion as well as intermodulation distortion.

Abstract: A display panel includes a TFT substrate, which includes a substrate, a plurality of scan lines, a plurality of data lines, and a first intermediate layer. The scan lines are disposed on the substrate along a first direction, and the scan lines are intersected with the data lines to define a plurality of sub-pixel units. The sub-pixel units include a first sub-pixel unit and a second sub-pixel unit. The first sub-pixel unit has a first light transmission area and a first component installation area, and the second sub-pixel unit has a second light transmission area and a second component installation area. The first intermediate layer is disposed on the substrate and has an opening. The opening is at least partially overlapped with the first light transmission area, and is at least partially overlapped with the second light transmission area.

Abstract: Methods of facilitating fabrication of circuit structures are provided which include, for instance: providing a structure with a film layer; modifying an etch property of the film layer by implanting at least one species of element or molecule into the upper portion of the film layer, the etch property of the film layer remaining unmodified beneath the upper portion; and subjecting the structure and film layer with the modified etch property to an etching process, the modified etch property of the film layer facilitating the etching process. Modifying the etch property of the upper portion of the film layer may include making the upper portion of the film layer preferentially susceptible or preferentially resistant to the etching process depending on the circuit fabrication approach being facilitated.

Abstract: The present disclosure relates to radio frequency (RF) microelectromechanical system (MEMS) device packaging, and specifically to reducing harmonic distortion caused by such packaging. In one embodiment, a die is provided that employs a gold-doped silicon substrate, wherein at least one RF MEMS device is disposed on the gold-doped silicon substrate. By employing the gold-doped silicon substrate, the packaging can achieve an exceptionally high resistivity without any additional expensive components, wherein the high resistivity has an associated low carrier lifetime. Notably, the low carrier lifetime corresponds to reduced harmonic distortion generated by the gold-doped silicon substrate, even when operating at high power. Thus, the gold-doped silicon substrate provides a less expensive packaging in which to place RF MEMS devices, wherein the packaging is capable of operating at high power with reduced harmonic distortion.

Abstract: Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

Abstract: For simplification of a structure and a manufacturing process of an element, and reduction of manufacturing cost, the present disclosure provides a light-receiving device including: a photoelectric conversion element; and an active element, wherein the active element includes at least one of a reset element configured to reset the photoelectric conversion element, an amplifier element configured to amplify a detection signal based on the photoelectric conversion element, or a selection element configured to selectively output the detection signal based on the photoelectric conversion element, and the photoelectric conversion element and at least part of the active element are formed by using an identical organic semiconductor material or an identical high molecular functional material.

Abstract: A thin-film transistor (TFT) substrate includes a semiconductor pattern, a conductive pattern, a first wiring pattern, an insulation pattern and a second wiring pattern. The semiconductor pattern is formed on a substrate. The conductive pattern is formed as a layer identical to the semiconductor pattern on the substrate. The first wiring pattern is formed on the semiconductor pattern. The first wiring pattern includes a source electrode and a drain electrode spaced apart from the source electrode. The insulation pattern is formed on the substrate having the first wiring pattern to cover the first wiring pattern. The second wiring pattern is formed on the insulation pattern. The second wiring pattern includes a gate electrode formed on the source and drain electrodes. Therefore, a TFT substrate is manufactured using two or three masks, so that manufacturing costs may be decreased.

Abstract: According to an embodiment of the disclosed technology, a manufacture method of an organic thin film transistor array substrate is provided. The method comprises: forming a first pixel electrode, a source electrode, a drain electrode and a data line in a first patterning process; forming an organic semiconductor island and a gate insulating island in a second patterning process; forming a data pad region in a third patterning process; and forming a second pixel electrode, a gate electrode and a gate line in a fourth patterning process.

Abstract: The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.

Abstract: Use of a forward biased diode to reduce leakage current of transistors implemented on silicon on insulator (SOI) is a particular challenge due to the difficulty of achieving effective contact with the region beneath the gate of the transistor. An improved implementation in SOI gate fingers that reach under the source through tunnels that are contacted with a region outside the transistor. A further embodiment uses drain extension implants to provide good channel connection.

Abstract: A method for fabricating an image sensor is described. A substrate is provided. Multiple photoresist patterns are formed over the substrate, and then a thermal reflow step is performed to convert the photoresist patterns into multiple microlenses arranged in an array. The focal length of the microlens increases from the center of the array toward the edge of the array.

Abstract: An E-ink display and method for repairing the same is provided. The method is for repairing a thin film transistor array substrate of the E-ink display. The thin film transistor array substrate having a plurality of pixel units is provided initially. Each of the pixel unit includes a thin film transistor and a pixel electrode. The thin film transistor has a gate electrode, a source electrode and a drain electrode. The gate electrode, the source electrode and the drain electrode are connected electrically to a scan line, a data line and the pixel electrode respectively. A portion of the pixel electrode is located above the data line. Next, a repairing portion is formed at the space between the data line and the pixel electrode. The repairing portion is utilized to electrically connect the pixel electrode and the data line.

Abstract: A gate turn-off thyristor (GTO) device has a lower portion, an upper portion and a lid. The lower portion has a lower base region of a first conductivity type, and a lower emitter region of a second conductivity type disposed at or from a lower surface of the lower base region. A lower junction is formed between the lower base region and the lower emitter region. The upper portion has an upper base region of the second conductivity type, and upper emitter regions of the first conductivity type disposed at or from an upper surface of the upper base region. An upper-lower junction is formed between the lower base region and the upper base region, and upper junctions are formed between the upper base region and the upper emitter regions. The upper base region and upper emitter regions form an upper base surface with first conductive contacts to the upper base region alternating with second conductive contacts to the upper emitter regions. The lid has a layer of insulator with upper and lower surfaces.

Abstract: A thin film transistor array substrate and the manufacturing method thereof are disclosed herein. A first patterned metal layer, an insulating layer, a patterned layer, and a second patterned metal layer are sequentially formed on a substrate. Then, a number of scan lines and a number of source lines are disposed on the substrate and define a number of pixel regions. A number of the storage capacitance lines are disposed on the substrate in a direction extending along the scan lines and across the pixel regions, wherein each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion. A number of patterned thin films are disposed on the storage capacitance lines and above the cross portion.

Abstract: A vertical-type semiconductor device for controlling a current flowing between electrodes opposed against each other across a semiconductor substrate, including: a semiconductor substrate having first and second surfaces opposed against each other; a first electrode formed in the first surface; a second electrode formed in the second surface through a high-resistance electrode whose resistance is Rs; and a third electrode formed along at least a part of the outer periphery of the second surface, wherein a potential difference Vs between the second and third electrodes is measured with a current I flowing between the first and second electrodes, and the current I is detected from the resistance Rs and the potential difference Vs.

Abstract: A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.

Abstract: There is a demand of a solid-state imaging device capable of being driven at a high speed and in which the shading of sensitivity and illuminance defect can be prevented from being caused. A solid-state imaging device (20) comprises a light-receiving sensor section disposed on the surface layer portion of a substrate (21) for performing a photoelectric conversion, a charge transfer section for transferring a signal charge read out from the light-receiving sensor section, a transfer electrode (27) (28) made of polysilicon formed on a substrate (21) at its position approximately above the charge transfer section through an insulating film (26), and an interconnection made of polysilicon and interconnected to the transfer electrode (27) (28). At least one of the polysilicon transfer electrode (27)(28) and the interconnection is formed on a polysilicon layer (27a) (28a) by selectively depositing a high-melting point metal having a resistance value lower than that of polysilicon.

Abstract: A method of manufacturing a thin film transistor (TFT) substrate to minimize a rugged surface of an organic layer overlapping with a storage electrode is provided. The method includes forming a passivation layer on a substrate having a storage electrode and an organic layer covering the passivation layer, forming a concave portion by partially removing a portion of the organic layer that overlaps with the storage electrode, planarizing a rugged pattern located on the bottom of the concave portion, and forming an opening extending to a surface of the passivation layer by removing the planarized organic layer from the concave portion.

Abstract: A semiconductor film is formed on a substrate. Subsequently, a resist film is formed on the semiconductor film, and dry etching is performed to the semiconductor film using the resist film as a mask. Due to the dry etching, the edge portion of the semiconductor film protrudes from the resist film. Next, the p-type impurities are introduced into the edge portion of the semiconductor film using the resist film as a mask. The volume density of the p-type impurities in a channel edge portion of the semiconductor film is two to five times the volume density of the p-type impurities in a channel center section. Subsequently, the resist film is removed to form a gate insulating film and a gate electrode.

Abstract: An E-ink display and method for repairing the same is provided. The method is for repairing a thin film transistor array substrate of the E-ink display. The thin film transistor array substrate having a plurality of pixel units is provided initially. Each of the pixel unit includes a thin film transistor and a pixel electrode. The thin film transistor has a gate electrode, a source electrode and a drain electrode. The gate electrode, the source electrode and the drain electrode are connected electrically to a scan line, a data line and the pixel electrode respectively. A portion of the pixel electrode is located above the scan line. Next, a repairing portion is formed at the space between the scan line and the pixel electrode. The repairing portion is utilized to electrically connect the pixel electrode and the scan line.

Abstract: The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 ?.

Abstract: A semiconductor device includes a thyristor body having at least one region in a substrate. According to an example embodiment of the present invention, a trench is in a substrate and adjacent to a thyristor body region in the substrate. The trench is lined with an insulative material and further includes conductive material that is insulated from the thyristor body region in the substrate by the liner material. A conductive thyristor control port is located in the trench and adapted for capacitively coupling to the thyristor body region in the substrate and to control current in the thyristor body by causing an outflow of minority carriers in the thyristor. With this approach, conductive material can be used to fill a portion of the trench while using the trench portion including the conductive material to electrically isolate a portion of the thyristor body in the substrate.

Abstract: A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad.

Abstract: An IGBT with monolithic integrated antiparallel diode has one or more emitter short regions forming the diode cathode in the region of the high-voltage edge. The p-type emitter regions of the IGBT have no emitter shorts. The counterelectrode of the diode exclusively comprises p-type semiconductor wells on the front side of the device. Particularly in applications, such as lamp ballast, in which the diode of the IGBT is firstly forward-biased, hard commutation is not effected and the current reversal takes place relatively slowly. The emitter short regions may be strips or points below the high-voltage edge. The horizontal bulk resistance is increased and the snapback effect is reduced without reducing the robustness in the edge region. In a second embodiment, the IGBT is produced using thin wafer technology and the thickness of the substrate defining the inner zone is less than 200 ?m. The thickness of the emitter region or of the emitter regions and short region(s) is less than 1 ?m.

Abstract: There is a demand of a solid-state imaging device capable of being driven at a high speed and in which the shading of sensitivity and illuminance defect can be prevented from being caused. A solid-state imaging device (20) includes a light-receiving sensor section disposed on the surface layer portion of a substrate (21) that performs a photoelectric conversion, a charge transfer section that transfers a signal charge read out from the light-receiving sensor section, a transfer electrode (27) (28) made of polysilicon formed on a substrate (21) at a position approximately above the charge transfer section through an insulating film (26), and an interconnection made of polysilicon and interconnected to the transfer electrode (27) (28). At least one of the polysilicon transfer electrode (27)(28) and the interconnection is formed on a polysilicon layer (27a) (28a) by selectively depositing a high-melting point metal having a resistance value lower than that of polysilicon.

Abstract: A switching semiconductor device includes a first compound layer formed on a single crystal substrate which includes silicon carbide or sapphire, and including a general formula InxGa1-xN, where 0?x?1; a second compound layer formed on the first compound layer, and including a general formula InyALzGa1-y-zN, where 0?y?1 and 0<z?1; and a gate electrode formed on the second compound layer. The gate electrode is electrically connected to a resistance element formed on a first interlayer insulating film that covers the gate electrode, through a metal wiring formed on a second interlayer insulating film that covers the first interlayer insulating film.

Abstract: A semiconductor device includes a thyristor body having at least one region in a substrate. According to an example embodiment of the present invention, a trench is in a substrate and adjacent to a thyristor body region in the substrate. The trench is lined with an insulative material and further includes conductive material that is insulated from the thyristor body region in the substrate by the liner material. A conductive thyristor control port is located in the trench and adapted for capacitively coupling to the thyristor body region in the substrate and to control current in the thyristor body by causing an outflow of minority carriers in the thyristor. With this approach, conductive material can be used to fill a portion of the trench while using the trench portion including the conductive material to electrically isolate a portion of the thyristor body in the substrate.

Abstract: A method of fabricating a thin film transistor array is provided. A first patterned conductive layer that distributes over an area range exceeding the designated display region is formed over a substrate. A first dielectric layer is formed over the substrate, wherein the first dielectric layer has the thickness getting smaller toward the edge, so that the first patterned conductive layer outside the designated display region is exposed. A second patterned conductive layer is formed over the first dielectric layer. The second patterned conductive layer and the exposed first patterned conductive layer are electrically connected. A second dielectric layer having a plurality of contact openings therein is formed over the substrate. A plurality of pixel electrodes is formed over the second dielectric layer such that the pixel electrode and the second patterned conductive layer are electrically connected through the contact openings. Finally, various layers outside the designated display regions are removed.

Abstract: A current-amplifying logarithmic mode CMOS image sensor having a first MOS transistor, a second MOS transistor, a third MOS transistor and a sensing device. The gate terminal and the first connection terminal of the first MOS transistor are tied to a high voltage terminal. The gate terminal of the second MOS transistor and the second connection terminal of the first MOS transistor are tied to a node point. The first connection terminal of the second MOS transistor is tied to the high voltage terminal. The gate terminal of the third MOS transistor is tied to a row select signal. The first connection terminal of the third MOS transistor is tied to the second connection terminal of the second MOS transistor. The second terminal of the third MOS transistor serves as a voltage output terminal. The sensing device includes a PMOS transistor and a lateral bipolar junction transistor.

Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p(or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under a high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.

Abstract: A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recovery characteristics without requiring heavy metal doping.

Abstract: A transistor structure includes a main gate silicon active region having a thickness of less than or equal to 30 nm; and auxiliary gate active regions located on either side of said main gate silicon active region, said auxiliary gate active regions being spaced a distance from said main gate active region of about 200 nm.

Abstract: A semiconductor device such as an IGBT, for realizing measurement precision for forward voltage effect characteristics using a relatively small current. It includes a second conductivity type of first anode region formed to partially constitute the upper surface of a first conductivity type of semiconductor substrate and having an anode electrode formed on its upper surface, a second anode region formed within said first anode region, and an anode electrode formed on said second anode region. The second anode region is electrically isolated from the first anode region, and the anode electrode formed on the upper surface of the second anode region is independent of the anode electrode formed on the upper surface of the first anode region. In such semiconductor device having said second anode region, even though a small force current, measurement can be performed at a current density which is equal to or close to a rated current.

Abstract: An array of light-sensitive sensors utilizes bipolar phototransistors that are formed of multiple amorphous semiconductor layers, such as silicon. In the preferred embodiment, the bipolar transistors are open base devices. In this preferred embodiment, the holes that are generated by reception of incoming photons to a particular open base phototransistor provide current injection to the base region of the phototransistor. The collector region is preferably an intrinsic amorphous silicon layer. The phototransistors may be operated in either an integrating mode in which bipolar current is integrated or a static mode in which a light-responsive voltage is monitored.

Abstract: The invention relates to a semiconductor component which is capable of blocking such as an (IGBT), a thyristor, a GTO or diodes, especially schottky diodes. An insulator profile section (10a, 10b, 10c, 10d, 11) provided in the border area of an anode metallic coating (1, 31) is fixed (directly in the edge area) on the substrate (9) of the component. The insulator profile has a curved area (KB) and a base area (SB), said curved area having a surface (OF) which begins flat and curves outward and upward in a steadily increasing manner. A metallic coating MET1; 30a, 30b, 30c, 30d, 31b) is deposited on the surface (OF). Said coating directly follows the surface curvature and laterally extends the inner anode metallic coating. The upper end of the curved metallic coating (MET1; 30a, 30b . . . ) is distanced and insulated from one of these surrounding outer metallic coatings (MET2; 3) by the surrounding base area (SB) of the insulator profile (10a, . . .

Abstract: In a multilayer logic device or processor device with a plurality of individually matrix-addressable stacked thin layers of an active material, the active material in each layer is provided between a first electrode set and a second electrode set wherein the electrodes in the first set realize the columns and the electrodes in the second set the rows in an orthogonal array. The intersections between the electrodes in the array define logic cells in the layer of active material, and the stacked layers of active material are provided on a common supporting substrate. A separation layer with determined electrical or thermal properties is provided between each layer of active material.

Abstract: Both the blocking voltage as well as the sweep voltage of conventional thyristors exhibit a pronounced temperature behavior, whereby the corresponding voltage values can change by up to 15% within the relevant temperature range (5° C.-120° C.). In the proposed thyristor, the overhead triggering is compelled by the “punch through” effect that is independent of the temperature (expanse of the space charge zone allocated to the p-base/n-base junction 10) up to the neighboring n-base/p-emitter junction 11). Due to the laterally non-uniform distribution of the dopant in the n+ stop zone (7′) of the anode-side base (7), further, it is assured that the central thyristor region always ignites first. Sweep or punch through voltage is not dependent on the temperature in the asymmetrical thyristors.

Abstract: In a gate turn-off thyristor (GTO) with homogeneous anode, emitter and stop layer, a device which short-circuit the stop layer with the anode is provided in an edge termination region. As a result, in a reverse-biased state, the GTO has a structure of a diode in the edge region and amplification of a reverse current is obviated. With this structure, thermal loading in the edge region is reduced, as the GTO tolerates a higher operating temperature at a predetermined voltage.

Abstract: A novel semiconductor switching device is disclosed. The switching device is designed and constructed to include, for example, a highly interdigitated cathode/gate structure on both anode and cathode sides. The semiconductor switching device can be multi-loaded on both anode and cathode sides which provides a great deal of flexibility in operation.

Abstract: There is provided a semiconductor substrate which includes a pair of main surfaces, a first semiconductor layer of a first conductivity type adjacent to one of the main surface, a second semiconductor layer of a second conducting type of which impurity concentration is lower than that of the first semiconductor layer and which is adjacent to the first semiconductivity, a third semiconductor layer of the first conductivity type adjacent to the second semiconductor, and a fourth semiconductor of the second conductivity type of which impurity concentration is higher than that of the third semiconductor and which is adjacent to the other of the main surfaces and the third semiconductor.

Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

Abstract: It is an object to obtain an insulated gate semiconductor device with an unreduced current value capable of being turned off while adopting structure for reducing the ON voltage, and a manufacturing method thereof. An N layer (43) is provided in close contact on a surface of an N.sup.- layer (42), a P base layer (44) is provided in close contact on the surface of the N layer (43), and a trench (47) which passes at least through the P base layer (44) is provided, and a gate electrode (49) is provided in the trench (47) through a gate insulating film (48). The carrier distribution of the N.sup.- layer (42) becomes closer to the carrier distribution of a diode, and an ON voltage is decreased and a current value capable of being turned off is not decreased when turning off. Accordingly, there are provided an insulated gate semiconductor device with low power consumption, small size, large capacity and high reliability.

Abstract: A p-type emitter layer having a low resistivity is arranged on a bottom surface of an n-type base layer having a high resistivity. A p-type base layer is formed in a top surface of the n-type base layer. Trenches are formed in the p-type base layer and the n-type base layer such that each trench penetrates the p-type base layer and reaches down to a halfway depth in the n-type base layer. Inter-trench regions made of semiconductor are defined between the trenches. An n-type emitter layer having a low resistivity is formed in a surface of the p-type base layer to be in contact with the upper part of each trench. A gate electrode is buried via a gate insulating film in each trench. That side surface of each inter-trench region which faces the gate electrode consists of a {100} plane.

Abstract: A GTO is specified which, starting from the anode-side main surface (2), comprises an anode emitter (6), a barrier layer (11), an n-base (7), a p-base (8) and a cathode emitter (9). The anode emitter (6) is designed as a transparent emitter and has anode short-circuits (10). By virtue of the combination of the barrier layer, the transparent anode emitter and the anode short-circuits, a GTO is obtained which can be operated at high switching frequencies, the substrate thickness of which can be reduced and which nevertheless exhibits no increase in the switching losses.

Abstract: The present invention provides a reverse conducting (RC) thyristor of a planar-gate structure for low-and-medium power use which is relatively simple in construction because of employing a planar structure for each of thyristor and diode regions, permits simultaneous formation of the both region and have high-speed performance and a RC thyristor of a buried-gate or recessed-gate structure which has a high breakdown voltage by the use of a buried-gate or recessed-gate structure, permits simultaneous formation of thyristor and diode regions and high-speed, high current switching performance, and the RC thyristor of the planar-gate structure has a construction which comprises an SI thyristor or miniaturized GTO of a planar-gate structure in the thyristor region and an SI diode of a planar structure in the diode region, the diode region having at its cathode side a Schottky contact between n emitters or diode cathode shorted region and the thyristor region having at its anode side an SI anode shorted structure fo

Abstract: A thyristor according to the invention comprises a layer sequence containing an n-type emitter layer (4), a p-type base layer (5), an n-type base layer (6) and a p-type emitter layer (7) in a semiconductor substrate (3) between an anode (1) and a cathode (2). The p-type emitter layer (7) is perforated by anode short-circuit zones (8) and is thereby subdivided into sections. In this arrangement, the anode short circuits (8) short-circuit the n-type base layer (6) to the anode (1). Disposed between the anode short circuits (8) and the p-type emitter layer (7) is a p-type barrier layer (9), also referred to as p-type soft layer. According to the invention, said p-type barrier layer (9) has gaps (12) in which the n-type base (6) is contacted by the anode (1) either directly or via an anode short circuit (8).

Abstract: In turn-off semiconductor components such as GTO thyristors, the semiconductor body can be locally overheated and destroyed as a consequence of inhomogeneities. The anode-side emitter is therefore doped with additional substances that locally compensate the emitter doping above the operating temperature and locally reduce the current amplification factor of the anode-side transistor structure. An increased turn-off current is thus achieved.

Abstract: A semiconductor device and a method for operating the same includes a first P-type semiconductor layer and a first N-type semiconductor layer provided thereon. A plurality of second P-type semiconductor layers and a plurality of third P-type semiconductor layers are formed on the surface of the first N-type semiconductor layer. A plurality of second N-type semiconductor layers are formed on their respective surfaces of the third P-type semiconductor layers. Emitter electrodes are provided on the second P-type semiconductor layers and second N-type semiconductor layers. A plurality of first gate electrodes is each provided above the first N-type semiconductor layer between the adjacent third P-type semiconductor layers. A plurality of second gate electrodes are each provided above the first N-type semi-conductor layer between the second P-type semiconductor layer and the third P-type semiconductor layer. A collector electrode is provided under the first P-type semiconductor layer.

Abstract: A monolithic semiconductor power switching device and a method of separating plural thyristor based active areas therein includes reverse conducting diode regions between the active areas. The reverse conducting diode regions influence current flow at the edges of the operable ones of the active areas so that current from an operable one of the active areas does not flow into and turn on an inoperable one of the active areas. The reverse conducting diode regions have a width so that substantially all of the carriers of the current from an operable one of the active areas recombine before reaching an adjacent active area.