Abstract: In order to compatibly implement improvement in withstand voltage and ON-state resistance as well as reduction in turnon loss and improvement in di/dt resistance, an n buffer layer (12) is locally exposed on a lower surface of a semiconductor substrate (160), while a polysilicon additional resistive layer (104) is formed to cover the exposed surface. An anode electrode (101) covering the lower surface of the semiconductor substrate (160) is connected to a p emitter layer (11) and the additional resistive layer (104). Thus, the n buffer layer (12) and the anode electrode (101) are connected with each other through the additional resistive layer (104), whereby a gate trigger current is reduced. Thus, turnon loss is reduced and di/dt resistance is increased. At the same time, the withstand voltage and the ON-state resistance are excellent due to provision of the n buffer layer (12).

Abstract: An object of the present invention is to provide a semiconductor device which is designed so as to increase a maximum controllable current and decrease hold current without degrading its characteristic and to provide a method of manufacturing such a semiconductor device. A transistor formation region 3 and a P diffusion region 15 are selectively formed through an insulating film 4 between gate electrodes 5 on an N.sup.- epitaxial layer 2. In a transistor formation region 3, an N.sup.+ diffusion region 12 is formed on a P diffusion region 11, a P diffusion region 13 is formed on the N.sup.+ diffusion region 12, and an N.sup.+ diffusion region 14 is selectively formed on a surface of the P diffusion region 13. Then, a cathode electrode 7 is formed on the P diffusion region 13, N.sup.+ diffusion region 14 and P diffusion region 15, and an anode electrode 8 is formed on a second major surface of the P.sup.+ substrate 1.

Abstract: A constant-voltage diode has a first semiconductor region of a first conductivity type, an adjoining semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type adjoining the second semiconductor region, and a fourth semiconductor region of the first conductivity type partially surrounded by the second semiconductor region. At low reverse biases between a cathode electrode and an anode electrode, the behavior of the device is determined by the pn junction between the first and second semiconductor regions. As the reverse biasing increases, the depletion layers of that junction will reach the fourth semiconductor region, but the reverse bias at this time is insufficient to break down that junction. A further increase of reverse bias causes breakdown of the pn junction between the third and fourth semiconductor regions. This effect is achieved by suitable impurity concentrations in the semiconductor regions.

Abstract: A reverse conducting gate turn-off thyristor (RC-GTO) includes, in the same semiconductor body, a gate turn-off thyristor, a reverse current diode, and a semiconductor isolation region between the gate turn-off thyristor and the reverse current diode and having a first conductivity type semiconductor layer adjacent an anode electrode and spaced apart second conductivity type high-dopant-impurity-concentration regions opposite the anode electrode.

Abstract: The present invention is directed to power semiconductor devices and, more particularly, to a semiconductor device with a static induction buffer structure which reduces the resistance of a buffer layer, enhances the injection efficiency of holes from the anode and permits the application of a high-intensity electric field across the cathode and anode, and a semiconductor device with a drift buffer structure in which an impurity density (concentration) gradient is set in a buffer layer to generate an internal electric field for holes to enhance the injection efficiency of holes from the anode and increase the electron storage efficiency or and impurity density (concentration) gradient is set in an anode region to generate an internal electric field for electrons and a high-intensity electric field can be applied across the cathode and anode.

Abstract: In a turn off type semiconductor device, an n-type emitter layer is divided into a plurality of elements by trenches. A silicide layer of a high melting point metal is provided on a p-type layer adjacent to the individual elements of the n-type emitter layer on a bottom of each of the trenches. A gate electrode is provided on the associated silicide layer so as to surround the plurality of elements of the n-type emitter layer obtained by the division of the emitter layer. An insulator is filled in each of the trenches dividing the n-type emitter layer surrounded by the gate electrode. A cathode electrode is provided on both the insulators and the n-type emitter layer.

Abstract: An MCT (MOS controlled thyristor) including a first outer layer of a first conductivity type whose surface contacts a first major electrode, and a second outer layer at which an MOS structure is disposed, and whose surface contacts a second major electrode. The MCT is provided with a second conductivity type region formed in the first outer layer in such a manner that it contacts the first major electrode, but does not contact an inner layer adjacent to the first layer. The MCT has a low on-resistance, a small turn-off loss, and can prevent a negative resistance phenomenon from occurring.

Abstract: A semiconductor structure comprises a gate-turn-off thyristor region (GR) and a diode region (DR) with an isolation area (SR) therebetween. The isolation area is provided with a multistage groove (30) having step structures (34,35). The multistage groove is formed through a two-stage etching process, and over-etched regions in the bottom corners of the multistage groove are relatively shallow ones. This structure is effective for increasing the breakdown voltage of the semiconductor structure and isolations between a the gate-turnoff thyristor region and the diode region.