Abstract: A semiconductor film is formed on a substrate. Subsequently, a resist film is formed on the semiconductor film, and dry etching is performed to the semiconductor film using the resist film as a mask. Due to the dry etching, the edge portion of the semiconductor film protrudes from the resist film. Next, the p-type impurities are introduced into the edge portion of the semiconductor film using the resist film as a mask. The volume density of the p-type impurities in a channel edge portion of the semiconductor film is two to five times the volume density of the p-type impurities in a channel center section. Subsequently, the resist film is removed to form a gate insulating film and a gate electrode.

Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: A switching semiconductor device includes a first compound layer formed on a single crystal substrate which includes silicon carbide or sapphire, and including a general formula InxGa1-xN, where 0?x?1; a second compound layer formed on the first compound layer, and including a general formula InyALzGa1-y-zN, where 0?y?1 and 0<z?1; and a gate electrode formed on the second compound layer. The gate electrode is electrically connected to a resistance element formed on a first interlayer insulating film that covers the gate electrode, through a metal wiring formed on a second interlayer insulating film that covers the first interlayer insulating film.

Abstract: Disclosed is a method for increasing substrate resistance in a silicon controlled rectifier in order to decrease turn on time so that the silicon controlled rectifier may be used as an effective electrostatic discharge protection device to protect against HBM, MM and CDM discharge events. Additionally, disclosed is an improved SCR structure that is adapted for use as an electrostatic discharge device to protect against human body model events by delivering an electrostatic discharge current directly to a ground rail. The improved SCR structure incorporates various features for increasing substrate resistance and, thereby, for decreasing turn on time. These features include a second n-well that functions as an obstacle to current flow, a narrow current flow channel between co-planar buried n-bands connected to a lower portion of the second n-well, a zero threshold voltage area, and an external resistor electrically connected between the SCR and the ground rail.

Abstract: The invention provides a method of manufacturing a fin-type field effect transistor (FinFET) that forms a unique FinFET that has a first fin with a central channel region and source and drain regions adjacent the channel region, a gate intersecting the first fin and covering the channel region, and a second fin having only a channel region.

Abstract: A thin film resistor (60) is contained between two metal interconnect layers (40, 100) of an integrated circuit. Contact may be made to the resistor (60) through vias (95) from the metal layer (100) above the resistor (60) to both the thin film resistor (60) and the underlying metal layer (40) simultaneously. The resistor (60) may include portions of a hard mask (70) under the vias (95) to protect the resistor material (60) during the via (95) etch. This design provides increased flexibility in fabricating the resistor (60) since processes, materials, and chemicals do not have to satisfy the conditions of both the resistor (60) and the rest of the integrated circuit (especially the interconnect layer 40) simultaneously.

Abstract: The forming of a contact with a deep region of a first conductivity type formed in a silicon substrate. The contact includes a doped silicon well region of the first conductivity type and an intermediary region connected between the deep layer and the well. This intermediary connection region is located under a trench. The manufacturing method enables forming of vertical devices, in particular fast bipolar transistors.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: An electron gun assembly resistor divides a voltage based on a predetermined voltage division ratio and permits a divided voltage to be applied to an electrode of an electron gun assembly. The electron gun assembly resistor is provided with an insulating substrate, a plurality of electrode elements formed on the insulating substrate, a resistor element having a pattern which connects the electrode elements together and which provides a predetermined resistance value, an insulating coating layer which covers the resistor element, and a plurality of metallic terminals connected to the electrode elements, respectively. The metallic terminals are arranged without exposing the electrode elements. The insulating coating layer covers the peripheries of the metallic terminals and are located away from the electrode elements.

Abstract: A field effect transistor semiconductor device (1) comprises a source region (33), a drain region (14) and a drain drift region (11), the device having a field shaping region (20) adjacent the drift region (11) and arranged such that, in use, when a voltage is applied between the source (33) and drain (14) regions and the device is non-conducting, a substantially constant electric field is generated in the field shaping region (20) and accordingly in the adjacent drift region (11). The field shaping region (20), which may be intrinsic semiconductor, is arranged to function as a capacitor dielectric region (20) between a first capacitor electrode region (21) and a second capacitor electrode region (22), the first and second capacitor electrode regions (21, 22) being adjacent respective ends of the dielectric region (20) and having different electron energy barriers.

Abstract: In a static induction transistor, in addition to a first gate layer (4), a plurality of second gate layers (41) having a shallower depth and a narrower gap therebetween than those of the first gate layer (4) are provided in an area surrounded by the first gate layer (4), thereby an SiC static induction transistor with an excellent off characteristic is realized, while ensuring a required processing accuracy during production thereof.

Abstract: In accordance with an embodiment of the present invention, a semiconductor rectifier includes an insulation-filled trench formed in a semiconductor region. Strips of resistive material extend along the trench sidewalls. The strips of resistive material have a conductivity type opposite that of the semiconductor region. A conductor extends over and in contact with the semiconductor region so that the conductor and the underlying semiconductor region form a Schottky contact.

Abstract: An object of the present invention is to improve the relationship between the switching loss and the conduction loss in a semiconductor device comprising a diode and a switching device made of silicon carbide, while suppressing occurrence of voltage oscillation of the device having a high amplitude. A resistor (12) is connected in parallel to a diode (11) made of silicon carbide. Although a resistive component of the diode (11) varies widely with turn-on and turn-off of the diode (11), connecting the resistor (12) in parallel to the diode (11) allows suppression of variations in a resistive component of an LCR circuit formed by the diode (11) and an external wiring. Accordingly, the LCR circuit is unlikely to satisfy the condition of natural oscillation and an increase in the quality factor of the LCR circuit is suppressed.

Abstract: The present invention provides a semiconductor device for detecting gate defects and the method of using the same to detect gate defects. The semiconductor device is comprised of a semiconductor substrate having an oxide layer on the top, a gate having spacers, formed on the oxide layer and surrounding the semiconductor substrate, wherein the gate is also patterned to divide the semiconductor substrate into two parts not electrically connected, and a conductive layer formed on the semiconductor outside the gate. In addition, the method for using the semiconductor device of the present invention to detect gate defects is comprised of applying a ground voltage and a set voltage respectively to two parts divided by the gate in the semiconductor device, and measuring current between the two parts.

Abstract: A semiconductor chip provided, at a lateral face thereof, with an electrode for external electric connection. Where a semiconductor chip has a plurality of electrodes, all the electrodes are preferably formed at one or more lateral faces of the semiconductor chip. Each electrode is preferably embedded in a groove which is formed in a lateral face of the semiconductor chip and which is opened laterally of the semiconductor chip. The semiconductor chip may be a discrete bipolar transistor element. In this case, each of the base electrode, the emitter electrode and the collector electrode is preferably formed at a lateral face of the semiconductor chip.

Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping surface area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved. The compound semiconductor device is also formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.

Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.

Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area of the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping surface area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved. The compound semiconductor device is also formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.

Abstract: An integrated power device having a power transistor made up of a first diode and a second diode that are connected together in series between a collector region and emitter-contact region of the power transistor to define a common intermediate node, a control circuit including a high-voltage region bonded on the emitter-contact region (14) by means of an adhesive layer, and biasing circuit connected between the common intermediate node and the high-voltage region. The biasing circuit including a contact pad electrically connected to the common intermediate node, an electrical connection region that is in electrical contact with the high-voltage region (30), and a wire having a first end soldered on the contact pad and a second end soldered on said electrical connection region.

Abstract: The thyristor is based on a semiconductor body with an anode-side base zone of the first conductivity type and one or more cathode-side base zones of the opposite, second conductivity type. Anode-side and cathode-side emitter zones are provided, and at least one region in the cathode-side base zone whose geometry gives it a reduced breakdown voltage as compared with the remaining regions in the cathode-side base zone and the edge of the semiconductor body. At the anode, below the region of reduced breakdown voltage, the thyristor has at least one recombination zone in which the free charge carriers have a reduced lifetime.

Abstract: A resistor element according to the present invention comprises a resistive layer provided on a semiconductor substrate through a first insulating film, a first wiring layer provided on the resistive layer through a second insulating film, a second wiring layer provided on the first wiring layer through a third insulating film, a first contact region including a plurality of contacts and provided in the second insulating film and the third insulating film, for electrically connecting the resistive layer to the second wiring layer and a second contact region including a plurality of contacts and provided in the second insulating film, for electrically connecting the resistive layer to said first wiring layer. The contacts of the second contact region are arranged on and along a periphery of a polygonal shape having a center registered with a center point of the first contact region.

Abstract: A semiconductor device having a CMOS structure, wherein, in manufacturing a CMOS circuit, an impurity element which imparts p-type conductivity to the active layer of the p-channel type semiconductor device is added before forming the gate insulating film. Then, by applying thermal oxidation treatment to the active layer, the impurity element is subjected to redistribution, and the concentration of the impurity element in the principal surface of the active layer is minimized. The precise control of threshold voltage is enabled by the impurity element that is present in a trace quantity.

Abstract: The present invention relates to a thin film transistor (TFT), liquid crystal display (LCD) and fabricating methods thereof, and more particularly to a TFT having source/drain lines on which an insulating layer and an active layer are located lie on an insulated substrate, to an LCD using the TFT and fabricating methods of the TFT and LCD. The TFT has a BBC (Buried Bus Coplanar) structure by forming a source/drain line on a substrate and by forming a buffer layer which covers the source/drain line which simplifies the process by means of reducing the number of deposition steps. The BBC structure of TFT has a source/drain line on a substrate, an insulating layer covering the source/drain line and the entire disclosed surface and a coplanar structure on the insulating layer. The present invention also provides a data line in the TFT of the BBC structure having low resistance applicable to a wide-screen by means of forming both the buffer layer and the source/drain line with a sufficient thickness.

Abstract: The present invention relates to an isolating wall for separating elementary components formed in different wells, a component located in at least one of the wells being capable of operating with a high current density. The isolating wall exhibits in its median portion a concentration of carriers higher than 1016 atoms/cm3. Preferably, the width of the openings from which the dopant diffusions are formed in the upper and lower surfaces of the substrate is higher than 1.3 times the half-thickness of the substrate.

Abstract: An insulated-gate bipolar semiconductor device is provided wherein electric resistance generated in an emitter impurity region and between an emitter electrode and a region in the close vicinity of a gate takes a prescribe value irrespective of the distance of the emitter impurity region in direct contact with the emitter electrode in order to increase a load short circuit safe operation region without degrading the forward voltage drop and switching characteristic.

Abstract: An electrostatic discharge protective circuit of the invention includes a silicon controller rectifier (SCR) and a current diverter. The current diverter is used to bypass an initial low current thereby to prevent the SCR from being triggered by the low current. Thus, a trigger current required to activate the SCR can be greatly increased thereby to maintain an internal circuit at a normal operating state.

Abstract: In a chip type resistor, a middle coat which is a component of a cover coat has extensions or enclaves formed at portions on a surface of main upper electrodes of terminal electrodes. Auxiliary upper electrodes of terminal electrodes are formed extending over both the surface of extensions or enclaves of middle coat and the surface of main upper electrodes. Therefore, the step between the surface of terminal electrodes at opposing ends of resistive film and the surface of cover coat for the resistive film can be reduced or eliminated with low cost.

Abstract: The present invention relates to a component protecting against electric overloads likely to occur on a conductor in series with which is placed a detection resistor. The component includes a first cathode-gate thyristor and a second anode-gate thyristor, of the gate current or forward break-over type. The anode region of the first thyristor, formed on the lower surface side, is separate from the isolating wall surrounding the thyristor and the rear surface of the isolating wall is coated with a portion of an insulating layer.

Abstract: A semiconductor component has a semiconductor body with at least one integrated lateral resistor. The lateral resistor is formed with a dopant concentration in the resistor region. The resistor region is located in a region which is accessible from the surface of the semi-conductor component and it has a defined dopant concentration. Scattering centers are provided in the region of the lateral resistor which reduce a temperature dependency of the lateral resistor.

Abstract: A bistable SCR-like switch (41) protects a signal line (65) of an SOI integrated circuit (40) against damage from ESD events. The bistable SCR-like switch (41) is provided by a first and a second transistors (42 and 44) which are formed upon the insulator layer (46) of the SOI circuit (40) and are separated from one another by an insulating region (60). Interconnections (62 and 64) extend between the two transistors (42 and 44) to connect a P region (62) of a first transistor (42) to a P region (54) of the second transistor (44) and an N region (50) of the first transistor (42) to an N region (58) of the second transistor (44). The transistors (42 and 44) may be either bipolar transistors or enhancement type MOSFET transistors. For bipolar transistors, the base of an NPN transistor (42) is connected to the collector of a PNP transistor (44) and the base of the PNP transistor (44) is connected to the collector of the NPN transistor (42).

Abstract: An amplifying-gate thyristor having an increased integrated circuit includes a main thyristor and an amplifying thyristor. The amplifying thyristor is of the gate turnoff-type. The main thyristor and the amplifying thyristor are such that the amplifying thyristor remains in the conductive state while the main thyristor is conductive. A control circuit turns off the amplifying thyristor when the current through the main thyristor is approximately its hold current.

Abstract: The invention provides a silicon controlled rectifier having an anode and a cathode and including an NPN transistor and a PNP transistor. The NPN transistor has an emitter coupled to the cathode, a base and a collector. The PNP transistor has a base coupled to the NPN collector, an emitter coupled to the anode, a first collector coupled to the NPN base and a second collector coupled to the NPN collector.

Abstract: A first metal electrode layer is formed to be electrically connected with a p base region formed in an n drift region. A second metal electrode layer which is electrically connected with an emitter region provided in the p base region is formed. A direct current power supply unit is provided to be electrically connected with the first and second metal electrode layers. The direct current power supply unit functions as means for applying forward bias to a pn junction between the n emitter region and the p base region.

Abstract: A monolithic assembly of thyristors having a common cathode and a single gate includes a lightly-doped substrate, several anode regions, on the front surface side, a cathode gate layer on the rear surface side of the substrate, a cathode layer on the rear surface side of the layer coated with a cathode metallization, a well extending from the front surface to the layer, a gate metallization formed on the upper surface of the well, and means for increasing the leakage resistance between the cathode layer and the cathode gate layer.

Abstract: A monolithic semiconductor component has a first thyristor having a gate, an anode and a cathode. The gate is connected to the cathode through a first resistor and to the anode through the series connection of a zener diode and a second thyristor. The thyristors are of the vertical type and the zener diode is of the lateral type. The cathode of the zener diode is connected to the cathode of the second thyristor through a metallization forming an output terminal.

Abstract: A segmented SCR ESD protection circuit for discharging an external electrostatic stress on a semiconductor integrated circuit is formed over a semiconductor substrate. The protection circuit includes an SCR device and a number of resistors. The SCR device is separated into a plurality of SCR segments for suppressing the occurrence of the secondary breakdown. Each of the resistors is connected to one of the SCR segments. The resistors can be in the form of parasitic resistances of the SCR device or in the form of additional electronic components formed on the semiconductor substrate.

Abstract: A semiconductor device structure having an epitaxial layer, formed of silicon for example, is disposed on a high band-gap material, such as silicon carbide, which is in turn disposed on a semiconductor substrate, such as silicon. The high band gap material achieves a charge concentration much higher than that of a conventional semiconductor material for the same breakdown voltage.

Abstract: A reverse conducting gate-turnoff thyristor includes a switching device section, a diode section, and an isolating section located between the switching device section and the diode section. The isolating section includes an impurity layer formed by controlling impurity diffusion and having an impurity concentration lower than those of the switching device section and the diode section.

Abstract: An SCR circuit formed on a semiconductor substrate includes a well region, a first diffusion region and a second diffusion region in the well region, and a third diffusion region in the substrate. The SCR circuit also includes a capacitor connected between the first diffusion region and the third diffusion region. The junction region between the well region and the diffusion region is forward biased when an electrostatic force is applied to the SCR circuit, thereby triggering the SCR circuit to discharge the electrostatic force.

Abstract: A semiconductor device is disclosed having a thyristor region coupled to a semiconductor switching device and a semiconductor rectifier. During turn-off operation, holes are drained from the p-type base region of the thyristor region through the semiconductor rectifier and to the cathode of the thyristor. During turn-on, electrons are supplied to an n-type emitter region of the thyristor from the cathode electrode through the semiconductor switching device.

Abstract: An amplifying-gate thyristor having an increased integrated circuit includes a main thyristor and an amplifying thyristor. The amplifying thyristor is of the gate turnoff-type. The main tbyristor and the amplifying thyristor are such that the amplifying thyristor remains in the conductive state while the main thyristor is conductive. A control circuit turns off the amplifying thyristor when the current through the main thyristor is approximately its hold current.

Abstract: MOS-gate controlled thyristor structures which have current saturation characteristics, do not have any parasitic thyristor structure, and require only a single gate drive. A resistive structure such as a MOSFET, Schottky diode, PN junction diode, diffused resistor or punch-through device (e.g. punch through PNP structure) is incorporated in series with the N.sup.+ emitter of the thyristor. In the on-state of the device, with a positive gate voltage, when operating at high currents, because of the voltage drop in the resistive structure in series with the N.sup.+ emitter, the potential of the N.sup.+ emitter, and along with it the potential of the P base, increases. When the potential is increased beyond a certain predetermined value, diversion of current is accomplished by one of the following ways: (i) the smallest distance between the P base region and the P.sup.+ cathode is such that punch-through occurs in these regions.

Abstract: In a gate insulated static induction thyristor with a split gate type shorted cathode structure, a first gate of the split gate structure is used as a cathode short-circuit gate and the cathode region is formed in the second gate. A MOS structure is formed on the second gate as a control gate electrode isolated therefrom. Since the channel integration density is high, the area efficiency increases. The MOS gate structure suppresses the minority carrier (hole) storage effect to permit high-speed swtching of the thyristor, and the shorted cathode structure provides for increased maximum controllable current/voltage durability. The split gate structure can be used in combination with planar, buried, recessed and double gate structures.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: An emitter switched thyristor (EST) has improved turn-off withstand capability without deteriorating its on-voltage. The EST obtains a potential drop through a resistor disposed between the main electrode and the base region and facilitates uniformly recovering the reverse-blocking ability of the PN junction, in contrast to the ESTs of the prior art which obtain the potential drop by the current in Z-direction for latching up the thyristor from the IGBT mode. The present EST may be formed also in a horizontal device or a trench structure.

Abstract: A polysilicon gate resistor consists of a plurality of parallel polysilicon strips extending from gate finger to gate pad. Different numbers of parallel strips can be selected during manufacture by using different contact masks.

Abstract: In order to compatibly implement improvement in withstand voltage and ON-state resistance as well as reduction in turnon loss and improvement in di/dt resistance, an n buffer layer (12) is locally exposed on a lower surface of a semiconductor substrate (160), while a polysilicon additional resistive layer (104) is formed to cover the exposed surface. An anode electrode (101) covering the lower surface of the semiconductor substrate (160) is connected to a p emitter layer (11) and the additional resistive layer (104). Thus, the n buffer layer (12) and the anode electrode (101) are connected with each other through the additional resistive layer (104), whereby a gate trigger current is reduced. Thus, turnon loss is reduced and di/dt resistance is increased. At the same time, the withstand voltage and the ON-state resistance are excellent due to provision of the n buffer layer (12).

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.