Abstract: A semiconductor substrate includes a plurality of parallel resistor films connected between a pair of conductor strips. The resistor films and conductor strips are coated with a protective coat. The resistor films are cut one by one by laser trimming to adjust the total resistance value of the plurality of parallel resistor films. The protective coat on the uncut resistors remains unremoved.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: A MOS-controlled thyristor which has current saturation characteristics and does not have any parasitic thyristor structure. In some embodiments, the device has two gate drives and is a four terminal device. In other embodiments, the device requires only a single gate drive and is a three terminal device. The device can be constructed in a cellular geometry. In all embodiments, the device has superior turn-off characteristics and a wider Safe-Operating-Area because the N.sup.++ emitter/P base junction is reverse biased during turn-off.

Abstract: In integrated structure sensing resistor for a power MOS device consists of a doped region extending from a deep body region of at least one cell of a first plurality of cells, constituting a main power device, to a deep body region of a corresponding cell of a second smaller plurality of cells constituting a current sensing device.

Abstract: An ESD protection circuit which provides protection for CMOS devices against ESD potentials of up to about 10 kV is provided. The ESD protection circuit is able to provide protection against both positive-going and negative-going high energy electrical transients, and is able to maintain a high impedance state when driven to a voltage beyond the supply rails of CMOS integrated circuit, but less than tile breakdown voltage of the ESD protection circuit. The ESD protection circuit routes currents associated with ESD potentials to a predetermined arbitrary point which may be selected during the fabrication process to meet the needs of a particular application. The structure of the ESD protection circuit permits the holding current to be adjusted to accommodate the current capacity of various external circuits.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with, but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: An optically triggered silicon controlled rectifier (SCR) circuit (20) has a number of semiconductor layers diffused into an N- substrate (21). The layers form an SCR (50) having a P+ anode region (25), a P+ gate region (24), and an N+ cathode region (27). An adjustable base-shunt resistance, in the form of a P- channel depletion mode MOSFET (Q3), connects between the SCR gate region and the cathode region. The MOSFET includes a MOSFET gate region (35), a P+ drain region (24), a P-- channel (26), and a P+ source region (23). The substrate also accommodates a PN photodiode (22, D1) which connects to the MOSFET gate region for switching the MOSFET on and off in response to incident optical radiation (L) thereon. The SCR gate region also comprises photosensitive material. When sufficient optical radiation illuminates the photodiode and the SCR gate region, the MOSFET is turned off and the SCR is triggered, permitting anode-to-cathode current to flow.

Abstract: A MOS-controlled thyristor which has current saturation characteristics and does not have any parasitic thyristor structure. The device requires only a single gate drive and is a three terminal device. The device can be constructed in a cellular geometry. In all embodiments, the device has superior turn-off characteristics and a wider Safe-Operating-Area because the N.sup.++ emitter/P base junction is reverse biased during turn-off.

Abstract: The sensitivity of breakdown voltage to temperature and dV/dT induced currents is reduced in semiconductor power devices having a wide base transistor. The sensitivity is reduced by diverting current from the emitter of the wide base transistor to the base of the wide base transistor (an emitter short that does not reduce breakdown voltage) or by injecting a current into the base of the wide base transistor to its collector (an injected current that may lower the breakdown voltage, but no more than that related to temperature and capacitive current). The invention finds application in both epitaxial grown and substrate based devices.

Abstract: A monolithic protection component is formed in a P-type low-doped semiconductor substrate. The protection diode comprises, in an upper surface of the substrate, a first and a second N-type well with a mean doping level; at the surface of the first well, a first highly doped P region; at the surface of the second well, a second very highly doped N region; a third very highly doped N region laterally contacting the first well; a fourth highly-doped P region beneath a portion of the lower surface of the third region; a first metallization contacting the surface of the first and second regions which constitute the first diode terminal; and a second metallization coupled to a P-type area extending up to the fourth region and second well, which forms the second terminal of the diode. The protection component provides a unidirectional protection diode. Two of the protection components may be combined in a single structure to provide a bidirectional protection diode.

Abstract: In a semiconductor device having insulated gate field effect transistors and bipolar transistors, a buried layer of a first conductivity type having an impurity concentration higher than that of a second layer of the first conductivity type is disposed in at least a lower region between a second layer of a second conductivity type and a third layer of the second conductivity type and in the vicinity of a boundary between the second layer of the first conductivity type, which serves as back gates of the field effect transistors and base layers of the bipolar transistors, and the first layer of the second conductivity type.

Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

Abstract: A power semiconductor device constituted of a MOSFET incorporating a current detecting function for detecting current making use of a voltage drop developed across a channel resistance in which variations in the channel resistance due to its temperature and the gate voltage are compensated for and thereby highly accurate current detection is achieved.

Abstract: A channel in which electron current is supplied from n.sup.+ type source layer to an n.sup.- type base layer is formed in a thyristor portion by using a first gate electrode to have an electrical connection in a thyristor state. Injection of hole current to a p type base layer, which is necessary to maintain the thyristor state is extracted to a source terminal by a control MOSFET portion including a second gate electrode a turn-off time and the state of this device is changed to the transistor state similar to that in the IGBT so that a short switching time turn-off is realized.

Abstract: The input ESD protection circuit of the present invention uses a series n+ active area resistor placed in an n-well placed in series with shunt transistor all of which are in parallel with an SCR shunt to ground circuit, thereby providing greater than +/-7000V HBM (the Mil. Std. human body model (HBM) test model) and +/-600V MM EIAJ (the EIAJ machine model (MM) test model) ESD protection response. The series n+ active area resistor is placed inside an n-well as are all metal contacts to the input, to improve junction integrity during an ESD event. The parallel SCR circuit is designed in a layout that has an n+ diffusion area tied to V.sub.SS surrounding the n+/p+ diffusion inside the n-well on three sides to provide greater surface area for current distribution.

Abstract: A bi-directional switch includes a well region of a first conductivity type placed within a substrate. A first region of second conductivity type is placed within the well. A second contact region of second conductivity type is placed within the well. A drift region of second conductivity is placed between the first contact and the second contact. The drift region is separated from the first contact by a first channel region and is separated from the second contact by a second channel region. A first gate region is placed over the first channel region and a second gate region over the second channel region.

Abstract: A static induction device (SI device) at least shares a structure in which an SI thyristor, an IGT and a capacitor are merged onto the single monolithic chip. The SI thyristor has a cathode, an anode and a gate regions, and a channel. The IGT has a well on a surface of the channel, a source and drain regions within the well, a gate insulating film on the well, and a gate electrode on the gate insulating film. The capacitor comprises the gate region of the SI thyristor, the gate insulating film on the gate region, and the gate electrode. The cathode and the drain region are connected to each other through a high-conductive electrode.

Abstract: A monolithic protection component is formed in a P-type low-doped semiconductor substrate. The protection diode comprises, in an upper surface of the substrate, a first and a second N-type well with a mean doping level; at the surface of the first well, a first highly doped P region; at the surface of the second well, a second very highly doped N region; a third very highly doped N region laterally contacting the first well; a fourth highly-doped P region beneath a portion of the lower surface of the third region; a first metallization contacting the surface of the first and second regions which constitute the first diode terminal; and a second metallization coupled to a P-type area extending up to the fourth region and second well, which forms the second terminal of the diode. The protection component provides a unidirectional protection diode. Two of the protection components may be combined in a single structure to provide a bidirectional protection diode.

Abstract: A semiconductor device including a switching device such as a MOSFET or an IGBT, and an avalanche device for protecting the switching device by generating an avalanche current when an overvoltage is applied to the switching device. The avalanche device shares a drift layer, that is, an epitaxial layer with the switching device. With this arrangement, the avalanche voltage of the avalanche device follows changes in the withstanding voltages of the switching device due to variations in the thickness or impurity concentration of the epitaxial layer or temperature. This makes it possible to reduce the margin between the avalanche voltage of the avalanche device and the withstanding voltage of the switching device, and to positively protect the switching device from damage.

Abstract: A switching device includes a thyristor and a MOSFET, and a voltage clamp circuit. The voltage clamp circuit includes an N.sup.+ type contact region formed in a surface layer of a N type substrate and electrically connected to a gate electrode of a MOSFET, and a P type guard ring surrounding the contact region.

Abstract: An emitter of a thyristor is divided into a plurality of emitter regions. An electrode is provided next to each of these regions, and a turn-off current path proceeds via this electrode from the base adjoining the emitter region over a first field effect transistor to a main terminal of the thyristor. Every emitter region is also connected to this main terminal via a second field effect transistor which is integrated into the semiconductor body of the thyristor, or is manufactured in thin-film technology.

Abstract: A semiconductor switching device that is suitable for use as a remote isolation device (RID) in telephone networks. The semiconductor switching device is a two-terminal voltage sensitive device that switches from an open-circuit condition to a short-circuit condition at a fixed breakover voltage, appears as an open-circuit below the breakover voltage, and appears as a short-circuit above the breakover voltage. When semiconductor switching devices are installed in a telephone network, they are held in their short-circuit condition by the network voltage supply and do not affect the normal operation of the network but will switch to their open-circuit condition if the network voltage supply is reduced to below the breakover voltage, and therefore, parts of the network may be isolated from each other by reducing the voltage supply. Isolation of the parts of the network from each other facilitates testing for maintenance purposes.

Abstract: A bidirectional two-terminal ungated thyristor (9) having two wide-base portions (25, 27). The bidirectional two-terminal ungated thyristor (9) has a first semiconductor device having a first narrow-base portion (28) in series with a first wide-base portion (25), and a second semiconductor device having a second narrow-base portion (26) in series with a second wide-base portion (27). A width of the first wide base portion (25) and a width of the second wide base portion (27) are decreased to decrease a total base width. The first and second wide-base portions (25, 27) having a decreased width produce a low forward voltage drop across the bidirectional two-terminal ungated thyristor (9); thus, improving a power dissipation capability of the bidirectional two-terminal ungated thyristor (9).

Abstract: A conductivity modulation type MISFET, and a control circuit thereof are provided. A semiconductor device 1 comprises a conductivity modulation type MOSFET 1a and a built-in MOSFET 1b which is designed to control a source electrode 12a and a control electrode 13 of a parasitic transistor to be in a short state or an open state, said conductivity modulation type MOSFET 1a having a polysilicon gate 6 on an obverse surface of n.sup.- -type conductivity modulation layer 4, a p-type channel diffusion area 7, n.sup.+ -type source diffusion area 8 and a parasitic transistor control electrode 13 conductively connected to the p-type channel diffusion area 7 through a p.sup.+ -type contact area 9.

Abstract: A base resistance controlled thyristor with integrated single-polarity gate control includes a thyristor having an anode region, a first base region, a second base region on the first base region and a cathode region contacting the second base region and defining a P-N junction therewith. For providing gated turn-off control, a depletion-mode field effect transistor is provided on the second base region and is separated therefrom by an insulating region. In particular, an insulating region, such as a buried dielectric layer, is provided on the second base region and the depletion-mode field effect transistor is formed thereon. The depletion-mode field effect transistor is electrically connected between the cathode contact and the second base region and provides a direct electrical connection therebetween in response to a turn-off bias signal which is preferably a zero or near zero bias.

Abstract: A method for fabricating polysilicon resistors of intermediate high value for use as cross-coupling or =ingle event upset (SEU) resistors in memory cells. A thin polysilicon film is implanted with arsenic ions to produce a predetermined resistivity. The thin film is then implanted with fluorine ions to stabilize the grain boundaries and thereby the barrier height. Reducing the variation in barrier height from run to run of wafers allows the fabrication of reproducible SEU resistors.

Abstract: A semiconductor device including a semiconductive substrate having first and second opposite surfaces; a thyristor formed on the substrate and including a base layer formed in the first surface of the substrate, a first emitter layer formed in the base layer, a conductive layer electrically connected to the emitter layer to serve as a cathode electrode, a first gate electrode connected to the base layer, a second emitter layer formed in the second surface of the substrate, a drain layer formed in the second emitter layer, a conductive layer for electrically connecting the second emitter layer with said drain layer and for serving as an anode electrode of said thyristor. A metal oxide semiconductor field effect transistor is provided to accelerate the flow of carriers in said thyristor to the anode electrode to turn off said thyristor.