Abstract: An overvoltage protection device having multiple shorting dots in the emitter region and multiple buried regions substantially aligned with these shorting dots. The placement, number, and area of these buried regions reduce and more accurately set the overshoot voltage value of the device while maintaining the high surge capacities of the device. Further, doping types and concentrations have been modified from that known in the prior art to reduce overshoot providing a more accurate and sensitive overvoltage protection device than that known previously in the prior art.

Abstract: An object of the present invention is to provide a semiconductor device which is designed so as to increase a maximum controllable current and decrease hold current without degrading its characteristic and to provide a method of manufacturing such a semiconductor device. A transistor formation region 3 and a P diffusion region 15 are selectively formed through an insulating film 4 between gate electrodes 5 on an N.sup.- epitaxial layer 2. In a transistor formation region 3, an N.sup.+ diffusion region 12 is formed on a P diffusion region 11, a P diffusion region 13 is formed on the N.sup.+ diffusion region 12, and an N.sup.+ diffusion region 14 is selectively formed on a surface of the P diffusion region 13. Then, a cathode electrode 7 is formed on the P diffusion region 13, N.sup.+ diffusion region 14 and P diffusion region 15, and an anode electrode 8 is formed on a second major surface of the P.sup.+ substrate 1.

Abstract: A notched insulation gate static induction transistor integrated circuit ording to the present invention comprises an enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to prevent current from flowing in a standby mode, and a depletion enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to cause current to slightly flow in the standby mode. The enhancement mode CMOS logic circuit and the depletion enhancement mode CMOS logic circuit are formed on a major surface of a substrate, and the depletion enhancement mode CMOS logic circuit is used in a circuit in which an average power consumption in a switching operation is higher than that in the standby mode.

Abstract: A gate turn-off thyristor having a p-emitter layer in the anode side, an n-base layer, a p-base layer and an n-emitter layer in the cathode side. The n-base layer is composed of a first layer portion adjacent to the p-emitter layer, a second layer portion adjacent to the p-base layer and having a lower impurity concentration than the first layer portion, and is constituted by a structure which alters a travelling path of positive holes injected from the p-emitter layer.

Abstract: In a semiconductor device having insulated gate field effect transistors and bipolar transistors, a buried layer of a first conductivity type having an impurity concentration higher than that of a second layer of the first conductivity type is disposed in at least a lower region between a second layer of a second conductivity type and a third layer of the second conductivity type and in the vicinity of a boundary between the second layer of the first conductivity type, which serves as back gates of the field effect transistors and base layers of the bipolar transistors, and the first layer of the second conductivity type.

Abstract: A general object of the present invention is to make a maximum controllable current large without exerting adverse effect on other characteristics. In a surface of an n.sup.- layer 2 formed on a p.sup.+ substrate 1, p diffusion regions 3a, 3b and 3c are formed separated by n.sup.+ diffusion regions 4a, 4b and an oxidation film 9. Above the p diffusion regions 3b and 3c, gate electrodes 5a and 5b are formed insulated from the surrounding by an oxidation film 6. An Al-Si electrode 7 is in contact with the p diffusion region 3a and the n.sup.+ diffusion region 4a while a metal electrode 8 is in contact with the p.sup.+ substrate 1. By virtue of interposition of the oxidation film 9, a thyristor consisting of the n.sup.+ diffusion region 4a, p diffusion region 3a, n.sup.- layer 2 and p.sup.+ substrate 1 is prevented from being actuated.

Abstract: The semiconductor device is formed of an EST part and an IGBT part, wherein the EST part has a first MOSFET and a second MOSFET synchronously switching, and the IGBT part has a third MOSFET controllable independently from them. At a turn-off of the semiconductor device, when turning off the first and second MOSFETs while keeping the third MOSFET at an on-state, IGBT operation remains. Thus, the current path which tends to flow to an emitter region changes toward an emitter electrode side even if the recovery of the potential barrier is late due to the junction in the emitter region, and the charge accumulation to the emitter region is restrained. After the potential barrier is recovered, the third MOSFET is turned off. Controllable turn-off current can be enlarged and turn-off time can be shortened.

Abstract: A semiconductor device including a normally-on SI thyristor, and a MOSFET connected in cascade with the SI thyristor. The gate of the SI thyristor is connected to the source of the MOSFET. This arrangement makes it possible to turn the device on and off by controlling only the voltage gate of the MOSFET, obviating a current to maintain the on state of the device. The device needs little driving energy and has a low on state voltage and a high switching speed. It can readily be integrated into one chip.

Abstract: The present invention is directed to power semiconductor devices and, more particularly, to a semiconductor device with a static induction buffer structure which reduces the resistance of a buffer layer, enhances the injection efficiency of holes from the anode and permits the application of a high-intensity electric field across the cathode and anode, and a semiconductor device with a drift buffer structure in which an impurity density (concentration) gradient is set in a buffer layer to generate an internal electric field for holes to enhance the injection efficiency of holes from the anode and increase the electron storage efficiency or and impurity density (concentration) gradient is set in an anode region to generate an internal electric field for electrons and a high-intensity electric field can be applied across the cathode and anode.

Abstract: Between electrodes (9) and (10) are formed a p.sup.+ substrate (2), an n.sup.- epitaxial layer (1) having a protruding portion (3), an n.sup.+ diffusion region (4) and p.sup.+ diffusion regions (13). Control electrodes (6) are formed on insulating films (5) on opposite sides of the protruding portion (3) and n.sup.+ diffusion region (4). The potential at the control electrodes (6) is increased or decreased with the potential at an electrode (10) increased relative to an electrode (9) to generate potential barrier or conductivity modulation in the n.sup.- epitaxial layer (1), whereby a semiconductor device turns off or on. Introduced holes are drawn through the p.sup.+ diffusion regions (13) when the semiconductor device turns off, to provide a small resistance and a short distance when the holes are drawn without changes in the area of the n.sup.+ diffusion region (4). This permits the semiconductor device to have small switching loss and high switching speed with a low ON-voltage.

Abstract: An N.sup.+ buffer layer (2) and an N.sup.- layer (3) are provided on a P.sup.+ silicon substrate (1) in this order. On an upper portion of the N.sup.- layer (3), a P.sup.- layer (4b) is selectively formed, and on the P.sup.- layer (4b), a P.sup.+ layer (4a) is provided. On part of an top surface of the P.sup.+ layer (4a), a plurality of N.sup.+ layers (5a) are provided, and a trench (13) is formed extending through each of the N.sup.+ layers (5a) and P.sup.+ layer (4a) downwards to the P.sup.- layer (4b). In the P.sup.- layer (4b), an N.sup.+ floating layer (5b) is provided covering the bottom face of each trench (13). In the inner hollow of the trench (13), a gate electrode (8a) is provided through a gate oxidation film (7a), while an emitter electrode (9a) is provided extending between the top surfaces of the adjacent N.sup.+ layers (5a) with the surface of the P.sup.+ layer (4a) interposed so as to electrically short circuit them. A collector electrode (10) is provided on a lower major surface of the P.

Abstract: An emitter switched thyristor without parasitic thyristor latch-up susceptibility includes a thyristor having an anode region, a first base region, a second base region in the first base region and an emitter region of first conductivity type in the second base region. An electrical connection is provided between the emitter region and the cathode contact by a field effect transistor in the first base region. The transistor is positioned adjacent the second base region and includes a source electrically connected to the emitter region by a metal strap on the surface of the substrate. The drain of the transistor is electrically connected to the cathode contact and has a conductivity type opposite the conductivity type of the first base region. Accordingly, the cathode contact and anode contact are not separated by a four layer parasitic thyristor. Parasitic latch-up operation is thereby eliminated.

Abstract: A base resistance controlled thyristor with integrated single-polarity gate control includes a thyristor having an anode region, a first base region, a second base region on the first base region and a cathode region contacting the second base region and defining a P-N junction therewith. For providing gated turn-off control, a depletion-mode field effect transistor is provided on the second base region and is separated therefrom by an insulating region. In particular, an insulating region, such as a buried dielectric layer, is provided on the second base region and the depletion-mode field effect transistor is formed thereon. The depletion-mode field effect transistor is electrically connected between the cathode contact and the second base region and provides a direct electrical connection therebetween in response to a turn-off bias signal which is preferably a zero or near zero bias.

Abstract: A merged P-I-N/Schottky power rectifier includes trenches, and P-N junctions along the walls of the trenches and along the bottoms of the trenches. By forming the P-N junctions along the trench walls, the total area of the P-N junctions relative to the surface area of the device can be increased, to thereby improve the device's on-state characteristics without sacrificing the total area of the Schottky region. The trenches may be U or V shaped in transverse cross-section or of other transverse cross-sectional shape, and the trenches may be polygonal or circular in top view.

Abstract: A semiconductor device includes a thyristor (4,5,8,9) in which connection is made to the cathode region (9) of the thyristor by means of an MOS structure. The MOS structure is provided by a fifth region (11) forming a pn junction with the cathode region (9), a sixth region (13) in contact with the cathode electrode (C) and forming a pn junction (14) with the fifth region (11), and an insulated gate (15) overlying a conduction channel area (110) of the fifth region (11) for defining a gateable conductive path for charge carriers into the cathode region (9) to initiate thyristor action. The conductive path is thus controlled by the voltage applied to the insulated gate (15), enabling the flow of charge carriers to the cathode region (9) to be stemmed by application of an appropriate gate voltage oxide. The fifth region (11) is electrically connected to provide a path for extraction of charge carriers during turn-off of the thyristor, thereby improving the controllable current capability of the thyristor.