Abstract: An amplifying-gate thyristor having an increased integrated circuit includes a main thyristor and an amplifying thyristor. The amplifying thyristor is of the gate turnoff-type. The main thyristor and the amplifying thyristor are such that the amplifying thyristor remains in the conductive state while the main thyristor is conductive. A control circuit turns off the amplifying thyristor when the current through the main thyristor is approximately its hold current.

Abstract: In a bidirectional surge protection device formed on a semiconductor substrate, buried layers, which have the same conduction type as and are higher in impurity concentration than the semiconductor substrate, are formed on the entire surfaces of the device regions provided on both surfaces of the semiconductor substrate or formed under emitter-push restraining layers alone, wherein injection of minority carriers from a surface opposite to the surface on which the device operates is restrained to lower a holding current. As a result, the bidirectional surge protection device easily becomes OFF once it becomes ON.

Abstract: The present invention, generally speaking, provides an apparatus and method whereby the current flow through an RF power transistor may be monitored without the use of any external parts. More particularly, in accordance with one embodiment of the invention, an RF power transistor includes a silicon die, a pair of interdigitated electrodes formed on the silicon die, each having a multiplicity of parallel electrode fingers and at least one bond pad. Regions of a first type of diffusion are formed beneath electrode fingers of one electrode of the pair of interdigitated electrodes, and regions of a second type of diffusion are formed beneath electrode fingers of another electrode of the pair of interdigitated electrodes. One electrode has multiple electrode fingers and multiple resistors formed on the silicon die, at least one resistor connected in series with each one of the electrode fingers.

Abstract: A semiconductor thyristor has multiple different semiconductor layers with regions arranged in predetermined configurations to cause a plasma of carriers to flow in an expanding volume over a finite time to reach a full conduction condition, after the thyristor is switched into a conductive condition. A smooth current or connectivity transition occurs between a nonconductive state and a conductive state, thereby eliminating the typical, more instantaneous and discontinuous on-switching conductivity transitions. The finite and increased time to reach the full conduction inherently reduces the di/dt effect created by switching the thyristor. The reduced di/dt substantially reduces the radiated and conductive interference signals generated by switching the thyristor. The growth in the size of the plasma is controlled using configurations of the semiconductor structure and doping profiles within the semiconductor layers.

Abstract: An amplifying-gate thyristor having an increased integrated circuit includes a main thyristor and an amplifying thyristor. The amplifying thyristor is of the gate turnoff-type. The main tbyristor and the amplifying thyristor are such that the amplifying thyristor remains in the conductive state while the main thyristor is conductive. A control circuit turns off the amplifying thyristor when the current through the main thyristor is approximately its hold current.

Abstract: Disclosed are devices having emitters having resistive emitter diffusion sections are in a radial pattern. Such devices include vertical PNP power devices. The radial pattern of holes defines resistive emitter diffusion sections between adjacent holes. The resistive emitter diffusion sections result in a lower emitter ballast resistance due to the higher emitter sheet resistance of PNP devices. This allows all the periphery of the emitter to be active, not just two sides. The device has improved emitter ballast resistance while at the same time remaining efficient with low saturation resistance.

Abstract: A power semiconductor component which can be turned off by gate control and whose semiconductor body has a plurality of unit cells arranged side by side which are comprised of a p-emitter region (1) adjacent to the anode, an adjoining lightly doped n-base region (2), followed by a p-base region (3) and an n-emitter region (4) embedded therein and which unit cells form a thyristor structure. At least one p-region (5) is embedded in the n-emitter region (4) of the unit cells, with the p-region forming a ballast resistor and being provided with two ohmic contacts, one of which forms the outer cathode metallization (K), which has no contact with the n-emitter region (4), and the other of which is a floating contact (K') which simultaneously contacts the n-emitter region (4) ohmically.

Abstract: An insulated gate semiconductor device (10) is fabricated by providing at least one ballast resistor (40) having a sheet resistance of at least one square. The ballast resistor (40) is formed in the emitter region (17) between two adjacent portions of the base region (26) at the top surface of the semiconductor body in which the device (10) is fabricated. The ballast resistor (40) improves the latch resistance of the device (10) in overload conditions.

Abstract: An integrated semiconductor device having a thyristor includes outer npn-transistors, outer pnp-transistors, and an inner npn-transistor. The outer pnp-transistors and the inner npn-transistor are interconnected so as to form a thyristor to allow the inner transistor to be biased into conduction. Furthermore, a current flow takes place via the outer npn-transistors and the inner npn-transistor. The integrated semiconductor device having a thyristor minimizes interference produced in neighboring components.

Abstract: There is disclosed an insulated gate bipolar transistor which includes a p type semiconductor region (11) formed in a surface of an n.sup.- semiconductor layer (3) by double diffusion in corresponding relation to a p type base region (4) of an IGBT cell adjacent thereto, and an emitter electrode (9) formed on and connected to the p type semiconductor region (11) through a contact hole (CH.sub.P) having a width (W.sub.ch2) which is greater than a width (W.sub.ch1) of a contact hole (CH.sub.1), thereby preventing device breakdown due to latch-up by the operation of a parasitic thyristor during an ON state and during an ON-state to OFF-state transition even if main and control electrodes in an active region are reduced in size.

Abstract: A finger-emitter power transistor including a substrate suitable for operating as the collector of the power transistor, an epitaxial layer superimposed over the substrate (and providing a base region for the transistor), and at least one buried emitter region (for each finger of the device) below the surface of the epitaxial layer. Each buried emitter region is provided with at least one connection area to an emitter surface metallization. The connection areas between the emitter regions and their emitter surface metallization are made in various widths to provide a ballast resistance of an adequate value.

Abstract: A vertical type surge protection device for absorbing surges of either polarity has a second region forming a first pn junction with a first region, a third region forming a first minority carrier injection junction with respect to the second region, a fourth region forming a second pn junction with the first region and a fifth region forming a second minority carrier injection junction with the fourth region. When the absolute value of a surge voltage applied across the device exceeds the breakdown voltage, either the one of the first and second pn junctions that is reverse biased owing to the surge polarity breaks down or punch-through occurs between the first and third regions or between the first and fifth regions, whereafter breakover ensues as a result of positive feedback.

Abstract: A PNPN semiconductor device has an inner P-type region which includes at least one ridge which extends into its outer N-type region and terminates short of the outer boundary of the outer N-type region, the inner P-type region includes a formation which is substantially level with the outer boundary of the outer N-type region, and the device includes a terminal which contacts the outer N-type region and the formation of the inner P-type region.An alternative structure of the PNPN semiconductor device has an inner P-type region having at least one elongate sub-region, of higher conductivity than the remainder of the inner P-type region, lying along the junction between the inner P-type region and the outer N-type region, the formation which is substantially level with the outer boundary of the outer N-type region, and the terminal which contacts the formation and the outer N-type region.

Abstract: An emitter of a thyristor is divided into a plurality of emitter regions. An electrode is provided next to each of these regions, and a turn-off current path proceeds via this electrode from the base adjoining the emitter region over a first field effect transistor to a main terminal of the thyristor. Every emitter region is also connected to this main terminal via a second field effect transistor which is integrated into the semiconductor body of the thyristor, or is manufactured in thin-film technology.

Abstract: A bidirectional two-terminal ungated thyristor (9) having two wide-base portions (25, 27). The bidirectional two-terminal ungated thyristor (9) has a first semiconductor device having a first narrow-base portion (28) in series with a first wide-base portion (25), and a second semiconductor device having a second narrow-base portion (26) in series with a second wide-base portion (27). A width of the first wide base portion (25) and a width of the second wide base portion (27) are decreased to decrease a total base width. The first and second wide-base portions (25, 27) having a decreased width produce a low forward voltage drop across the bidirectional two-terminal ungated thyristor (9); thus, improving a power dissipation capability of the bidirectional two-terminal ungated thyristor (9).