Abstract: A power semiconductor module is presented in which terminal elements are press-fitted into openings in a plastic housing. This measure improves the reliability of the internal bonds between the substrate and the terminal element since there is no longer a risk of the terminal elements loosening in the plastic housing.

Abstract: A compression assembled semiconductor package for housing a power semiconductor die which includes two major pole pieces in intimate electrical contact with respective major electrodes of a power semiconductor die. The package includes a plastic molded insulation ring disposed around the power semiconductor die. The pole pieces are secured to respective ends of the plastic molded insulation ring. One of the pole pieces may include an annular flange that penetrates the plastic molded insulation ring from an interior wall thereof and is embedded in its body. An annular flange may also be embedded in the plastic molded insulation ring and connected to an annular rib of a pole piece by a circular connector.

Abstract: This is a semiconductor power module provided with: a ceramic substrate; a metallic plate bonded to a surface of this substrate; a cylindrical metallic flange which is hermetically bonded to a surface of substrate or the metallic plate; a ceramic housing for hermetically sealing an opening of the metallic flange; and at least one or more semiconductor chips soldered to the metallic plate. The metallic flange is made of metal with a low thermal expansion coefficient. A hermetically sealed container is created by welding the metallic flange, the ceramic substrate and the housing with silver brazing. Moreover, external collector, emitter and gate electrodes are bonded on the housing by using the silver brazing. The collector, emitter and gate conductive pillars are respectively connected to the external collector, emitter and gate electrodes with calking. Thus, this hermetically sealed container is strong in mechanical strength and high in explosion-proof durability and excellent in moisture resistance.

Abstract: A plurality of semiconductor chips is each arranged over a first conductor. Each of semiconductor chips has a first main electrode, a second main electrode and a control electrode. A second conductor is electrically connected to the second main electrode and has columns each having an upper surface arranged over each of the semiconductor chips and equal to the number of the semiconductor chips. A circuit board has openings penetrated by the columns and equal to the number of the semiconductor chips and has a first insulating film, a third conductive film arranged on a back surface of the first insulating film and electrically connected to the second conductor, and a fourth conductive film arranged on a surface of the first insulating film and electrically connected to the control electrode.

Abstract: A compression assembled semiconductor package for housing a power semiconductor die which includes two major pole pieces in intimate electrical contact with respective major electrodes of a power semiconductor die. The package includes a plastic molded insulation ring disposed around the power semiconductor die. The pole pieces are secured to respective ends of the plastic molded insulation ring. One of the pole pieces may include an annular flange that penetrates the plastic molded insulation ring from an interior wall thereof and is embedded in its body. The annular flange preferably comprises a projection having a squared tab and circular distal end that is received by a receiving groove having a notch (to receive the squared tab) and a cavity (to receive the distal end).

Abstract: A base body is provided, on which a first sealing ring and a second sealing ring are disposed. A substrate is disposed on the sealing rings in such a way that a cavity is formed between the first sealing ring, the second sealing ring, the base body and the substrate. An etching substance can be introduced into the cavity in order to etch clear a conductive layer that has been applied to the substrate. When a conductive layer that has been applied to the substrate back surface has been uncovered, an electrolyte can be introduced into the cavity, making contact with the conductive layer and therefore the substrate back surface.

Abstract: In one embodiment, an integrated circuit includes a heat generating structure within a dielectric region and one or more substantially horizontally arranged heat dissipation layers within the dielectric region. Each heat dissipation layer includes electrically inactive thermally conductive structures, at least two such structures in at least one such layer being substantially horizontally connected and thermally coupled to one another within the layer. The electrically inactive thermally conductive structures cooperate to facilitate dissipation of heat from the heat generating structure. In another embodiment, an integrated circuit includes one or more heat generating structures within a dielectric region and electrically inactive thermal posts formed at least partially within the dielectric region. At least one such post is substantially horizontally connected and thermally coupled to another such post.

Abstract: In accordance with a press contact type semiconductor device, a metallic body having macroscopic vacancies inside is arranged between a main electrode of the semiconductor device and a main electrode plate, or between an intermediate electrode plate arranged on a respective main plane of the semiconductor element and a main electrode plate.

Abstract: A semiconductor device includes an electronic circuit, a metal guard ring surrounding the electronic circuit, and a passivation layer covering the electronic circuit and guard ring. The passivation layer has a slot extending from the surface of the device down to the guard ring. The slot prevents cracks that may form in the passivation layer at the edges of the device from propagating to the area inside the guard ring. Locating the slot over the guard ring enables the size of the device to be reduced, and enables the guard ring to keep moisture and contaminants that enter the slot from reaching lower layers of the device.

Abstract: The present invention relates to power semiconductor devices and particularly to a power semiconductor device which contains a plurality of power semiconductor elements, and an object of the invention is to provide a power semiconductor device which is capable of reducing differences in impedance caused by differences in length among wire interconnections, facilitating the electric connection between the main circuit terminals and the outside, and lightening restrictions on the number and layout of the power semiconductor elements installed.

Abstract: A TRIAC which is one species of chip-type semiconductors includes an element body made of silicon, electrodes provided on one face of the element body, a molybdenum plate provided on one of the electrodes by an alloy plate made of aluminum and silicon, a molybdenum plate provided on the other face of the element body by a similar alloy plate, and nickel layers provided on connection faces of the molybdenum plates to outer electrode plates, so that the electrode and molybdenum plate are firmly connected without conventional high-temperature solder which includes a great amount of lead, and that the alloy plate never melt even when newly developed low-temperature institute is employed, and that the operation of the molybdenum plates is sufficiently realized.

Abstract: A compression assembled semiconductor package for housing a power semiconductor die which includes two major pole pieces in intimate electrical contact with respective major electrodes of a power semiconductor die. The package includes a plastic molded insulation ring disposed around the power semiconductor die. The pole pieces are secured to respective ends of the plastic molded insulation ring. One of the pole pieces may include an annular flange that penetrates the plastic molded insulation ring from an interior wall thereof and is embedded in its body. An annular flange may also be embedded in the plastic molded insulation ring and connected to an annular rib of a pole piece by a circular connector.

Abstract: A turn-off high power semiconductor device with the inner pnpn-layer structure of a Gate-Commutated Thyristor and a first gate on the cathode side has an additional second gate on the anode side, said second gate contacting the n-doped base layer and having a second gate contact. A second gate lead which is of rotationally symmetrical design and is disposed concentrically with respect to the anode contact is in contact with said second gate contact. Said second gate lead is brought out of the component and electrically insulated from the anode contact.

Abstract: A compound semiconductor device is formed having a plurality of FETs exhibiting the same electrode ratio of a difference between a surface area of the active region and the combined overlapping surface area of the source and drain ohmic electrodes to the combined overlapping surface area of the source and drain ohmic electrodes. As such, precise control of a threshold voltage of the FETs is achieved. The compound semiconductor device is also formed so as to include a plurality of resistors having the same ratio of a difference between a surface area of the resistivity region and the combined overlapping surface area of the pair electrodes to the combined overlapping surface area of the pair electrodes. In this manner, a resistivity of the resistor is precisely controlled.

Abstract: In accordance with a press contact type semiconductor device, a metallic body having macroscopic vacancies inside is arranged between a main electrode of the semiconductor device and a main electrode plate, or between an intermediate electrode plate arranged on a respective main plane of the semiconductor element and a main electrode plate.

Abstract: A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.

Abstract: A first cathode flange (14) provided with branch-like protrusions (14d) extending towards substantially its outer periphery and a gate flange (15) provided with branch-like protrusions (15c) extending towards substantially its outer periphery are connected to a cathode electrode (7a) and a gate electrode (7b), respectively, formed on one surface of a gate drive substrate (7). With this structure, a gate commutated turn-off semiconductor device which eliminates the necessity of a gate spacer and a cathode spacer and allows reduction in time and cost required for manufacture can be achieved.

Abstract: This invention relates to a pressure-contact type semiconductor device (1) having a ring-shaped gate terminal, and aims at overcoming such a technical problem that a gate current is not uniformly supplied to a semiconductor substrate (4) due to a connection structure for the device (1) and an external gate driver (2). For this purpose, a ring-shaped gate terminal (10) is structured as a resistor whose resistivity is at least 0.1 m&OHgr;·cm in the present invention. Thus, a voltage drop by the aforementioned resistor enlarges in a concentrated part of the gate current, and it follows that the gate current is shunted to another non-concentrated part. The present invention is utilizable as a high-power element in a power applied device.

Abstract: A semiconductor apparatus includes a plurality of semiconductor units and a common gate liner having silicon chip resistors at portions corresponding to the semiconductor units. Each unit includes a semiconductor chip, a collector base plate fixed to the chip, an insulative positioning guide, an emitter contact terminal, and a contact probe having two distal contact ends. The positioning guide positions the emitter contact terminal on the emitter electrode and the contact probe on a gate pad. The semiconductor units are collectively held by the gate liner such that the contact probes press the respective silicon chip resistors and the respective gate pads. The individual positioning guide prevents dislocation of the contact probe and the gate pad. The semiconductor apparatus simplifies the gate wiring and improves the precise positioning of the constituent elements and the reliability of the apparatus. The package size is reduced as well.

Abstract: A semiconductor device including (a) a base plate, (b) an insulation substrate including of an insulator plate with a front electrode and a back electrode bonded thereon and fixed onto the base plate by the back electrode, (c) a semiconductor element fastened onto the insulation substrate by the front electrode, (d) an insulating cover covering the semiconductor element, and (e) electrodes that are led from the semiconductor element to the outside of the insulating cover. The back electrode is larger than the insulator plate, and the base plate has a through hole that is smaller than the back electrode and larger than the insulator plate. The insulation substrate is positioned in the through hole and is fastened onto the back surface of the base plate by the periphery of the back electrode. The insulation substrate can make direct contact with a heat sink without the base plate intervening therebetween, and thereby thermal resistance between the semiconductor element and the heat sink is decreased.

Abstract: A power semiconductor module, a metal terminal for the power semiconductor module, and methods of fabricating a power semiconductor module and the metal terminal are disclosed. In the power semiconductor module, the metal terminal improves the adhesive strength between the metal terminal and a substrate of the module by increasing the surface area of the metal terminal that contacts an adhesive. A hole and a protrusion formed in an attachment plate of the terminal provide more surface area contacting the adhesive, thereby increasing the adhesive strength between the metal terminal and a metal substrate.

Abstract: In a GCT device which controls large current at the operating frequency of 1 kHz or more, a ring-shaped gate terminal (10) is made of a magnetic material with the maximum permeability of 15,000 or less in the CGS Gaussian system of units. Further, in the outer end portion of an outer plane portion (10O) of the ring-shaped gate terminal (10), a plurality of slits extending diametrically are provided along the circumference to be coupled to mounting holes (10b).

Abstract: A plug structure capable of directly coupling to a packageless bonding pad without having to go through a third conductive medium. The plug structure includes several plugs on a base substrate, such as a printed circuit board or a carrier. A solder is disposed on the plug surface in which the plug can be a cylinder or mushroom-like shape and the solder can be a film or a ball.

Abstract: A CMOS structure having a silicon dioxide outer ring around the sense region. The CMOS sense structure has a substrate, a n− region, a n+ region, an isolation region, a field implant region and a silicon dioxide outer ring region. The n− region is formed in the substrate, and the n+ region is formed within the n− region. The isolation region is formed in the substrate next to the edge of the n− region. The field implant region is formed under the isolation region. The silicon dioxide outer ring region is formed over the n− region, a portion of the isolation region and a portion of the n+ region. The silicon dioxide outer ring can prevent surface leakage that is caused by etching and lengthening the distance from the n− region to the field implant region so that edge junction leakage is reduced.

Abstract: A compression bonded type semiconductor device including a semiconductor substrate having a top surface and a bottom surface a gate electrode and a cathode electrode formed on the top surface of said substrate, and an anode electrode formed on the bottom surface of said substrate. Also included is an insulating cylinder accommodating the semiconductor substrate, a ring gate electrode contacting said gate electrode, and an external gate terminal having an outer periphery projecting from a lateral side of said insulating cylinder and being rigidly attached thereto, and having an inner periphery contacting said ring gate electrode.

Abstract: A connecting device for power semiconductor modules with compensation for mechanical stresses includes a sleeve connected to a substrate and having a region with a given very small diameter. A wire pin is provided for insertion into the region of the sleeve during operation to form an electrical connection for a board. The wire pin has a diameter greater than the given diameter for clamping the wire pin upon insertion in the region. Axial freedom of movement of the wire pin in the sleeve makes it possible to avoid mechanical stresses resulting from different material characteristics when a temperature change takes place.

Abstract: The present invention relates to a power transistor module for radio frequency applications, particularly for use in an amplifier stage in a radio base station or in a ground transmitter for TV or radio, wherein said power transistor module comprises a support plate, a power transistor chip arranged thereon, outer electrical connections projecting from the module for external connection and inner electrical connections connected between said transistor chip and said outer connections, at least one of said inner electrical connections comprising a first conductor pattern arranged on a flexible foil. The invention further comprises a power amplifier comprising said module, a method in the fabrication of said module, a method in the fabrication of a power amplifier, where said module is electrically connected to a circuit board mounted at a heat sink and to be mounted at said heat sink, and finally to a power amplifier manufactured according to the method.

Abstract: A semiconductor device including (a) a base plate, (b) an insulation substrate including of an insulator plate with a front electrode and a back electrode bonded thereon and fixed onto the base plate by the back electrode, (c) a semiconductor element fastened onto the insulation substrate by the front electrode, (d) an insulating cover covering the semiconductor element, and (e) electrodes that are led from the semiconductor element to the outside of the insulating cover. The back electrode is larger than the insulator plate, and the base plate has a through hole that is smaller than the back electrode and larger than the insulator plate. The insulation substrate is positioned in the through hole and is fastened onto the back surface of the base plate by the periphery of the back electrode. The insulation substrate can make direct contact with a heat sink without the base plate intervening therebetween, and thereby thermal resistance between the semiconductor element and the heat sink is decreased.

Abstract: Socketable balls are mounted to a BGA package by first placing the balls into pockets or holes of a tray that are sized such that when the balls are inserted, an upper portion of the ball protrudes above a planar surface of the tray. A layer of a polymer material is then applied over the balls and a top area of each of the balls is exposed, and plated with solder. During the plating step the polymer provides a solder-tight seal against each of the balls such that, except for the top area, the rest of the surface area of the balls remains solder-free. The solder-plated top area of each of the balls is then bonded to the corresponding plurality of lands of the package by reflowing the solder to establish electrical contact therebetween.

Abstract: A double circular gate conductor 9 comprises a first circular gate conductor 7 connected to a gate electrode 2a, a second circular gate conductor 8, and a connecting conductor which connects the first circular gate conductor 7 and the second circular gate conductor 8, and is configured so as to equalize the voltage drop due to self-inductance or mutual inductance between the first circular gate conductor 7, second circular gate conductor 8 and cathode post electrode 4. In this manner it is possible to guarantee more or less uniform parallel inductance over the surface of the element.

Abstract: A pressure assembled power module is provided with first and second die, the first and second die being stacked atop one another and sandwiched between first and second conductive sheets, where the die are separated by a relatively flat central conductive lead. Integral to the central conductive lead are spring elements which bias the die against both the conductive sheets and the central conductive lead. Consequently, electrical and thermal interconnections are achieved between semiconductor devices and between the semiconductor devices and a heat sink or substrate.

Abstract: A power semiconductor component includes a semiconductor body having a beed peripheral surface, a cathode electrode and an anode electrode. A materially joined connection between at least the anode electrode and the semiconductor body is not produced by alloying. The anode electrode has a diameter being greater than the cathode electrode and smaller than the semiconductor body.

Abstract: A multichip press-contact type semiconductor device including a plurality of semiconductor chips, a plurality of heat buffer plates, a conductive metal sheet, and first and second press-contact electrode plates. The heat buffer plates are disposed to correspond to the plurality of semiconductor chips. The conductive metal sheet is located on the plurality of heat buffer plates and substantially decreases the parasitic inductance by causing a short-circuit in electrode wiring connecting the semiconductor chips. The first press-contact electrode plate is located on the conductive metal sheet, and has column protrusions corresponding to the semiconductor chips on the surface facing the semiconductor chips. The second press-contact electrode plate is located on the side of the rear surface of the semiconductor chips. The first and second press-contact electrode plates hold therebetween the conductive metal sheet, the heat buffer plates, and the semiconductor chips, piled on each other.

Abstract: A semiconductor device is provided which includes a plurality of semiconductor chips each of which has a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface, and a plurality of support plates each of which is secured to the second main surface of the corresponding semiconductor chip. These semiconductor chips and support plates constitute individual semiconductor elements. The semiconductor elements are accommodated in the flat package that includes first and second common electrode plates and an insulating sleeve interposed between the common electrode plates, such that the semiconductor chip and the support plates are positioned by positioning guides. The first common electrode plate is in contact under pressure with the support plates.

Abstract: In the present invention, by virtue of heat buffer plates respectively located on the major surfaces of IGBT chips and FRD chips arranged in a single plane, the total thickness of each chip and a corresponding one of the heat can be set to a substantially predetermined value. A thickness-correcting member having elongated projections corresponding to the chips is provided on those surfaces of the heat buffer plates which is remote from the chips. A heat buffer disk plate is provided on those surfaces of the chips which are opposite to the major surfaces thereof. The thickness-correcting member, the heat buffer plates and the IGBT and FRD chips are held and simultaneously pressed between an emitter press-contact electrode plate and a collector press-contact electrode plate.

Abstract: A compression bonded type semiconductor element having a ring-shaped gate terminal in the form of an annular metal disk projecting through the side of an insulating cylinder. The ring-shaped gate terminal includes an inner circumferential planar portion which is disposed so as to be slidable on an annular ring gate electrode. The annular ring gate electrode is in contact with a gate electrode formed on a semiconductor substrate, and the ring gate electrode is pressed against the gate electrode via the ring-shaped gate terminal by an elastic body.

Abstract: The top-side (n-type) electrode and bottom-side (p-type) electrode of a Si chip with a p-n junction are pressed against a Cu cathode electrode and a Cu anode electrode via Mo plates respectively, thereby establishing electrical connection. The inner wall of a case is round and the Si chip is almost square. The top of the case is covered with ceramic, for example. A washer is a compression member. A chip frame holds the Si chip and Mo plates in compression positions and simultaneously determines their locations within the case. Specifically, the side face of the Si chip is not flush with the side face of each of the Mo plates. This enables the chip frame to make the creepage distance longer. Since the chip frame is a single chip frame without any joint, the creepage distance between the anode and cathode electrodes is defined by part of the chip frame that faces part of the surface of the Si chip and parts of the surfaces of the Mo plates sandwiching the Si chip between them.

Abstract: In a pressure contact housing for semiconductor components, the gate electrode contact ring 4 is provided with spiral recesses 5. The latter can absorb axial movements produced during the assembly of the housing, without loading the material. A good and durable electrical contact between the gate electrode and the gate electrode contact ring is obtained thereby.

Abstract: A press pack power semiconductor device incorporates a number of semiconductor elements. The power semiconductor device has a first insulating frame surrounding each of the semiconductor elements and having a lattice for positioning the semiconductor elements. First and second hard metal electrode plates are provided on the respective sides of each semiconductor element. A first electrode member is in contact with the first hard metal electrode plate. A second insulating frame, having a lattice for positioning the second hard metal electrode plate, is laid on the first insulating frame. A second electrode member is provided. This second electrode member has a lattice-shaped groove in which a lattice-shaped frame portion of the second insulating frame is fitted for positioning.

Abstract: IGBT chips and FRD chips are arranged on the same plane so as to be press-contacted by an emitter press-contact electrode plate and a collector press-contact electrode plate at the same time. The FRD chips are arranged at a central portion, and the IGBT chips are arranged at the peripheral portion of the FRD chips. A resin substrate having an opening in its contact portion between a main surface of each of said chip and the emitter press-contact electrode plate is provided between both press-contact electrode plates. Gate press-contact electrodes are formed on the resin substrate to be electrically connected to a gate electrode of each of the IGBT chips. Also, gate wires are fixed to the resin substrate to supply a control signal for controlling the IGBT chips to the gate electrode of the IGBT chips from the gate wires through the gate press-contact electrode.

Abstract: A power semiconductor module is specified in which at least one semiconductor chip, which is fitted on a baseplate, is made contact with by a respective contact plunger. The position of the contact plungers can be set individually in a manner corresponding to a distance between the semiconductor chips and a main connection which accommodates the contact plungers. The contact plungers are either subjected to pressure by means of a spring or fixed by means of a solder layer.

Abstract: In the case of a controllable power semiconductor component, which comprises at least one planar, essentially rectangular power semiconductor chip (13), which power semiconductor chip (13) has on its top side a large-area metallization layer (14) for the large-area electrical connection to a metal mating element (17, 19), and also a separate small-area connection region for the gate connection in the form of a gate pad (16), a simplified form of the metal mating element (17, 19) and adjustment thereof are achieved by virtue of the fact that the gate pad (16) is arranged in a corner of the power semiconductor chip (13).

Abstract: An alloy-free pressure contact type semiconductor device maintains a high reliability during transportation even without a pressure contact tool such as a simplified stack and therefore does not require a high transportation cost. Through holes (H1) and (H2) each having a circular cross section are formed in distortion buffer plates (21A) and (21K) at the center. A first and a second bottomed holes (i.e., recesses) (N1) and (N2) are formed in an anode electrode plate (41A) and a cathode electrode plate (41K). From the through hole (H1) up to the first bottomed hole (N1), a pressure contact pin (9) biased by a coil spring (8) is disposed. From the through hole (H2) down to the second bottomed hole (N2), a fixing pin (90) is disposed. Without applying external pressure upon the device, it is possible to prevent displacement of the first and the second distortion buffer plates due to vibration or impact during transportation and damage to a semiconductor body.

Abstract: An insulated gate type semiconductor device has a gate electrode which controls current flow between two regions of the same conductivity type in a semiconductor substrate. A main electrode has a first portion contacting a first one of the two regions, a second portion extending above the gate electrode and a third portion providing a raised external contact surface to contact an external electrode. The gate electrode is insulated above and below by insulating films. To prevent damage to the gate electrode and the lower insulating films due to the pressure of the external electrode, there is a supporting insulating layer on the surface of the substrate underlying the contact portion of the main electrode and having a thickness substantially greater than the thickness of the insulating film below the gate electrode and the contact surface is more remote from the substrate than the second portion of said main electrode.

Abstract: Provided is a press contact type semiconductor device which improves the shape of an insulator formed along an outer peripheral edge and a major surface of a semiconductor substrate, simplifies alignment of an anode heat compensator and a cathode heat compensator, causes no biting, causes no separation in molding, and has excellent heat dissipation. In the press contact type semiconductor device, the inner periphery of a ring-shaped insulator (22) which is formed along an edge of the overall periphery and a major surface of a semiconductor substrate (6) provided with a P-N junction in its interior comprises a tapered portion (22a) along the inner peripheral direction and a vertical portion (22b) forming a perpendicular inner peripheral diameter which is continuous to this tapered portion (22a).

Abstract: A connection structure for connecting a plurality of semiconductor switches in parallel includes a pressed contact for a semiconductor switch. The pressed contact includes a layered structure which connects a drain conductor to a plurality of drain electrodes, a source conductor to a plurality of source electrodes, a gate conductor to a plurality of gate electrodes, and an insulating film between the gate conductor and the source conductor. The gate electrodes are a plurality of resilient elastic wings which are pressed upward against the gate conductor, thereby ensuring a good electrical connection.

Abstract: A plurality of segments of small-sized IGBT devices are arranged concentrically in a plurality of rows in a pellet substrate. Each segment has an independent polysilicon gate electrode layer. A gate electrode terminal lead-out portion is provided at a central portion of the pellet substrate. A metal gate electrode layer electrically connects the polysilicon gate electrode layer of at least one of the segments of a unit, which unit is constituted by at least one of the segments arranged radially from the central portion of the pellet substrate towards a peripheral portion of the pellet substrate, to the gate electrode terminal lead-out portion. The metal gate electrode layer includes a trunk wiring portion extending radially from the gate electrode terminal lead-out portion, and a branch wiring portion extending from the trunk wiring portion in a circumferential direction of the pellet substrate and electrically connected to the polysilicon gate electrode layer of each segment.

Abstract: In order to obtain a pressure-connection type semiconductor device while preventing misregistration of a semiconductor base substrate and a thermal compensator with no penetration of an insulating/holding material and a method suitable for fabricating this device, concentric first and second steps (31c, 31a) are provided on an upper major surface of a first thermal compensator (31) from its outer periphery toward the center. A corner groove (3b) is provided along the overall periphery of an inner comer of the first step (31c), in the form of a ring. Since no insulating/holding material is provided in a contact surface between the semiconductor the substrate and the thermal compensator, the semiconductor base substrate and the thermal compensator are maintained in excellent electrical contact while no local stress is applied to the semiconductor substrate when the same is brought into pressure contact with the thermal compensator.

Abstract: A semiconductor component comprises a semiconductor body that has its underside secured on a metallic substrate and is joined at its upper side to an auxiliary member composed of a material having great thermal conductivity and which serves as a heat buffer. This auxiliary member increases the loadability of the semiconductor component with respect to additional, thermal stressing pulses.

Abstract: The gate lead for a center gate thyristor consists of a contact disk connected to the end of an elongated flexible conductive lead wire which is insulated over its major length. The lead is threaded through the central opening in a plunger which is received in a central opening in the pole piece and terminates in a contact disk which is captured against the bottom of the plunger. A compression spring is captured between the other end of the cylinder and the plunger, thereby to press the contact disk into high pressure contact with the gate electrode on the junction when the device is assembled. The opposite end of the gate lead wire is connected to a terminal which can be easily connected to the interior end of the gate pin which extends through the insulation housing of the assembly.