Light Responsive Structure Patents (Class 257/184)
  • Publication number: 20150041655
    Abstract: Optopair for use in sensors and analyzers of gases such as methane, and a fabrication method therefor is disclosed. It comprises: a) an LED, either cascaded or not, having at least one radiation emitting area, whose spectral maximum is de-tuned from the maximum absorption spectrum line of the gas absorption spectral band; and b) a Photodetector, whose responsivity spectral maximum can be either de-tuned from, or alternatively completely correspond to the maximum absorption spectrum line of the absorption spectral band of the gas. Modeling the LED emission and Photodetector responsivity spectra and minimizing the temperature sensitivity of the optopair based on the technical requirements of the optopair signal registration circuitry, once the spectral characteristics of the LED and Photodetector materials and the temperature dependencies of said spectral characteristics are determined, provides the LED de-tuned emission and Photodetector responsivity target peaks respectively.
    Type: Application
    Filed: May 2, 2014
    Publication date: February 12, 2015
    Applicant: BAH HOLDINGS LLC
    Inventors: MICHAEL TKACHUK, Sergey Suchalkin
  • Patent number: 8937298
    Abstract: A semiconductor integrated circuit has one or more integral nitride-type sensors. In one embodiment, an integral nitride-type sensor and a coplanar supplemental circuit are formed from a common silicon substrate base. In another embodiment, an integral nitride-type sensor and a supplemental circuit are integrated in a vertical orientation.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 20, 2015
    Assignee: RoseStreet Labs, LLC
    Inventor: Robert Forcier
  • Patent number: 8937342
    Abstract: A CMOS image sensor includes an active pixel structure suitable for sensing light incident from outside and converting a sensed light into an electrical signal, and an optical block structure suitable for blocking a visible light and passing a UV light to check and evaluate an electrical characteristic of the active pixel area. The UV pass filter includes first and second insulation layers comprising an insulator, and a metal layer formed between the first and second insulation layers.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: January 20, 2015
    Assignees: SK Hynix Inc., Postech Academy-Industry Foundation
    Inventors: Do Hwan Kim, Su Hwan Lim, Hae Wook Han, Young Woong Do, Won Jun Lee
  • Patent number: 8933434
    Abstract: A vertical stack including a p-doped GaN portion, a multi-quantum-well, and an n-doped GaN portion is formed on an insulator substrate. The p-doped GaN portion may be formed above, or below, the multi-quantum-well. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a top surface of the p-doped GaN portion. A selective low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material on the physically exposed surfaces of the p-doped GaN portion, thereby forming an elemental semiconductor material portion. Metallization is performed on a portion of the elemental semiconductor material portions to form an electrical contact structure that provides effective electrical contact to the p-doped GaN portion through the elemental semiconductor material portion.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Company
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Publication number: 20150008433
    Abstract: Various embodiments of a compensated photonic device structure and fabrication method thereof are described herein. In one aspect, a photonic device may include a substrate and a functional layer disposed on the substrate. The substrate may be made of a first material and the functional layer may be made of a second material that is different from the first material. The photonic device may also include a compensation region formed at an interface region between the substrate and the functional layer. The compensation region may be doped with compensation dopants such that a first carrier concentration around the interface region of function layer is reduced and a second carrier concentration in a bulk region of functional layer is reduced.
    Type: Application
    Filed: July 8, 2014
    Publication date: January 8, 2015
    Inventors: Mengyuan Huang, Liangbo Wang, Su Li, Tuo Shi, Pengfei Cai, Wang Chen, Ching-yin Hong, Dong Pan
  • Patent number: 8928105
    Abstract: A method to fabricate monolithically-integrated optoelectronic module apparatuses (100) comprising at least two series-interconnected optoelectronic components (104, 106, 108). The method includes deposition and scribing on an insulating substrate or superstate (110) of a 3-layer stack in order (a, b, c) or (c, b, a) comprising: (a) back-contact electrodes (122, 124, 126, 128), (b) semiconductive layer (130), and (c) front-contact components (152, 154, 156, 158). Via holes (153, 155, 157) are drilled so that heat of the drilling process causes a metallization at the surface of said via holes that renders conductive the semi-conductive layer's surface (132, 134, 136, 138) of said via holes, thereby establishing series-interconnecting electrical paths between optoelectronic components (104, 106, 108) by connecting first front-contact components (154, 156) to second back-contact electrodes (124, 126).
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: January 6, 2015
    Assignee: Flisom AG
    Inventors: Roger Ziltener, Roland Kern, David Bremaud, Björn Keller
  • Patent number: 8928036
    Abstract: A barrier infrared detector with absorber materials having selectable cutoff wavelengths and its method of manufacture is described. A GaInAsSb absorber layer may be grown on a GaSb substrate layer formed by mixing GaSb and InAsSb by an absorber mixing ratio. A GaAlAsSb barrier layer may then be grown on the barrier layer formed by mixing GaSb and AlSbAs by a barrier mixing ratio. The absorber mixing ratio may be selected to adjust a band gap of the absorber layer and thereby determine a cutoff wavelength for the barrier infrared detector. The absorber mixing ratio may vary along an absorber layer growth direction. Various contact layer architectures may be used. In addition, a top contact layer may be isolated into an array of elements electrically isolated as individual functional detectors that may be used in a detector array, imaging array, or focal plane array.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: January 6, 2015
    Assignee: California Institute of Technology
    Inventors: David Z. Ting, Cory J. Hill, Alexander Seibel, Sumith Y. Bandara, Sarath D. Gunapala
  • Patent number: 8916947
    Abstract: In various embodiments, a photodetector includes a semiconductor substrate and a plurality of pixel regions. Each of the plurality of pixel regions comprises an optically sensitive layer over the semiconductor substrate. A pixel circuit is formed for each of the plurality of pixel regions. Each pixel circuit includes a pinned photodiode, a charge store, and a read out circuit for each of the plurality pixel regions. The optically sensitive layer is in electrical communication with a portion of a silicon diode to form the pinned photodiode. A potential difference between two electrodes in communication with the optically sensitive layer associated with a pixel region exhibits a time-dependent bias; a biasing during a first film reset period being different from a biasing during a second integration period.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: December 23, 2014
    Assignee: InVisage Technologies, Inc.
    Inventors: Edward Hartley Sargent, Rajsapan Jain, Igor Constantin Ivanov, Michael R. Malone, Michael Charles Brading, Hui Tian, Pierre Henri Rene Della Nave, Jess Jan Young Lee
  • Publication number: 20140353713
    Abstract: A semiconductor device includes a substrate, a first insulation layer formed on the substrate in a first region, a photon absorption seed layer formed on the first insulation layer in the first region and on the substrate in a second region separate from the first region, and a photon absorption layer formed on the photon absorption seed layer in the first region. The photon absorption seed layer has a particular structure that may assist in reducing dislocation density in a region that includes a photon absorption layer.
    Type: Application
    Filed: December 27, 2013
    Publication date: December 4, 2014
    Inventors: BONGJIN KUH, KICHUL KIM, JEONGMEUNG KIM, JOONGHAN SHIN, JONGSUNG LIM, HANMEI CHOI
  • Publication number: 20140355636
    Abstract: In order to provide a highly reliable silicon-germanium semiconductor optical element of high luminous efficiency or of low power consumption that can reduce or prevent the occurrence of dislocations or crystal defects on the interface between a light emitting layer or a light absorption layer and a cladding layer, in a silicon-germanium semiconductor optical element, a germanium protective layer 11 of non-light emission is disposed between a germanium light emitting layer or the light absorption layer 10 and a cladding layer 12 disposed above a substrate. The germanium protective layer 11 has the electrical conductivity different from electrical conductivity of the germanium light emitting layer or the light absorption layer 10.
    Type: Application
    Filed: December 12, 2011
    Publication date: December 4, 2014
    Inventors: Tadashi Okumura, Shinichi Saito, Kazuki Tani, Etsuko Nomoto, Katsuya Oda
  • Patent number: 8901605
    Abstract: There is provided a semiconductor wafer including a base wafer whose surface is entirely or partially a silicon crystal plane, an inhibitor positioned on the base wafer to inhibit crystal growth and having an opening that reaches the silicon crystal plane, a first crystal layer made of SixGe1-x (0?x<1) and positioned on the silicon crystal plane that is exposed in the opening, a second crystal layer positioned on the first crystal layer and made of a III-V Group compound semiconductor that has a band gap width larger than a band gap width of the first crystal layer, and a pair of metal layers positioned on the inhibitor and the second crystal layer. The pair of the metal layers are each in contact with the first crystal layer and the second crystal layer.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: December 2, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Tomoyuki Takada, Sadanori Yamanaka, Masao Shimada, Masahiko Hata, Taro Itatani, Hiroyuki Ishii, Eiji Kume
  • Patent number: 8878267
    Abstract: A purpose of the present invention is to provide a preferable separation structure of wells when a photoelectric conversion unit and a part of a peripheral circuit unit or a pixel circuit are separately formed on separate substrates and electrically connected to each other. To this end, a solid-state imaging device includes a plurality of pixels including a photoelectric conversion unit and a amplification transistor configured to amplify a signal generated by the photoelectric conversion unit; a first substrate on which a plurality of the photoelectric conversion units are disposed; and a second substrate on which a plurality of the amplification transistors are disposed. A well of a first conductivity type provided with a source region and a drain region of the amplification transistor is separated from a well, which is disposed adjacent to the well in at least one direction, of the first conductivity type provided with the source region and the drain region of the amplification transistor.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: November 4, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Fumihiro Inui
  • Publication number: 20140319579
    Abstract: The present invention is directed to a position sensing detector made of a photodiode having a semi insulating substrate layer; a buffered layer that is formed directly atop the semi-insulating substrate layer, an absorption layer that is formed directly atop the buffered layer substrate layer, a cap layer that is formed directly atop the absorption layer, a plurality of cathode electrodes electrically coupled to the buffered layer or directly to the cap layer, and at least one anode electrode electrically coupled to a p-type region in the cap layer. The position sensing detector has a photo-response non-uniformity of less than 2% and a position detection error of less than 10 ?m across the active area.
    Type: Application
    Filed: February 17, 2014
    Publication date: October 30, 2014
    Applicant: OSI Optoelectronics
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Publication number: 20140312386
    Abstract: An optoelectronic device includes: a substrate made of a first material; a region in the substrate, the region being made of a second material different from the first material; an N-well in the region made of the second material; and a photo diode formed in the region by ion implantation. The second material for example is silicon germanium (Si1-xGex) or silicon carbide (Si1-yCy) wherein 0<x,y<1.
    Type: Application
    Filed: July 1, 2014
    Publication date: October 23, 2014
    Applicant: PIXART IMAGING INCORPORATION
    Inventors: Sen-Huang Huang, Hsin-Hui Hsu, Nien-Tse Chen
  • Publication number: 20140312303
    Abstract: The present invention discloses a photo-detector comprising: an n-type photon absorbing layer of a first energy bandgap; a middle barrier layer, an intermediate layer is a semiconductor structure; and a contact layer of a third energy bandgap, wherein the layer materials are selected such that the first energy bandgap of the photon absorbing layer is narrower than that of said middle barrier layer; wherein the material composition and thickness of said intermediate layer are selected such that the valence band of the intermediate layer lies above the valence band in the barrier layer to create an efficient trapping and transfer of minority carriers from the barrier layer to the contact layer such that a tunnel current through the barrier layer from the contact layer to the photon absorbing layer is less than a dark current in the photo-detector and the dark current from the photon-absorbing layer to said middle barrier layer is essentially diffusion limited and is due to the unimpeded flow of minority carrier
    Type: Application
    Filed: April 7, 2014
    Publication date: October 23, 2014
    Applicant: Semi Conductor Devices-An Elbit Systems-Rafael Partnership
    Inventor: Philip KLIPSTEIN
  • Patent number: 8866187
    Abstract: A photodetector structure can include a silicon substrate and a silicon layer on the silicon substrate, that can include a first portion of an optical transmission medium that further includes a silicon cross-sectional transmission face. A germanium layer can be on the silicon substrate and can include a second portion of the optical transmission medium, adjacent to the first portion can include a germanium cross-sectional transmission face butt-coupled to the silicon cross-sectional transmission face.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: October 21, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung Won Na, Pil-Kyu Kang, Seong Gu Kim, Yong Hwack Shin, Ho-Chul Ji, Jung Hyung Pyo, Kyoung Ho Ha
  • Patent number: 8866199
    Abstract: An object of the present invention is to provide a group III-V compound semiconductor photo detector comprising an absorption layer having a group III-V compound semiconductor layer containing Sb as a group V constituent element, and an n-type InP window layer, resulting in reduced dark current. The InP layer 23 grown on the absorption layer 23 contains antimony as impurity, due to the memory effect with antimony which is supplied during the growth of a GaAsSb layer of the absorption layer 21. In the group III-V compound semiconductor photo detector 11, the InP layer 23 contains antimony as impurity and is doped with silicon as n-type dopant. Although antimony impurities in the InP layer 23 generate holes, the silicon contained in the InP layer 23 compensates for the generated carriers. As a result, the second portion 23d of the InP layer 23 has sufficient n-type conductivity.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: October 21, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Takashi Ishizuka, Kei Fujii, Youichi Nagai
  • Patent number: 8860164
    Abstract: A light receiving element includes a core configured to propagate a signal light, a first semiconductor layer having a first conductivity type, the first semiconductor layer being configured to receive the signal light from the core along a first direction in which the core extends, an absorbing layer configured to absorb the signal light received by the first semiconductor layer, and a second semiconductor layer having a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Limited
    Inventor: Kazumasa Takabayashi
  • Patent number: 8859889
    Abstract: A solar cell element is disclosed. The solar cell element comprises a semiconductor substrate, a first electrode, a second electrode, a first wiring member and a second wiring member. The semiconductor substrate with a first surface and a second surface comprises a plurality of through-holes. The first electrode comprises a plurality of conduction portions and at least one first output extracting portion. The second electrode has a resistivity of less than 2.5×10-8 ?m (ohm-meter). The first wiring member comprises a first end face in a long direction thereof. The second wiring member comprises a second end face in a long direction thereof facing the first end face.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: October 14, 2014
    Assignee: KYOCERA Corporation
    Inventor: Koutarou Umeda
  • Publication number: 20140291644
    Abstract: An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary diode comprises: a light emitting or absorbing region having a diameter between about 20 and 30 microns and a height between 2.5 to 7 microns; a plurality of first terminals spaced apart and coupled to the light emitting region peripherally on a first side, each first terminal of the plurality of first terminals having a height between about 0.5 to 2 microns; and one second terminal coupled centrally to a mesa region of the light emitting region on the first side, the second terminal having a height between 1 to 8 microns.
    Type: Application
    Filed: March 24, 2014
    Publication date: October 2, 2014
    Applicant: NthDegree Technologies Worldwide Inc.
    Inventors: Mark David Lowenthal, William Johnstone Ray, Neil O. Shotton, Richard A. Blanchard, Brad Oraw
  • Publication number: 20140264437
    Abstract: A low noise infrared photo detector with a vertically integrated field effect transistor (FET) structure is formed without thermal diffusion. The FET structure includes a high sensitivity photo detector layer, a charge well layer, a transfer well layer, a charge transfer gate, and a drain electrode. In an embodiment, the photo detector layer and charge well are InGaAs and the other layers are InP layers.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Sensors Unlimited, Inc.
    Inventor: Peter Dixon
  • Patent number: 8835979
    Abstract: Using a multiple layer, varied composition barrier layer in place of the typical single layer barrier layer of an infrared photodetector results in a device with increased sensitivity and reduced dark current. A first barrier is adjacent the semiconductor contact; a second barrier layer is between the first barrier layer and the absorber layer. The barrier layers may be doped N type or P type with Beryllium, Carbon, Silicon or Tellurium. The energy bandgap is designed to facilitate minority carrier current flow in the contact region and block minority current flow outside the contact region.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: September 16, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Terence J De Lyon, Rajesh D Rajavel, Hasan Sharifi
  • Patent number: 8835906
    Abstract: A sensor includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat, where the photothermal absorber outputs an electric signal in response to incident light to be introduced into the photothermal absorber or heat to be applied to the photothermal absorber. A semiconductor wafer includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: September 16, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Masahiko Hata, Tomoyuki Takada, Sadanori Yamanaka, Taro Itatani
  • Patent number: 8835980
    Abstract: Provided is a semiconductor wafer including: a base wafer containing silicon; an inhibitor that has been formed on the base wafer, has an aperture in which a surface of the base wafer is exposed, and inhibits crystal growth; and a light-absorptive structure that has been formed inside the aperture in contact with a surface of the base wafer exposed inside the aperture, where the light-absorptive structure includes a first semiconductor and a second semiconductor.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: September 16, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Masahiko Hata, Taro Itatani
  • Patent number: 8835981
    Abstract: According to embodiments of the present invention, a solid-state image sensor has a semiconductor element substrate having a plurality of photo electric conversion elements, an interlaminar insulating film having wires, formed at a first surface of the semiconductor element substrate, a color filter having a plurality of dye films of a plurality of colors, formed at a second surface of the semiconductor element substrate, a micro lens array having a plurality of micro lenses, formed above the color filter, a plurality of inner lenses formed between the photoelectric conversion elements and the dye films, and a shroud that surrounds each of the inner lenses, formed above the second surface of the semiconductor element substrate.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Amane Oishi
  • Patent number: 8829566
    Abstract: A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of wavelengths and the second type of semiconductor to absorb light in a second range of wavelengths. A multiplication region is defined proximate to and separate from the absorption region. The multiplication region includes an intrinsic semiconductor region in which there is an electric field to multiply the electrons created in the absorption region.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: September 9, 2014
    Assignee: Intel Corporation
    Inventors: Michael T. Morse, Olufemi I. Dosunmu, Ansheng Liu, Mario J. Paniccia
  • Patent number: 8816363
    Abstract: A method of manufacturing an organic light-emitting element. A first layer is formed above a substrate, and exhibits hole injection properties. A bank material layer is formed above the first layer using a bank material. Banks are formed by patterning the bank material layer, and forming a resin film on a surface of the first layer by attaching a portion of the bank material layer to the first layer, the banks defining apertures corresponding to light-emitters, the resin material being the same as the bank material. A functional layer is formed by applying ink to the apertures that contacts the resin film. The ink contains an organic material. The functional layer includes an organic light-emitting layer. A second layer is formed above the functional layer and exhibits electron injection properties. The hole injection properties of the first layer are then degraded by applying electrical power to an element structure.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: August 26, 2014
    Assignee: Panasonic Corporation
    Inventors: Takashi Isobe, Kosuke Mishima, Kaori Akamatsu, Satoru Ohuchi
  • Patent number: 8816416
    Abstract: Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: August 26, 2014
    Assignee: Sony Corporation
    Inventor: Kiyoshi Hirata
  • Patent number: 8809105
    Abstract: A method for processing a semiconductor assembly is presented. The method includes thermally processing a semiconductor assembly in a non-oxidizing atmosphere at a pressure greater than about 10 Torr. The semiconductor assembly includes a semiconductor layer disposed on a support, and the semiconductor layer includes cadmium and sulfur.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: August 19, 2014
    Assignee: First Solar, Inc.
    Inventors: Jinbo Cao, Bastiaan Arie Korevaar
  • Patent number: 8810765
    Abstract: An electroluminescence element includes an electroluminescence substrate including a thin film transistor substrate, and a light-emitting layer provided over the thin film transistor substrate and divided by picture-element separating portions so as to correspond to unit picture elements; and a sealing substrate arranged to hermetically seal the light-emitting layer of the electroluminescence substrate. At least one of the electroluminescence substrate and the sealing substrate is a flexible substrate. Spacers are provided between the electroluminescence substrate and the sealing substrate.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: August 19, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Okabe, Hirohiko Nishiki
  • Patent number: 8809906
    Abstract: A semiconductor optical device includes a first clad layer, a second clad layer and an optical waveguide layer sandwiched between the first clad layer and the second clad layer, wherein the optical waveguide layer includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer and extending in one direction, and a third semiconductor layer covering a top surface of the second semiconductor layer, and wherein the first semiconductor layer includes an n-type region disposed on one side of the second semiconductor layer, a p-type region disposed on the other side of the second semiconductor layer, and an i-type region disposed between the n-type region and the p-type region, and wherein the second semiconductor layer has a band gap narrower than band gaps of the first semiconductor layer and the third semiconductor layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Limited
    Inventors: Lei Zhu, Shigeaki Sekiguchi, Shinsuke Tanaka, Kenichi Kawaguchi
  • Patent number: 8802484
    Abstract: A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: August 12, 2014
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Purakh Raj Verma, Guowei Zhang, Kah Wee Ang
  • Patent number: 8791542
    Abstract: According to an embodiment, a solid-state imaging device includes a photoelectric, conversion element. The photoelectric conversion element includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. In the solid-state imaging device, D2m3/L2m3×ni32/N2<D1M2/L1M2×ni22/N2 and D1m1/L1m1×ni12/N1<D1m2/L1m2×ni22/N1 are established.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Toriyama, Koichi Kokubun, Hiroki Sasaki
  • Publication number: 20140203325
    Abstract: A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si.
    Type: Application
    Filed: January 22, 2013
    Publication date: July 24, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Purakh Raj VERMA, Guowei ZHANG, Kah Wee ANG
  • Publication number: 20140197453
    Abstract: Embodiments of an exemplary image sensor structure of the present disclosure contains at least two different layers of band gap semiconductors, where each upper layer of the different layers has a different band gap than a lower layer. For such an image sensor structure, the upper layer has a greater band gap than any layer positioned below the upper layer including the lower layer.
    Type: Application
    Filed: January 30, 2013
    Publication date: July 17, 2014
    Applicant: Broadcom Corporation
    Inventor: Ilya Blayvas
  • Publication number: 20140197425
    Abstract: Provided is a broadband photomixer technology that is a core to generate continuous frequency variable and pulsed terahertz waves. It is possible to enhance light absorptance by applying the transmittance characteristic of a 2D light crystal structure and it is possible to increase the generation efficiency of terahertz waves accordingly. Moreover, it is possible to implement a wide area array type terahertz photomixer by applying an interdigit structure and spatially properly arranging a light crystal structure having various cycles. Accordingly, it is possible to solve difficulty in thermal characteristic and light alignment by mitigating the high light density of a light absorption unit and low photoelectric conversion efficiency is drastically improved. In addition, the radiation pattern of terahertz waves may be electrically controlled through the present invention.
    Type: Application
    Filed: January 14, 2014
    Publication date: July 17, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Kiwon MOON, Han-Cheol RYU, Sang-Pil HAN, Kyung Hyun PARK
  • Patent number: 8779467
    Abstract: To provide a light emitting device high in reliability with a pixel portion having high definition with a large screen. According to a light emitting device of the present invention, on an insulator (24) provided between pixel electrodes. an auxiliary electrode (21) made of a metal film is formed, whereby a conductive layer (20) made of a transparent conductive film in contact with the auxiliary electrode can be made low in resistance and thin. Also, the auxiliary electrode (21) is used to achieve connection with an electrode on a lower layer, whereby the electrode can be led out with the transparent conductive film formed on an EL layer. Further, a protective film (32) made of a film containing hydrogen and a silicon nitride film which are laminated is formed, whereby high reliability can be achieved.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masaaki Hiroki, Masakazu Murakami, Hideaki Kuwabara
  • Patent number: 8772623
    Abstract: Low bandgap, monolithic, multi-bandgap, optoelectronic devices (10), including PV converters, photodetectors, and LED's, have lattice-matched (LM), double-heterostructure (DH), low-bandgap GaInAs(P) subcells (22, 24) including those that are lattice-mismatched (LMM) to InP, grown on an InP substrate (26) by use of at least one graded lattice constant transition layer (20) of InAsP positioned somewhere between the InP substrate (26) and the LMM subcell(s) (22, 24). These devices are monofacial (10) or bifacial (80) and include monolithic, integrated, modules (MIMs) (190) with a plurality of voltage-matched subcell circuits (262, 264, 266, 270, 272) as well as other variations and embodiments.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: July 8, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Mark W. Wanlass, Jeffrey J. Carapella
  • Patent number: 8766391
    Abstract: Photodetector arrays, image sensors, and other apparatus are disclosed. In one aspect, an apparatus may include a surface to receive light, a plurality of photosensitive regions disposed within a substrate, and a material coupled between the surface and the plurality of photosensitive regions. The material may receive the light. At least some of the light may free electrons in the material. The apparatus may also include a plurality of discrete electron repulsive elements. The discrete electron repulsive elements may be coupled between the surface and the material. Each of the discrete electron repulsive elements may correspond to a different photosensitive region. Each of the discrete electron repulsive elements may repel electrons in the material toward a corresponding photosensitive region. Other apparatus are also disclosed, as are methods of use, methods of fabrication, and systems incorporating such apparatus.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: July 1, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventor: Hidetoshi Nozaki
  • Publication number: 20140175510
    Abstract: Provided is a germanium photodetector having a germanium epitaxial layer formed without using a buffer layer and a method of fabricating the same. In the method, an amorphous germanium layer is formed on a substrate. The amorphous germanium layer is heated up to a high temperature to form a crystallized germanium layer. A germanium epitaxial layer is formed on the crystallized germanium layer.
    Type: Application
    Filed: March 1, 2014
    Publication date: June 26, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Dongwoo SUH, Sang Hoon KIM, Gyungock KIM, JiHo JOO
  • Patent number: 8759873
    Abstract: A bispectral detector comprising upper and lower semiconductor layers of a first conductivity type in order to absorb a first and a second electromagnetic spectrum, separated by an intermediate layer that forms a barrier; semiconductor zones of a second conductivity type implanted in upper layer and lower layer and each implanted at least partially in the bottom of an opening that passes through upper layer and intermediate layer; and conductor elements connected to semiconductor zones. At least that part of each opening that passes through upper layer is separated from the latter by a semiconductor cap layer: whereof the concentration of dopants of the second conductivity type is greater than 1017 cm?3; and whereof the thickness is chosen as a function of said concentration so that it exceeds the minority carrier diffusion length in the cap layer.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: June 24, 2014
    Assignee: Commissariat a l'Energie Atomique et Aux Energies Alternatives
    Inventors: Olivier Gravrand, Jacques Baylet
  • Publication number: 20140167107
    Abstract: A semiconductor light receiving device includes a substrate having an incident surface receiving light incident on the semiconductor light receiving device and a principal surface opposite to the incident surface; a first semiconductor layer disposed on the principal surface of the substrate, the first semiconductor layer defining one of a cathode region and an anode region; a light absorbing region disposed on the first semiconductor layer; and a second semiconductor layer disposed on the light absorbing region, the second semiconductor layer defining the other of the cathode region and the anode region and forming a junction with the light absorbing region. The light absorbing region includes a semiconductor layer having a conductivity type opposite to the conductivity type of the first semiconductor layer. The semiconductor layer of the light absorbing region forms a p-n junction with the first semiconductor layer.
    Type: Application
    Filed: November 5, 2013
    Publication date: June 19, 2014
    Applicants: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshihiro YONEDA, Takuya FUJII, Tooru UCHIDA
  • Patent number: 8754445
    Abstract: A layer in which the potential level difference normally unrequired for device operation is generated is positively inserted in a device structure. The potential level difference has such a function that even if a semiconductor having a small bandgap is exposed on a mesa side surface, a potential drop amount of the portion is suppressed, and a leakage current inconvenient for device operation can be reduced. This effect can be commonly obtained for a heterostructure bipolar transistor, a photodiode, an electroabsorption modulator, and so on. In the photodiode, since the leakage current is alleviated, the device size can be reduced, so that in addition to improvement of operating speed with a reduction in series resistance, it is advantageous that the device can be densely disposed in an array.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: June 17, 2014
    Assignees: NTT Electronics Corporation, Nippon Telegraph and Telephone Corporation
    Inventors: Tadao Ishibashi, Seigo Ando, Yoshifumi Muramoto, Toshihide Yoshimatsu, Haruki Yokoyama
  • Patent number: 8735939
    Abstract: According to one embodiment, a solid state imaging device includes a photoelectric converting portion including a semiconductor region and a semiconductor film. The semiconductor region has a first region and a second region. The first region is of a second conductivity type. The first region is provided in a semiconductor substrate. The second region is of a first conductivity type. The first conductivity type is a different conductivity type from the second conductivity type. The second region is provided on the first region. The semiconductor film is of the second conductivity type. The semiconductor film is provided on the semiconductor region. An absorption coefficient of a material of the semiconductor film to a visible light is higher than an absorption coefficient of a material of the semiconductor substrate to the visible light. A thickness of the semiconductor film is smaller than a thickness of the semiconductor region.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koichi Kokubun
  • Patent number: 8698197
    Abstract: The present invention is directed to a position sensing detector made of a photodiode having a semi insulating substrate layer; a buffered layer that is formed directly atop the semi-insulating substrate layer, an absorption layer that is formed directly atop the buffered layer substrate layer, a cap layer that is formed directly atop the absorption layer, a plurality of cathode electrodes electrically coupled to the buffered layer or directly to the cap layer, and at least one anode electrode electrically coupled to a p-type region in the cap layer. The position sensing detector has a photo-response non-uniformity of less than 2% and a position detection error of less than 10 ?m across the active area.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: April 15, 2014
    Assignee: OSI Optoelectronics, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Patent number: 8692295
    Abstract: A double heterojunction bipolar transistor on a substrate comprises a collector formed of InGaAsP, a base in contact with the collector, an emitter in contact with the base, and electrodes forming separate electrical contacts with each of the collector, base, and emitter, respectively. A device incorporates this transistor and an opto-electronic device optically coupled with the collector of the transistor to interact with light transmitted therethrough.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: April 8, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, Stephen Thomas, III
  • Patent number: 8691618
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate including a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species and form a copper indium disulfide material. The copper indium disulfide material includes a thickness of substantially copper sulfide material. The thickness of the copper sulfide material is removed to expose a surface region having a copper poor surface characterized by a copper to indium atomic ratio of less than about 0.95:1. The method subjects the copper poor surface to a metal cation species to convert the copper poor surface from an n-type semiconductor characteristic to a p-type semiconductor characteristic.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: April 8, 2014
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8680586
    Abstract: A semiconductor light emitting device including: a substrate made of GaAs; and a semiconductor layer formed on the substrate, in which part of the substrate on a side opposite to the semiconductor layer is removed by etching so that the semiconductor light emitting device has a thickness of not more than 60 ?m.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: March 25, 2014
    Assignee: ROHM Co., Ltd.
    Inventors: Tadahiro Hosomi, Kentaro Mineshita
  • Patent number: 8680574
    Abstract: A hybrid nanostructure array having a substrate and two types of nanostructures, including a set of first nanostructures extending from the substrate and a set of second nanostructures interspersed among the first nanostructures. The first and second nanostructures comprise structures having nanoscale proportions in two dimensions and being elongate in the third dimension. For example, the nanostructures can be nanotubes, nanowires, nanorods, nanocolumns, and/or nanofibers. Also disclosed is a hybrid nanoparticle array using two different types of nanoparticles that have all three dimensions in the nanoscale. The two types of nanostructures or nanoparticles can vary in composition, shape, or size.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: March 25, 2014
    Assignee: The Regents of The University of Michigan
    Inventor: Anastasios John Hart
  • Patent number: 8674406
    Abstract: A strain-balanced photodetector is provided for detecting infrared light at an extended cutoff wavelength in the range of 4.5 ?m or more. An InAsSb absorber layer has an Sb content is grown in a lattice-mismatched condition to a GaSb substrate, and a plurality of GaAs strain-compensating layers are interspersed within the absorber layer to balance the strain of the absorber layer due to the lattice mismatch. The strain-compensation layers allow the absorber to achieve a thickness exhibiting sufficient absorption efficiency while extending the cutoff wavelength beyond that possible in a lattice-matched state. Additionally, the strain-compensation layers are sufficiently thin to be substantially quantum-mechanically transparent such that they do not substantially affect the transmission efficiency of the absorber. The photodetector is preferably formed as a majority carrier filter photodetector exhibiting minimal dark current, and may be provided individually or in a focal plane array.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: March 18, 2014
    Assignee: Lockheed Martin Corp.
    Inventors: Jeffrey W. Scott, George Paloczi