Abstract: Engineered substrates having epitaxial templates for forming epitaxial semiconductor materials and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a first semiconductor material at a front surface of a donor substrate. The first semiconductor material is transferred to first handle substrate to define a first formation structure. A second formation structure is formed to further include a second semiconductor material homoepitaxial to the first formation structure. The method can further include transferring the first portion of the second formation structure to a second handle substrate such that a second portion of the second formation structure remains at the first handle substrate.

Abstract: Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.

Abstract: Field effect transistors are provided. An active region protrudes from a substrate and a gate electrode is provided on the active region. Source/drain regions are provided at both sides of the active region under the gate electrode, respectively. A width of a lower portion of the gate electrode is greater than a width of an upper portion of the gate electrode.

Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a first gate structure on the fin-shaped structure; forming a first epitaxial layer in the fin-shaped structure adjacent to the first gate structure; forming an interlayer dielectric layer on the first gate structure and the first epitaxial layer; forming an opening in the interlayer dielectric layer to expose the first epitaxial layer; forming a silicon cap on the first epitaxial layer; and forming a contact plug in the opening.

Abstract: The objective is to improve capabilities such as high-speed switching of a compound semiconductor device. Provided is a semiconductor wafer comprising a silicon wafer; an insulating film that is formed on the silicon wafer and that has an open portion reaching the silicon wafer; a Ge crystal formed in the open portion; a seed compound semiconductor crystal that is grown with the Ge crystal as a nucleus and that protrudes beyond a surface of the insulating film; and a laterally grown compound semiconductor layer that is laterally grown on the insulating film with a specified surface of the seed compound semiconductor crystal as a seed surface.

Abstract: An embodiment uses a very thin layer nanostructure (e.g., a Si or SiGe fin) as a template to grow a crystalline, non-lattice matched, epitaxial (EPI) layer. In one embodiment the volume ratio between the nanostructure and EPI layer is such that the EPI layer is thicker than the nanostructure. In some embodiments a very thin bridge layer is included between the nanostructure and EPI. An embodiment includes a CMOS device where EPI layers covering fins (or that once covered fins) are oppositely polarized from one another. An embodiment includes a CMOS device where an EPI layer covering a fin (or that once covered a fin) is oppositely polarized from a bridge layer covering a fin (or that once covered a fin). Thus, various embodiments are disclosed from transferring defects from an EPI layer to a nanostructure (that is left present or removed). Other embodiments are described herein.

Abstract: A semiconductor device containing a GaN FET has n-type doping in at least one III-N semiconductor layer of a low-defect layer and an electrical isolation layer below a barrier layer. A sheet charge carrier density of the n-type doping is 1 percent to 200 percent of a sheet charge carrier density of the two-dimensional electron gas.

Abstract: A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes epitaxially depositing a layer of rare earth oxide on the surface of the silicon substrate. The rare earth oxide being substantially crystal lattice matched to the surface of the silicon substrate. The method further includes forming an aluminum oxide layer on the rare earth oxide, the aluminum oxide being substantially crystal lattice matched to the surface of the rare earth oxide and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide layer substantially crystal lattice matched to the surface of the aluminum oxide.

Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

Abstract: A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion.

Abstract: A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions.

Abstract: Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.

Abstract: The transistor includes an underlying layer 301 formed on a substrate 300, and a first layer (including an operation layer 302) made of a nitride semiconductor formed on the underlying layer 301. The underlying layer 301 is a multilayered structure including a plurality of stacked nitride semiconductor layers. The underlying layer 301 includes a transition-metal-containing layer containing at least one of cobalt, nickel, ruthenium, osmium, rhodium, or iridium which is a transition metal.

Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

Abstract: A semiconductor device according to an exemplary embodiment comprises a substrate, a middle layer comprising a first semiconductor layer disposed on the substrate and comprising AlxGa1-xN (0?x?1) doped with a first dopant and a second semiconductor layer disposed on the first semiconductor layer and comprising undoped gallium nitride (GaN) and a drive unit disposed on the second semiconductor layer.

Abstract: There are provided a semiconductor device and a method for manufacturing the same.

Abstract: A device including a silicon substrate, a silicon germanium layer, a silicon layer, a gate stack, and silicon-containing stressors is provided. In an embodiment, the silicon germanium layer is disposed over a silicon substrate and relaxed while the silicon layer is disposed over the silicon germanium layer and un-relaxed. The silicon layer may be free from germanium. The gate stack is of an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) and disposed over the silicon layer and the silicon germanium layer. A portion of the silicon layer forms a channel region of the NMOS FET. The silicon-containing stressors are formed in recesses in the silicon layer and have a lattice constant smaller than a lattice constant of the silicon germanium layer.

Abstract: An optoelectronic semiconductor body has a substrate that includes a strained layer that is applied to the substrate in a first epitaxy step. The strained layer includes at least one recess formed vertically in the strained layer. In a second epitaxy step, a further layer applied to the strained layer. The further layer fills the at least one recess and covers the strained layer at least in some areas.

Abstract: The following layers are deposited above the upper surface of a base substrate in this order with a lattice relaxation layer therebetween: a lower barrier layer made of AlxGa1-xN (0<x?0.20), a channel layer made of GaN, and an upper barrier layer made of AlyGa1-yN (0.15?y?0.30, where x<y). A drain electrode, a source electrode, and an insulating layer are placed on the upper surface of the upper barrier layer. Furthermore, a gate electrode is placed in a position spaced with the insulating layer. A recessed structure is placed directly under the gate electrode. The channel layer includes an n-type doped second channel sub-layer and undoped first channel sub-layer deposited on the lower barrier layer in that order. The bottom of the recessed structure is within the heightwise range of the first channel sub-layer.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a Si substrate (1100); a plurality of convex structures (1200) formed on the Si substrate (1100), in which every two adjacent convex structures (1200) are separated by a cavity in a predetermined pattern, and the cavity between every two adjacent convex structures (1200) is less than 50 nm in width; a first semiconductor film (1300), in which the first semiconductor film (1300) is formed between the every two adjacent convex structures (1200) and connected with tops of the every two adjacent convex structures (1200); a buffer layer (2100) formed on the first semiconductor film (1300); and a high-mobility III-V compound semiconductor layer (2000) formed on the buffer layer (2100).

Abstract: A GaN-based semiconductor element includes a substrate, a buffer layer formed on the substrate, including an electrically conductive portion, an epitaxial layer formed on the buffer layer, and a metal structure in ohmic contact with the electrically conductive portion of the buffer layer for controlling an electric potential of the buffer layer.

Abstract: A bridge structure for use in a semiconductor device includes a semiconductor substrate and a semiconductor structure layer. The semiconductor structure layer is formed on a surface of the semiconductor substrate and a lattice difference is formed between the semiconductor structure layer and the semiconductor substrate. The semiconductor structure layer includes at least a first block, at least a second block and at least a third block, wherein the first block and the third block are bonded on the surface of the semiconductor substrate, the second block is floated over the semiconductor substrate and connected with the first block and the third block.

Abstract: The present invention provides a silicon-compatible compound junctionless field effect transistor enabled to be compatible to a bulk silicon substrate for substituting an expensive SOI substrate, to form a blocking semiconductor layer between a silicon substrate and an active layer by a semiconductor material having a specific difference of energy bandgap from that of the active layer to substitute a prior buried oxide for blocking a leakage current at an off-operation time and to form the active layer by a semiconductor layer having electron or hole mobility higher than that of silicon, and to operate perfectly as a junctionless device though the dopant concentration of the active layer is much lower than the prior junctionless device.

Abstract: A solar cell including: a silicon (Si) substrate; a buffer layer disposed on a side of the silicon substrate; a germanium (Ge) junction disposed on a side of the buffer layer opposite the silicon substrate; a first electrode electrically connected to the germanium junction; and a second electrode electrically connected to the germanium junction, wherein the buffer layer has a lattice constant that increases in a direction from the silicon substrate to the germanium junction.

Abstract: A semiconductor structure includes agate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.

Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.

Abstract: A hetero-substrate, a nitride-based semiconductor light emitting device, and a method of manufacturing the same are provided. The hetero-substrate may include a substrate including a silicon semiconductor, a buffer layer disposed on the substrate, a first semiconductor layer disposed on the buffer layer and including a nitride semiconductor, a second semiconductor layer disposed on the first semiconductor layer and including a first conductive type nitride semiconductor having a first doping concentration, and a stress control structure disposed between the first semiconductor layer and the second semiconductor layer and including at least one stress compensation layer and at least one third semiconductor layer including a first conductive type nitride semiconductor having a second doping concentration that is the same or lower than the first doping concentration.

Abstract: A method of fabricating a semiconductor device is disclosed comprising the steps of: providing a substrate having a first region, a second region and a plurality of gate electrodes which are formed on the first and second regions of the substrate; forming a mask film to expose the first region of the substrate while covering the second region of the substrate, such that the mask film has a negative lateral profile at a boundary between the first and second regions of the substrate; forming sigma trenches in the first region of the substrate by etching the first region of the substrate using the mask film and the gate electrodes as a mask; and forming an epitaxial layer in each of the sigma trenches.

Abstract: Substrate structures and methods of manufacturing the substrate structures. A substrate structure is manufactured by forming a protrusion area of a substrate under a buffer layer, and forming a semiconductor layer on the buffer layer, thereby separating the substrate from the buffer layer except in an area where the protrusion is formed. The semiconductor layer on the buffer layer not contacting the substrate has freestanding characteristics, and dislocation or cracks may be reduced and/or prevented.

Abstract: A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed.

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract: A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.

Abstract: To provide an epitaxial substrate for electronic devices, in which current flows in a lateral direction, which enables accurate measurement of the sheet resistance of HEMTs without contact, and to provide a method of efficiently producing the epitaxial substrate for electronic devices, the method characteristically includes the steps of forming a barrier layer against impurity diffusion on one surface of a high-resistance Si-single crystal substrate, forming a buffer as an insulating layer on the other surface of the high-resistance Si-single crystal substrate, producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate, and measuring resistance of the main laminate of the epitaxial substrate without contact.

Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.

Abstract: A semiconductor device includes a silicon substrate, an aluminum nitride layer which is arranged on the silicon substrate and has a region where silicon is doped thereof as an impurity, a buffer layer which is arranged on the aluminum nitride layer and has a structure where a plurality of nitride semiconductor films are laminated, and a semiconductor functional layer which is arranged on the buffer layer and made of nitride semiconductor.

Abstract: A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.

Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer formed of non-doped AlXGa1-XN (0?X<1); a second nitride semiconductor layer formed on the first nitride semiconductor layer of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y), and having a smaller lattice constant than that of the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer of a non-doped or n-type nitride semiconductor, and having a lattice constant equal to that of the first nitride semiconductor layer; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer of InWAlZGa1-W-ZN (0<W?1, 0<Z<1); a gate electrode formed in a recess structure having a bottom face which arrives at the third nitride semiconductor layer; and a source electrode and a drain electrode.

Abstract: A method of fabricating a FINFET includes the following steps. A plurality of fins is patterned in a wafer. A dummy gate is formed covering a portion of the fins which serves as a channel region. Spacers are formed on opposite sides of the dummy gate. The dummy gate is removed thus forming a trench between the spacers that exposes the fins in the channel region. A nitride material is deposited into the trench so as to cover a top and sidewalls of each of the fins in the channel region. The wafer is annealed to induce strain in the nitride material thus forming a stressed nitride film that covers and induces strain in the top and the sidewalls of each of the fins in the channel region of the device. The stressed nitride film is removed. A replacement gate is formed covering the fins in the channel region.

Abstract: A method of forming a strained silicon-on-insulator includes forming a first wafer having a compressively strained active semiconductor layer, forming a second wafer having an insulation layer formed above a bulk semiconductor layer, and bonding the compressively strained active semiconductor layer of the first wafer to the insulation layer of the second wafer.

Abstract: In some embodiments of the invention, a device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer. The third semiconductor layer is disposed between the second semiconductor layer and the light emitting layer. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the third semiconductor layer is no more than 1%. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the second semiconductor layer is at least 1%. The third semiconductor layer is at least partially relaxed.

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract: An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more.

Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric.

Abstract: There is provided a semiconductor wafer including a base wafer, an insulating layer, and a Si crystal layer in the stated order. The semiconductor wafer further includes an inhibition layer that is provided on the Si crystal layer and has an opening penetrating therethrough to reach the Si crystal layer. The inhibition layer inhibiting crystal growth of a compound semiconductor. Furthermore, a seed crystal is provided within the opening, and a compound semiconductor has a lattice match or a pseudo lattice match with the seed crystal.

Abstract: Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 E+20 arsenic atoms per cubic centimeter. The structures can be used to form metal oxide semiconductor devices.

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.

Abstract: A DBR/gallium nitride/aluminum nitride base grown on a silicon substrate includes a Distributed Bragg Reflector (DBR) positioned on the silicon substrate. The DBR is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the DBR, an inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.

Abstract: Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.

Abstract: A field effect transistor includes: a channel layer 103 containing GaN or InGaN; a first electron-supplying layer 104 disposed over the channel layer 103 and containing InxAlyGa1-x-yN (0?x<1, 0<y<1, 0<x+y<1); a first etch stop layer 105 disposed over the first electron-supplying layer 104 and containing indium aluminum nitride (InAlN); and a second electron-supplying layer 106 provided over the first etch stop layer 105 and containing InaAlbGa1-a-bN (0?a<1, 0<b<1, 0<a+b<1). A first recess 111, which extends through the second electron-supplying layer 106 and the first etch stop layer 105 and having a bottom surface constituted of a section of the first electron-supplying layer 104, is provided in the second electron-supplying layer 106 and the first etch stop layer 105. A gate electrode 109 covers the bottom surface of the first recess 111 and is disposed in the first recess 111.