With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) Patents (Class 257/190)
-
Patent number: 9040331Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.Type: GrantFiled: July 20, 2012Date of Patent: May 26, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Anthony J. Lochtefeld
-
Publication number: 20150137179Abstract: A power device disclosed herein comprises a substrate, a first semiconductor layer formed on the substrate, a second semiconductor layer formed on the first semiconductor layer and comprising a first element of group III, a third semiconductor layer formed on the second semiconductor layer and a plurality of first interlayers formed in the third semiconductor layer and comprising a second element of III group. The first element of III group and the second element of III group are the same. The second semiconductor layer and the plurality of first interlayers are doped with carbon.Type: ApplicationFiled: November 19, 2013Publication date: May 21, 2015Applicants: HUGA OPTOTECH INC., EPISTAR CORPORATIONInventors: Ya-Yu YANG, Heng-Kuang LIN
-
Publication number: 20150137180Abstract: A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.Type: ApplicationFiled: January 27, 2015Publication date: May 21, 2015Inventors: Ming-Hua Yu, Pei-Ren Jeng, Tze-Liang Lee
-
Publication number: 20150129931Abstract: A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel.Type: ApplicationFiled: March 20, 2014Publication date: May 14, 2015Applicant: SK hynix Inc.Inventor: Yun-Hyuck JI
-
Publication number: 20150129911Abstract: Tunable p-i-n diodes comprising Ge heterojunction structures are provided. Also provided are methods for making and using the tunable p-i-n diodes. Tunability is provided by adjusting the tensile strain in the p-i-n heterojunction structure, which enables the diodes to emit radiation over a range of wavelengths.Type: ApplicationFiled: November 8, 2013Publication date: May 14, 2015Applicant: Wisconsin Alumni Research FoundationInventors: Max G. Lagally, José Roberto Sánchez Pérez
-
Patent number: 9029911Abstract: Disclosed are a light emitting device, a method of manufacturing the light emitting device, a light emitting device package and a lighting system. The light emitting device includes a silicon substrate; a nitride buffer layer on the silicon substrate; and a gallium nitride epitaxial layer on the nitride buffer layer, wherein the nitride buffer layer includes a first nitride buffer layer having a first aluminum nitride layer on the silicon substrate and a first gallium nitride layer on the first aluminum nitride layer.Type: GrantFiled: July 31, 2012Date of Patent: May 12, 2015Assignee: LG Innotek Co., Ltd.Inventors: Jung Hun Jang, Jeong Sik Lee, Seung Keun Nam
-
Publication number: 20150123124Abstract: A transistor device, such as a rotated channel metal oxide/insulator field effect transistor (RC-MO(I)SFET), includes a substrate including a non-polar or semi-polar wide band gap substrate material such as an Al2O3 or a ZnO or a Group-III Nitride-based material, and a first structure disposed on a first side of the substrate comprising of AlInGaN-based and/or ZnMgO based semiconducting materials. The first structure further includes an intentional current-conducting sidewall channel or facet whereupon additional semiconductor layers, dielectric layers and electrode layers are disposed and upon which the field effect of the dielectric and electrode layers occurs thus allowing for a high density monolithic integration of a multiplicity of discrete devices on a common substrate thereby enabling a higher power density than in conventional lateral power MOSFET devices.Type: ApplicationFiled: January 6, 2015Publication date: May 7, 2015Inventors: Bunmi T. ADEKORE, James FIORENZA
-
Patent number: 9024355Abstract: Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.Type: GrantFiled: May 30, 2012Date of Patent: May 5, 2015Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn, Jeffrey W. Sleight
-
Publication number: 20150115320Abstract: Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures.Type: ApplicationFiled: October 3, 2014Publication date: April 30, 2015Inventor: Anthony J. Lochtefeld
-
Publication number: 20150115321Abstract: A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device are disclosed, where the substrate structure includes: a substrate, at least one seed layer on the substrate formed of a material including boron (B) and/or phosphorus (P), and a buffer layer on the seed layer. This substrate structure makes it possible to reduce the thickness of the buffer layer and also improve the performance characteristics of a semiconductor device formed with the substrate structure.Type: ApplicationFiled: October 9, 2014Publication date: April 30, 2015Inventors: Moon-seung YANG, Rakib Uddin MOHAMMAD, Myoung-jae LEE, Sang-moon LEE, Sung-hun LEE, Seong-ho CHO
-
Publication number: 20150108543Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow trench isolations (STI) region disposed on the side of the gate stack, wherein the STI region is within the substrate; and a source/drain (S/D) structure distributed between the gate stack and STI region, wherein the S/D structure comprises a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; and a S/D extension disposed between the substrate and strained material, wherein the S/D extension comprises a portion extending below the spacer and substantially vertical to the major surface.Type: ApplicationFiled: December 22, 2014Publication date: April 23, 2015Inventor: Ying Xiao
-
Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods
Patent number: 9012253Abstract: Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance with one embodiment of the disclosure includes forming multiple crystals carried by a support member, with the crystals having an orientation selected to facilitate formation of gallium nitride. The method can further include forming a volume of gallium nitride carried by the crystals, with the selected orientation of the crystals at least partially controlling a crystal orientation of the gallium nitride, and without bonding the gallium nitride, as a unit, to the support member. In other embodiments, the number of crystals can be increased by a process that includes annealing a region in which the crystals are present, etching the region to remove crystals having an orientation other than the selected orientation, and/or growing the crystals having the selected orientation.Type: GrantFiled: December 15, 2010Date of Patent: April 21, 2015Assignee: Micron Technology, Inc.Inventors: Anthony Lochtefeld, Hugues Marchand -
Patent number: 9012277Abstract: Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions.Type: GrantFiled: January 9, 2012Date of Patent: April 21, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Stefan Flachowsky, Ralf Illgen
-
Publication number: 20150102385Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first buffer layer, a second buffer layer, a n-type transistor structure, and a p-type transistor structure. The first buffer layer having a first germanium concentration is formed on a substrate. The second buffer layer having a second germanium concentration is formed on the substrate, the second germanium concentration being larger than the first germanium concentration. The n-type transistor structure is formed on the first buffer layer, and the p-type transistor structure is formed on the second buffer layer.Type: ApplicationFiled: October 10, 2013Publication date: April 16, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventor: KA-HING FUNG
-
Patent number: 9006785Abstract: Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material and a third layer of single-crystalline semiconductor material. In the structures, the second layer is in contact with and sandwiched between the first and third layers and the first layer is selectively doped to provide one or more doped regions in the layer.Type: GrantFiled: January 28, 2013Date of Patent: April 14, 2015Assignee: Wisconsin Alumni Research FoundationInventors: Zhenqiang Ma, Jung-Hun Seo, Max G. Lagally
-
Patent number: 9006786Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material having the first lattice constant; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and a pair of notches extending into opposite sides of the middle portion; and an isolation structure surrounding the fin structure, wherein a top surface of the isolation structure is higher than a top surface of the pair of notches.Type: GrantFiled: July 3, 2013Date of Patent: April 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu, Carlos H. Diaz, Jean-Pierre Colinge
-
Patent number: 9006083Abstract: Methods and structures for GaN on silicon-containing substrates are disclosed, comprising a texturing process to generate a rough surface containing (111) surface, which then can act as an underlayer for epitaxial GaN. LED devices are then fabricated on the GaN layer. Variations of the present invention include different orientations of silicon layer instead of (100), such as (110) or others; and other semiconductor materials instead of GaN, such as other semiconductor materials suitable for LED devices.Type: GrantFiled: February 16, 2012Date of Patent: April 14, 2015Inventor: Ananda H. Kumar
-
Publication number: 20150091057Abstract: Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both re-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: ASM IP Holding B.V.Inventors: Qi Xie, Vladimir Machkaoutsan, Jan Willem Maes
-
Patent number: 8994002Abstract: A fin field effect transistor (FinFET) device is provided. The FinFET includes a superlattice layer and a strained layer. The superlattice layer is supported by a substrate. The strained layer is disposed on the superlattice layer and provides a gate channel. The gate channel is stressed by the superlattice layer. In an embodiment, the superlattice layer is formed by stacking different silicon germanium alloys or stacking other III-V semiconductor materials.Type: GrantFiled: March 16, 2012Date of Patent: March 31, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
-
Patent number: 8994070Abstract: A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.Type: GrantFiled: December 17, 2013Date of Patent: March 31, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Zhiyuan Cheng
-
Patent number: 8994069Abstract: A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×1017 cm?3 and 1×1020 cm?3, and/or the oxygen concentration within 5×1018 cm?3 and 1×1020 cm?3. The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process.Type: GrantFiled: June 5, 2013Date of Patent: March 31, 2015Assignee: Visual Photonics Epitaxy Co., Ltd.Inventors: Yu-Chung Chin, Chao-Hsing Huang
-
Patent number: 8994032Abstract: III-N material grown on a buffer on a silicon substrate includes a single crystal electrically insulating buffer positioned on a silicon substrate. The single crystal buffer includes rare earth aluminum nitride substantially crystal lattice matched to the surface of the silicon substrate, i.e. a lattice co-incidence between REAlN and Si better than a 5:4 ratio. A layer of single crystal III-N material is positioned on the surface of the buffer and substantially crystal lattice matched to the surface of the buffer.Type: GrantFiled: March 4, 2013Date of Patent: March 31, 2015Assignee: Translucent, Inc.Inventors: Erdem Arkun, Andrew Clark, Rytis Dargis
-
Patent number: 8987028Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.Type: GrantFiled: June 24, 2014Date of Patent: March 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Anthony J. Lochtefeld, Matthew T. Currie, Zhiyuan Cheng, James Fiorenza, Glyn Braithwaite, Thomas A. Langdo
-
Publication number: 20150076558Abstract: The present disclosure provides a FinFET. The FinFET includes a silicon-on-insulator (SOI) with an insulator; a plurality of fin structures on the insulator; an isolation on the insulator, and between two adjacent fin structures in the plurality of fin structures; and an oxide layer between each of the plurality of fin structures and the insulator, wherein the insulator comprises silicon germanium oxide. A method for manufacturing the FinFET includes forming a plurality of fin structures on a layer having a larger lattice constant than that of the fin structure by a patterning operation; oxidizing the fin structure and the layer to transform the layer into a first oxide layer; filling insulating material between adjacent fin structures; and etching the insulating material to expose a top surface and at least a portion of a sidewall of the fin structure.Type: ApplicationFiled: September 13, 2013Publication date: March 19, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: YI-JING LEE, CHENG-HSIEN WU, CHIH-HSIN KO, CLEMENT HSINGJEN WANN
-
Publication number: 20150076559Abstract: Integrated circuits with strained silicon and methods for fabricating such integrated circuits are provided. An integrated circuit includes a stack with a surface layer, an intermediate layer, and a base layer, where the surface layer overlies the intermediate layer, and the intermediate layer overlies the base layer. The surface layer and the base layer include strained silicon, where the silicon atoms are stretched beyond a normal crystalline silicon interatomic distance. The intermediate layer includes crystalline silicon germanium.Type: ApplicationFiled: September 17, 2013Publication date: March 19, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Kai Frohberg, Torsten Huisinga, Egon Ronny Pfuetzner
-
Publication number: 20150076514Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.Type: ApplicationFiled: September 16, 2013Publication date: March 19, 2015Applicant: STMicroelectronics, Inc.Inventors: Pierre Morin, Nicolas Loubet
-
Publication number: 20150076560Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure. An EPI strain-inducing fill is deposited into the cavity. The EPI strain-inducing fill includes a main SiGe layer and a Si cap that overlies the main SiGe layer. The EPI strain-inducing fill is doped with boron and has a first peak boron content in an upper portion of the EPI strain-inducing fill of about 2.5 times or greater than an average boron content in an intermediate portion of the main SiGe layer.Type: ApplicationFiled: September 18, 2013Publication date: March 19, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Joanna Wasyluk, Carsten Reichel, Joachim Patzer, Kai Wurster
-
Patent number: 8981427Abstract: A device includes a crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by using a planarization process configured with a selectivity of the crystalline material to the insulator greater than one. In a preferred embodiment, the planarization process uses a composition including abrasive spherical silica, H2O2 and water. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.Type: GrantFiled: July 15, 2009Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jennifer M. Hydrick, James G. Fiorenza
-
Publication number: 20150069465Abstract: A layer of a silicon germanium alloy containing 30 atomic percent or greater germanium and containing substitutional carbon is grown on a surface of a semiconductor layer. The presence of the substitutional carbon in the layer of silicon germanium alloy compensates the strain of the silicon germanium alloy, and suppresses defect formation. Placeholder semiconductor fins are then formed to a desired dimension within the layer of silicon germanium alloy and the semiconductor layer. The placeholder semiconductor fins will relax for the most part, while maintaining strain in a lengthwise direction. An anneal is then performed which may either remove the substitutional carbon from each placeholder semiconductor fin or move the substitutional carbon into interstitial sites within the lattice of the silicon germanium alloy. Free-standing permanent semiconductor fins containing 30 atomic percent or greater germanium, and strain in the lengthwise direction are provided.Type: ApplicationFiled: September 10, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
-
Patent number: 8975635Abstract: First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.Type: GrantFiled: November 28, 2012Date of Patent: March 10, 2015Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
-
Patent number: 8975674Abstract: A bridge structure for use in a semiconductor device includes a semiconductor substrate and a semiconductor structure layer. The semiconductor structure layer is formed on a surface of the semiconductor substrate and a lattice difference is formed between the semiconductor structure layer and the semiconductor substrate. The semiconductor structure layer includes at least a first block, at least a second block and at least a third block, wherein the first block and the third block are bonded on the surface of the semiconductor substrate, the second block is floated over the semiconductor substrate and connected with the first block and the third block.Type: GrantFiled: November 9, 2012Date of Patent: March 10, 2015Assignee: National Applied Research LaboratoriesInventors: Chun-Lin Chu, Shu-Han Hsu, Guang-Li Luo, Chee-Wee Liu
-
Publication number: 20150060942Abstract: Sometimes to warp a group III nitride semiconductor and a silicon by the stress of the group III nitride semiconductor acting on the silicon. A semiconductor device includes a substrate, a buffer layer, and a semiconductor layer. A trench is formed on a sixth face of the semiconductor layer. The trench passes through the semiconductor layer and the buffer layer. The bottom of the trench reaches at least the inside of the substrate.Type: ApplicationFiled: August 8, 2014Publication date: March 5, 2015Inventors: Ippei Kume, Takashi Onizawa, Takashi Hase, Shigeru Hirao, Tadatoshi Danno
-
Patent number: 8969916Abstract: A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less. A strain-inducing semiconductor alloy is embedded in the semiconductor region laterally adjacent to the bottom portion of the gate electrode structure, and drain and source regions are at least partially positioned in the strain-inducing semiconductor alloy.Type: GrantFiled: July 31, 2014Date of Patent: March 3, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Stephan Kronholz, Markus Lenski, Vassilios Papageorgiou
-
Publication number: 20150054029Abstract: An integrated circuit device includes a semiconductor substrate; and a gate stack disposed over the semiconductor substrate. The gate stack further includes a gate dielectric layer disposed over the semiconductor substrate; a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer comprises tantalum aluminum carbon nitride (TaAlCN); a work function layer disposed over the multi-function blocking/wetting layer; and a conductive layer disposed over the work function layer.Type: ApplicationFiled: November 4, 2014Publication date: February 26, 2015Inventors: SHIU-KO JANGJIAN, TING-CHUN WANG, CHI-CHERNG JENG, CHI-WEN LlU
-
Publication number: 20150054028Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer.Type: ApplicationFiled: October 16, 2014Publication date: February 26, 2015Inventors: Thomas W. DYER, Haining S. YANG
-
Publication number: 20150054030Abstract: MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice constant different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe. Implanting a portion of the source/drain regions with Ge forms the embedded stressor. Implanting carbon into the source/drain regions and annealing the substrate after implanting the carbon suppresses dislocation formation, thereby improving device performance.Type: ApplicationFiled: November 5, 2014Publication date: February 26, 2015Inventors: Chih-Hao Wang, Shih-Hsieng Huang, Ta-Wei Wang
-
Publication number: 20150053992Abstract: A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, a gate structure over the active layer, and a barrier layer between the gate structure and the active layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The gate structure is configured to deplete the 2DEG under the gate structure. The gate structure includes a dopant. The barrier layer is configured to block diffusion of the dopant from the gate structure into the active layer.Type: ApplicationFiled: August 26, 2013Publication date: February 26, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Chun LIU, Chi-Ming CHEN, Chen-Hao CHIANG, Chung-Yi YU, Chia-Shiung TSAI, Xiaomeng CHEN
-
Publication number: 20150048417Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A third silicon germanium region is over the second silicon germanium region, wherein the third silicon germanium region has a third germanium percentage lower than the second germanium percentage.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
-
Publication number: 20150048418Abstract: A semiconductor power device, comprising: a substrate; a first semiconductor layer with a first lattice constant formed on the substrate, wherein the first semiconductor layer comprises a first group III element; a first grading layer formed on the first semiconductor layer and comprising a first portion; a second semiconductor layer with a second lattice constant formed on the first grading layer, wherein the second semiconductor layer comprises a second group III element; and a first interlayer formed in the first grading layer and adjacent to the first portion of the first grading layer, wherein a composition of the first interlayer is different from that of the first portion, and the first grading layer comprises the first group III element and the second group III element, and concentrations of both the first group III element and the second group III element in the first grading layer are gradually changed.Type: ApplicationFiled: April 18, 2014Publication date: February 19, 2015Applicants: HUGA OPTOTECH INC., EPISTAR CORPORATIONInventors: Heng-Kuang LIN, Yih-Ting KUO, Tsung-Cheng CHANG
-
Publication number: 20150048296Abstract: A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar. The inner portion of the active pillar includes a first semiconductor layer having a first lattice constant, and the outer region of the active pillar includes a second semiconductor layer having a second lattice constant smaller than the first lattice constant.Type: ApplicationFiled: August 14, 2014Publication date: February 19, 2015Inventor: Nam Kyun PARK
-
Publication number: 20150041853Abstract: A structure including a compound semiconductor layer epitaxially grown on an epitaxial oxide layer is provided wherein the lattice constant of the epitaxial oxide layer may be different from the semiconductor substrate on which it is grown. Fabrication of one structure includes growing a graded semiconductor layer stack to engineer a desired lattice parameter on a semiconductor substrate or layer. The desired compound semiconductor layer is formed on the graded layer. The epitaxial oxide layer is grown on and lattice matched to the desired layer. Fabrication of an alternative structure includes growing a layer of desired compound semiconductor material directly on a germanium substrate or a germanium layer formed on a silicon substrate and growing an epitaxial oxide layer on the layer of the desired material.Type: ApplicationFiled: August 12, 2013Publication date: February 12, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: KANGGUO CHENG, POUYA HASHEMI, ALI KHAKIFIROOZ, ALEXANDER REZNICEK
-
Publication number: 20150041854Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer.Type: ApplicationFiled: September 19, 2014Publication date: February 12, 2015Inventors: Sung-Li Wang, Ding-Kang Shih, Chih-Hsin Ko
-
Publication number: 20150041852Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.Type: ApplicationFiled: August 9, 2013Publication date: February 12, 2015Applicant: Taiwan Semiconductor Manufacturing Comapny, Ltd.Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
-
Publication number: 20150041825Abstract: A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, and a barrier structure between the substrate and the channel layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The barrier structure is configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer.Type: ApplicationFiled: August 12, 2013Publication date: February 12, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Chun LIU, Chi-Ming CHEN, Chen-Hao CHIANG, Chung-Yi YU, Chia-Shiung TSAI, Xiaomeng CHEN
-
Patent number: 8952419Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.Type: GrantFiled: September 19, 2011Date of Patent: February 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Young-jo Tak, Jae-won Lee, Young-soo Park, Jun-youn Kim
-
Publication number: 20150035009Abstract: A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.Type: ApplicationFiled: July 21, 2014Publication date: February 5, 2015Inventors: Chang-Jae YANG, Sang-Su KIM, Jae-Hwan LEE, Jung-Dal CHOI
-
Publication number: 20150035008Abstract: A finFET device can include a high mobility semiconductor material in a fin structure that can provide a channel region for the finFET device. A source/drain recess can be adjacent to the fin structure and a graded composition epi-grown semiconductor alloy material, that includes a component of the high mobility semiconductor material, can be located in the source/drain recess.Type: ApplicationFiled: March 26, 2014Publication date: February 5, 2015Applicant: Samsung Electronics Co., Ltd.Inventors: Jorge A. Kittl, Mark S. Rodder, Robert C. Bowen
-
Patent number: 8946773Abstract: A semiconductor buffer structure may include a silicon substrate and a buffer layer that is formed on the silicon substrate. The buffer layer may include a first layer, a second layer formed on the first layer, and a third layer formed on the second layer. The first layer may include AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and have a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP2 that is greater than the lattice constant LP1 and smaller than the lattice constant LP0. The third layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP3 that is greater than the lattice constant LP1 and smaller than the lattice constant LP2.Type: GrantFiled: March 15, 2013Date of Patent: February 3, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Young-jo Tak, Jae-kyun Kim, Joo-sung Kim, Jun-youn Kim, Jae-won Lee, Hyo-ji Choi
-
Patent number: 8946772Abstract: A substrate for epitaxial growth of the present invention comprises: a single crystal part comprising a material different from a GaN-based semiconductor at least in a surface layer part; and an uneven surface, as a surface for epitaxial growth, comprising a plurality of convex portions arranged so that each of the convex portions has three other closest convex portions in directions different from each other by 120 degrees and a plurality of growth spaces, each of which is surrounded by six of the convex portions, wherein the single crystal part is exposed at least on the growth space, which enables a c-axis-oriented GaN-based semiconductor crystal to grow from the growth space.Type: GrantFiled: February 13, 2009Date of Patent: February 3, 2015Assignee: Mitsubishi Chemical CorporationInventors: Hiroaki Okagawa, Hiromitsu Kudo, Teruhisa Nakai, Seong-Jin Kim
-
Patent number: 8946775Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0<tilted?0.5° with respect to a axis perpendicular to a (111) crystal plane, and the AlN layer is formed on the surface. The AlGaN layer is formed on the AlN layer. Moreover, an Al content in the AlGaN layer is decreased gradually in a layer thickness direction from the silicon substrate side toward the GaN layer side.Type: GrantFiled: August 22, 2012Date of Patent: February 3, 2015Assignee: Industrial Technology Research InstituteInventors: Chen-Zi Liao, Chih-Wei Hu, Yen-Hsiang Fang, Rong Xuan