With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) Patents (Class 257/190)
  • Publication number: 20150053992
    Abstract: A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, a gate structure over the active layer, and a barrier layer between the gate structure and the active layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The gate structure is configured to deplete the 2DEG under the gate structure. The gate structure includes a dopant. The barrier layer is configured to block diffusion of the dopant from the gate structure into the active layer.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun LIU, Chi-Ming CHEN, Chen-Hao CHIANG, Chung-Yi YU, Chia-Shiung TSAI, Xiaomeng CHEN
  • Publication number: 20150054029
    Abstract: An integrated circuit device includes a semiconductor substrate; and a gate stack disposed over the semiconductor substrate. The gate stack further includes a gate dielectric layer disposed over the semiconductor substrate; a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer comprises tantalum aluminum carbon nitride (TaAlCN); a work function layer disposed over the multi-function blocking/wetting layer; and a conductive layer disposed over the work function layer.
    Type: Application
    Filed: November 4, 2014
    Publication date: February 26, 2015
    Inventors: SHIU-KO JANGJIAN, TING-CHUN WANG, CHI-CHERNG JENG, CHI-WEN LlU
  • Publication number: 20150048418
    Abstract: A semiconductor power device, comprising: a substrate; a first semiconductor layer with a first lattice constant formed on the substrate, wherein the first semiconductor layer comprises a first group III element; a first grading layer formed on the first semiconductor layer and comprising a first portion; a second semiconductor layer with a second lattice constant formed on the first grading layer, wherein the second semiconductor layer comprises a second group III element; and a first interlayer formed in the first grading layer and adjacent to the first portion of the first grading layer, wherein a composition of the first interlayer is different from that of the first portion, and the first grading layer comprises the first group III element and the second group III element, and concentrations of both the first group III element and the second group III element in the first grading layer are gradually changed.
    Type: Application
    Filed: April 18, 2014
    Publication date: February 19, 2015
    Applicants: HUGA OPTOTECH INC., EPISTAR CORPORATION
    Inventors: Heng-Kuang LIN, Yih-Ting KUO, Tsung-Cheng CHANG
  • Publication number: 20150048417
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A third silicon germanium region is over the second silicon germanium region, wherein the third silicon germanium region has a third germanium percentage lower than the second germanium percentage.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Publication number: 20150048296
    Abstract: A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar. The inner portion of the active pillar includes a first semiconductor layer having a first lattice constant, and the outer region of the active pillar includes a second semiconductor layer having a second lattice constant smaller than the first lattice constant.
    Type: Application
    Filed: August 14, 2014
    Publication date: February 19, 2015
    Inventor: Nam Kyun PARK
  • Publication number: 20150041852
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Comapny, Ltd.
    Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Publication number: 20150041853
    Abstract: A structure including a compound semiconductor layer epitaxially grown on an epitaxial oxide layer is provided wherein the lattice constant of the epitaxial oxide layer may be different from the semiconductor substrate on which it is grown. Fabrication of one structure includes growing a graded semiconductor layer stack to engineer a desired lattice parameter on a semiconductor substrate or layer. The desired compound semiconductor layer is formed on the graded layer. The epitaxial oxide layer is grown on and lattice matched to the desired layer. Fabrication of an alternative structure includes growing a layer of desired compound semiconductor material directly on a germanium substrate or a germanium layer formed on a silicon substrate and growing an epitaxial oxide layer on the layer of the desired material.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: KANGGUO CHENG, POUYA HASHEMI, ALI KHAKIFIROOZ, ALEXANDER REZNICEK
  • Publication number: 20150041825
    Abstract: A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, and a barrier structure between the substrate and the channel layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The barrier structure is configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun LIU, Chi-Ming CHEN, Chen-Hao CHIANG, Chung-Yi YU, Chia-Shiung TSAI, Xiaomeng CHEN
  • Publication number: 20150041854
    Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer.
    Type: Application
    Filed: September 19, 2014
    Publication date: February 12, 2015
    Inventors: Sung-Li Wang, Ding-Kang Shih, Chih-Hsin Ko
  • Patent number: 8952419
    Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jo Tak, Jae-won Lee, Young-soo Park, Jun-youn Kim
  • Publication number: 20150035009
    Abstract: A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.
    Type: Application
    Filed: July 21, 2014
    Publication date: February 5, 2015
    Inventors: Chang-Jae YANG, Sang-Su KIM, Jae-Hwan LEE, Jung-Dal CHOI
  • Publication number: 20150035008
    Abstract: A finFET device can include a high mobility semiconductor material in a fin structure that can provide a channel region for the finFET device. A source/drain recess can be adjacent to the fin structure and a graded composition epi-grown semiconductor alloy material, that includes a component of the high mobility semiconductor material, can be located in the source/drain recess.
    Type: Application
    Filed: March 26, 2014
    Publication date: February 5, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Mark S. Rodder, Robert C. Bowen
  • Patent number: 8946774
    Abstract: A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more single crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a mirror polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An axis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: February 3, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masaki Ueno
  • Patent number: 8946775
    Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0<tilted?0.5° with respect to a axis perpendicular to a (111) crystal plane, and the AlN layer is formed on the surface. The AlGaN layer is formed on the AlN layer. Moreover, an Al content in the AlGaN layer is decreased gradually in a layer thickness direction from the silicon substrate side toward the GaN layer side.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: February 3, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chen-Zi Liao, Chih-Wei Hu, Yen-Hsiang Fang, Rong Xuan
  • Patent number: 8946723
    Abstract: Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base. The epitaxial substrate includes a (111) single crystal Si substrate and a buffer layer including a plurality of first lamination units. Each of those units includes a composition modulation layer formed of a first composition layer made of AlN and a second composition layer made of AlxGa1-xN being alternately laminated, and a first intermediate layer made of AlyGa1-yN (0?y<1). The relationship of x(1)?x(2)? . . . ?x(n?1)?x(n) and x(1)>x(n) is satisfied, where n represents the number of laminations of each of the first and second composition layers, and x(i) represents the value of x in i-th one of the second composition layers as counted from the base substrate side. The second composition layer is coherent to the first composition layer, and the first intermediate layer is coherent to the composition modulation layer.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 3, 2015
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Miyoshi, Shigeaki Sumiya, Mikiya Ichimura, Sota Maehara, Mitsuhiro Tanaka
  • Patent number: 8946863
    Abstract: An epitaxial substrate for electronic devices, in which current flows in a lateral direction and of which warpage configuration is properly controlled, and a method of producing the same. The epitaxial substrate for electronic devices is produced by forming a bonded substrate by bonding a low-resistance Si single crystal substrate and a high-resistance Si single crystal substrate together; forming a buffer as an insulating layer on a surface of the bonded substrate on the high-resistance Si single crystal substrate side; and producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate. The resistivity of the low-resistance Si single crystal substrate is 100 ?·cm or less, and the resistivity of the high-resistance Si single crystal substrate is 1000 ?·cm or more.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: February 3, 2015
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Daisuke Hino, Ryo Sakamoto, Tomohiko Shibata
  • Patent number: 8946773
    Abstract: A semiconductor buffer structure may include a silicon substrate and a buffer layer that is formed on the silicon substrate. The buffer layer may include a first layer, a second layer formed on the first layer, and a third layer formed on the second layer. The first layer may include AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and have a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP2 that is greater than the lattice constant LP1 and smaller than the lattice constant LP0. The third layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP3 that is greater than the lattice constant LP1 and smaller than the lattice constant LP2.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jo Tak, Jae-kyun Kim, Joo-sung Kim, Jun-youn Kim, Jae-won Lee, Hyo-ji Choi
  • Patent number: 8946772
    Abstract: A substrate for epitaxial growth of the present invention comprises: a single crystal part comprising a material different from a GaN-based semiconductor at least in a surface layer part; and an uneven surface, as a surface for epitaxial growth, comprising a plurality of convex portions arranged so that each of the convex portions has three other closest convex portions in directions different from each other by 120 degrees and a plurality of growth spaces, each of which is surrounded by six of the convex portions, wherein the single crystal part is exposed at least on the growth space, which enables a c-axis-oriented GaN-based semiconductor crystal to grow from the growth space.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: February 3, 2015
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Hiroaki Okagawa, Hiromitsu Kudo, Teruhisa Nakai, Seong-Jin Kim
  • Publication number: 20150028349
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.
    Type: Application
    Filed: July 29, 2013
    Publication date: January 29, 2015
    Applicant: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Pierre Morin
  • Publication number: 20150021661
    Abstract: A transistor includes a substrate and a graded layer on the substrate, wherein the graded layer is doped with p-type dopants. The transistor further includes a superlattice layer (SLS) on the graded layer, wherein the SLS has a p-type dopant concentration equal to or greater than 1×1019 ions/cm3. The transistor further includes a buffer layer on the SLS, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Inventors: Chi-Ming CHEN, Po-Chun LIU, Chung-Yi YU, Chia-Shiung TSAI, Xiaomeng CHEN
  • Publication number: 20150021660
    Abstract: A transistor includes a substrate and a buffer layer on the substrate, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and a back-barrier layer between a first portion of the channel layer and a second portion of the channel layer. The back-barrier layer has a band gap discontinuity with the channel layer. The transistor further includes an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer. The transistor further includes a two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the active layer.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Inventors: Chi-Ming CHEN, Chih-Wen HSIUNG, Po-Chun LIU, Ming-Chang CHING, Chung-Yi YU, Xiaomeng CHEN
  • Publication number: 20150014745
    Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.
    Type: Application
    Filed: October 2, 2014
    Publication date: January 15, 2015
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Brian R. Bennett, John Bradley Boos, Theresa F. Chick, James G. Champlain
  • Publication number: 20150008483
    Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material having the first lattice constant; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and a pair of notches extending into opposite sides of the middle portion; and an isolation structure surrounding the fin structure, wherein a top surface of the isolation structure is higher than a top surface of the pair of notches.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 8, 2015
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu, Carlos H. Diaz, Jean-Pierre Colinge
  • Patent number: 8927319
    Abstract: There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: January 6, 2015
    Assignee: The Regents of the University of Michigan
    Inventors: Stephen R. Forrest, Jeramy Zimmerman, Kyusang Lee, Kuen-Ting Shiu
  • Patent number: 8927984
    Abstract: A transistor device, such as a rotated channel metal oxide/insulator field effect transistor (RC-MO(I)SFET), includes a substrate including a non-polar or semi-polar wide band gap substrate material such as an Al2O3 or a ZnO or a Group-III Nitride-based material, and a first structure disposed on a first side of the substrate comprising of AlInGaN-based and/or ZnMgO based semiconducting materials. The first structure further includes an intentional current-conducting sidewall channel or facet whereupon additional semiconductor layers, dielectric layers and electrode layers are disposed and upon which the field effect of the dielectric and electrode layers occurs thus allowing for a high density monolithic integration of a multiplicity of discrete devices on a common substrate thereby enabling a higher power density than in conventional lateral power MOSFET devices.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: January 6, 2015
    Assignee: RamGoss, Inc.
    Inventors: Bunmi T. Adekore, James Fiorenza
  • Patent number: 8928036
    Abstract: A barrier infrared detector with absorber materials having selectable cutoff wavelengths and its method of manufacture is described. A GaInAsSb absorber layer may be grown on a GaSb substrate layer formed by mixing GaSb and InAsSb by an absorber mixing ratio. A GaAlAsSb barrier layer may then be grown on the barrier layer formed by mixing GaSb and AlSbAs by a barrier mixing ratio. The absorber mixing ratio may be selected to adjust a band gap of the absorber layer and thereby determine a cutoff wavelength for the barrier infrared detector. The absorber mixing ratio may vary along an absorber layer growth direction. Various contact layer architectures may be used. In addition, a top contact layer may be isolated into an array of elements electrically isolated as individual functional detectors that may be used in a detector array, imaging array, or focal plane array.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: January 6, 2015
    Assignee: California Institute of Technology
    Inventors: David Z. Ting, Cory J. Hill, Alexander Seibel, Sumith Y. Bandara, Sarath D. Gunapala
  • Publication number: 20150001582
    Abstract: An iron-doped high-electron-mobility transistor (HEMT) structure includes a substrate, a nucleation layer over the substrate, and a buffer layer over the nucleation layer. The gallium-nitride buffer layer includes a iron-doping-stop layer having a concentration of iron that drops from a juncture with an iron-doped component of the buffer layer over a thickness that is relatively small compared to that of the iron-doped component. The iron-doping-stop layer is formed at lower temperature compared to the temperature at which the iron-doped component is formed. The iron-doped HEMT structure also includes a channel layer over the buffer layer. A carrier-supplying barrier layer is formed over the channel layer.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Applicant: IQE KC, LLC
    Inventors: Oleg Laboutin, Yu Cao, Wayne Johnson
  • Publication number: 20140374798
    Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
    Type: Application
    Filed: June 24, 2014
    Publication date: December 25, 2014
    Inventors: Anthony J. Lochtefeld, Matthew T. Currie, Zhiyuan Cheng, James Fiorenza, Glyn Braithwaite, Thomas A. Langdo
  • Publication number: 20140374797
    Abstract: A semiconductor device includes a substrate, a compound semiconductor layer, and first and second semiconductor patterns. The substrate includes first and second regions. The first semiconductor pattern is on the compound semiconductor layer of the first region and includes an element semiconductor. The second semiconductor pattern is on the compound semiconductor layer of the second region and includes a Group III-V semiconductor material.
    Type: Application
    Filed: May 13, 2014
    Publication date: December 25, 2014
    Inventors: Tae-Yong KWON, Sang-Su KIM, Jung-Gil YANG, Jung-Dal CHOI
  • Publication number: 20140374796
    Abstract: A semiconductor structure includes a first semiconductor region. The first semiconductor region includes a first semiconductor layer composed of a group IV semiconductor material having a top surface and a back surface. The first semiconductor layer has an opening in the top surface to at least a depth greater than an aspect ratio trapping (ART) distance. The first semiconductor region also has a second semiconductor layer composed of a group III/V semiconductor compound deposited within the opening and on the top surface of the first semiconductor layer. The second semiconductor layer forms an ART region from the bottom of the opening to the ART distance.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 25, 2014
    Inventors: Thomas N. Adam, Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8916906
    Abstract: A silicon wafer used in manufacturing GaN for LEDs includes a silicon substrate, a buffer layer of boron aluminum nitride (BxAl1-xN) and an upper layer of GaN, for which 0.35?x?0.45. The BAlN forms a wurtzite-type crystal with a cell unit length about two-thirds of a silicon cell unit length on a Si(111) surface. The C-plane of the BAlN crystal has approximately one atom of boron for each two atoms of aluminum. Across the entire wafer substantially only nitrogen atoms of BAlN form bonds to the Si(111) surface, and substantially no aluminum or boron atoms of the BAlN are present in a bottom-most plane of atoms of the BAlN. A method of making the BAlN buffer layer includes preflowing a first amount of ammonia equaling less than 0.01% by volume of hydrogen flowing through a chamber before flowing trimethylaluminum and triethylboron and then a subsequent amount of ammonia through the chamber.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: December 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: William E. Fenwick
  • Publication number: 20140367741
    Abstract: Provided is a semiconductor device comprising a substrate including a first area and a second area, first through third crystalline layers sequentially stacked on the first area and having first through third lattice constants, respectively, a first gate electrode formed on the third crystalline layer, fourth and fifth crystalline layers sequentially stacked on the second area and having fourth and fifth lattice constants, respectively, and a second gate electrode formed on the fifth crystalline layer, wherein the third lattice constant is greater than the second lattice constant, the second lattice constant is greater than the first lattice constant, and the fifth lattice constant is smaller than the fourth lattice constant.
    Type: Application
    Filed: January 14, 2014
    Publication date: December 18, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gil YANG, Sang-Su KIM, Chang-Jae YANG
  • Patent number: 8912567
    Abstract: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: December 16, 2014
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., International Business Machines Corporation
    Inventors: Yung Fu Chong, Zhijiong Luo, Judson Holt
  • Patent number: 8912529
    Abstract: A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20140361337
    Abstract: Provided is a lattice-matched HEMT device, which is a HEMT device having high reverse breakdown voltage while securing two-dimensional electron gas concentration in a practical range. In producing a semiconductor device by forming a channel layer made of GaN on a base substrate such as an AlN template substrate or a substrate that includes a Si single crystal base material as a base, forming a barrier layer made of a group-III nitride having a composition of InxAlyGazN (x+y+z=1, 0?z?0.3) on the channel layer, and forming a source electrode, a drain electrode, and a gate electrode on the barrier layer, an In mole fraction x, a Ga mole fraction z, and a thickness d of the barrier layer satisfy a predetermined range.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Applicant: NGK INSULATORS, LTD.
    Inventors: Tomohiko Sugiyama, Shigeaki Sumiya, Sota Maehara, Mitsuhiro Tanaka
  • Publication number: 20140361336
    Abstract: The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 11, 2014
    Inventors: Chung-Hsien Chen, Tung Ying Lee, Yu-Lien Huang, Chi-Wen Liu
  • Publication number: 20140361335
    Abstract: A device includes a substrate, a P-channel transistor and an N-channel transistor. The substrate includes a first layer of a first semiconductor material and a second layer of a second semiconductor material. The first and second semiconductor materials have different crystal lattice constants. The P-channel transistor includes a channel region having a compressive stress in a first portion of the substrate. The channel region of the P-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. The N-channel transistor includes a channel region having a tensile stress formed in a second portion of the substrate. The channel region of the N-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. Methods of forming the device are also disclosed.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Inventors: Stefan Flachowsky, Ralf Illgen, Gerd Zschaezsch
  • Publication number: 20140353715
    Abstract: A transistor device may include a substrate that has a well portion. The transistor device may further include a source member and a drain member. The transistor device may further include a fin bar. The fin bar may be formed of a first semiconductor material, may be disposed between the source member and the drain member, and may overlap the well portion. The transistor device may further include a fin layer. The fin layer may be formed of a second semiconductor material, may be disposed between the source member and the drain member, and may contact the fin bar.
    Type: Application
    Filed: May 16, 2014
    Publication date: December 4, 2014
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: De Yuan XIAO
  • Publication number: 20140353714
    Abstract: A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 4, 2014
    Inventors: Nicolas Loubet, Douglas LaTulipe, Alexander Reznicek
  • Patent number: 8901570
    Abstract: Provided is an epitaxial silicon carbide single-crystal substrate in which a silicon carbide epitaxial film having excellent in-plane uniformity of doping density is disposed on a silicon carbide single-crystal substrate having an off angle that is between 1° to 6°. The epitaxial film is grown by repeating a dope layer that is 0.5 ?m or less and a non-dope layer that is 0.1 ?m or less. The dope layer is formed with the ratio of the number of carbon atoms to the number of silicon atoms (C/Si ratio) in a material gas being 1.5 to 2.0, and the non-dope layer is formed with the C/Si ratio being 0.5 or more but less than 1.5. The resulting epitaxial silicon carbide single-crystal substrate comprises a high-quality silicon carbide epitaxial film, which has excellent in-plane uniformity of doping density, on a silicon carbide single-crystal substrate having a small off angle.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: December 2, 2014
    Assignee: Nippon Steel & Sumitomo Metal Corporation
    Inventors: Takashi Aigo, Hiroshi Tsuge, Taizo Hoshino, Tatsuo Fujimoto, Masakazu Katsuno, Masashi Nakabayashi, Hirokatsu Yashiro
  • Publication number: 20140346564
    Abstract: A multi-threshold voltage (Vt) field-effect transistor (FET) formed through strain engineering is provided. An embodiment integrated circuit device includes a first transistor including a first channel region over a first buffer, the first channel region formed from a III-V semiconductor material and a second transistor including a second channel region over a second buffer, the second channel region formed from the III-V semiconductor material, the second buffer and the first buffer having a lattice mismatch. A first strain introduced by a lattice mismatch between the III-V semiconductor material and the first buffer is different than a second strain introduced by a lattice mismatch between the III-V semiconductor material and the second buffer. Therefore, the threshold voltage of the first transistor is different than the threshold voltage of the second transistor.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gerben Doornbos, Krishna Kumar Bhuwalka
  • Publication number: 20140346565
    Abstract: A method is provided for fabricating MOS transistors. The method includes providing a semiconductor substrate having at least a first region and a second region; and forming first transistors on the semiconductor substrate. Wherein source/drain regions of the first transistors are configured as SiGe growth regions; and a first density of SiGe growth regions in the first region is smaller than a second density of SiGe growth regions in the second region. The method also includes forming dummy SiGe growth regions in the first region to increase the first density such that the total density of SiGe growth regions in the first region is in a range similar to the second density; and forming trenches in the first region and the second region and the dummy SiGe growth region. Further, the method includes forming embedded source/drain regions of the first transistors and dummy SiGe regions.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 27, 2014
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: QINGSONG WEI, SHUKUN YU
  • Patent number: 8895421
    Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: November 25, 2014
    Assignee: Transphorm Inc.
    Inventors: Primit Parikh, Yuvaraj Dora, Yifeng Wu, Umesh Mishra, Nicholas Fichtenbaum, Rakesh K. Lal
  • Patent number: 8896025
    Abstract: A method for fabricating a semiconductor device includes forming a recess to an AlGaN layer by etching, the AlGaN layer having an Al composition ratio of 0.2 or greater, the recess having a bottom having an RMS roughness less than 0.3 nm, forming a first Ta layer having a thickness of 4 nm to 8 nm on the bottom of the recess, and annealing the first Ta layer to make an ohmic contact in the AlGaN layer.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: November 25, 2014
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masatoshi Koyama
  • Patent number: 8896022
    Abstract: A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 0<x<1, a GaN-based carrier transit layer formed on the AlxGa1-xN layer, a carrier supply layer formed on the carrier transit layer, a source electrode and a drain electrode formed on the carrier supply layer, and a gate electrode formed on the carrier supply layer between the source electrode and the drain electrode. Therefore, a GaN-HEMT that is superior in device characteristics can be realized in the case of using a relatively less expensive conductive SiC substrate compared with a semi-insulating SiC substrate.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 25, 2014
    Assignee: Fujitsu Limited
    Inventors: Kenji Imanishi, Toshihide Kikkawa
  • Publication number: 20140339604
    Abstract: A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less. A strain-inducing semiconductor alloy is embedded in the semiconductor region laterally adjacent to the bottom portion of the gate electrode structure, and drain and source regions are at least partially positioned in the strain-inducing semiconductor alloy.
    Type: Application
    Filed: July 31, 2014
    Publication date: November 20, 2014
    Inventors: Stephan Kronholz, Markus Lenski, Vassilios Papageorgiou
  • Patent number: 8890104
    Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 18, 2014
    Assignee: SK Hynix Inc.
    Inventors: Min Yong Lee, Young Ho Lee, Seung Beom Baek, Jong Chul Lee
  • Patent number: 8889531
    Abstract: A semiconductor body comprised of a semiconductor material includes a first monocrystalline region of the semiconductor material having a first lattice constant along a reference direction, a second monocrystalline region of the semiconductor material having a second lattice constant, which is different than the first, along the reference direction, and a third, strained monocrystalline region between the first region and the second region.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: November 18, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Reinhart Job
  • Patent number: 8890206
    Abstract: An AlGaN/GaN HEMT includes a compound semiconductor laminated structure, a gate electrode formed above the compound semiconductor laminated structure, and a p-type semiconductor layer formed between the compound semiconductor laminated structure and the gate electrode, and the p-type semiconductor layer has tensile strain in a direction parallel to a surface of the compound semiconductor laminated structure.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 18, 2014
    Assignee: Transphorm Japan, Inc.
    Inventor: Atsushi Yamada
  • Patent number: 8890207
    Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang