Abstract: The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches.

Abstract: A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.

Abstract: A manufacturing method of a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby a nitride layer is formed on a sidewall of the gate conductive layer and extending into the opening.

Abstract: A flash memory cell string and a method of fabricating the same are provided. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, a tunneling insulating layer, a charge storage node, a control insulating layer, and a control electrode which are sequentially laminated on the semiconductor substrate. In each cell device, a source/drain region is not formed. The switching device does not include a source or drain region in a side connected to the cell devices. The switching device includes a source or drain region in the other side that is not connected to the cell devices. The source or drain region does or does not overlap the control electrode. Accordingly, it is possible to improve a miniaturization property and performance of NAND flash memory cell devices.

Abstract: Provided is a CMOS transistor formed using Ge condensation and a method of fabricating the same. The CMOS transistor may include an insulating layer, a silicon layer on the insulating layer and including a p-MOS transistor region and an n-MOS transistor region, a first gate insulating layer and a first gate on a channel region of the p-MOS transistor region, and a second gate insulating layer and a second gate on a channel region of the n-MOS transistor region, wherein a source region and a drain region of the p-MOS transistor region may be tensile-strained due to Ge condensation, and the channel region of the n-MOS transistor region may be tensile-strained due to the Ge condensation.

Abstract: An active matrix substrate includes: pixel regions (5L, 5R, and 5M) provided in line and column direction; scan signal lines (16? and 16?); data signal lines (Sp, Sq, sp, and sq) crossing the scan signal lines at right angles; a gate insulating film covering the scan signal lines; and an interlayer insulating film covering the data signal lines, two of the data signal lines (Sq and sp) being provided (i) so as to overlap a gap between two of the pixel regions (5L and 5R) which are adjacent to each other in the line direction or (ii) so as to overlap a region which extends along the gap, the interlayer insulating film having a hollow part K so that the hollow part K and a gap between the two of the data signal lines (Sq and sp) overlap each other, and part of the hollow part K and the scan signal lines (16? and 16?) overlap each other via the gate insulating film.

Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.

Abstract: A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size.

Abstract: A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts.

Abstract: Systems and methods are disclosed for forming a custom integrated circuit (IC) with a first fixed (non-programmable) region on a wafer with non-customizable mask layers, wherein the first fixed region includes multiplicities of transistors and a first interconnect layer and a second interconnect layer above the first interconnect layer which form base cells; and a programmable region above the first fixed region with customizable mask layers, wherein at least one mask layer in the programmable region is coupled to the second interconnect layer which provides electrical access to all transistor nodes of the base cells and wherein the programmable region comprises a third interconnect layer coupled to the customizable mask layers to customize the IC. A second fixed region may be formed above the programmable region to provide multiple fixed regions and reduce the number of required masks in customizing the custom IC.

Abstract: A method for fabricating a semiconductor device includes: forming a plurality of photoresist patterns over a substrate structure; forming an insulation layer for a spacer over a structure including the photoresist patterns; forming a plurality of spacers on sidewalls of the photoresist patterns by anisotropically etching the insulation layer, and forming a first opening through the insulation layer; and forming second openings in the insulation layer to expose the substrate structure.

Abstract: The present invention discloses a CMOS-MEMS cantilever structure. The CMOS-MEMS cantilever structure includes a substrate, a circuit structure, and a cantilever beam. The substrate has a circuit area and a sensor unit area defined thereon. The circuit structure is formed in the circuit area. The cantilever beam is disposed in the sensor unit area with one end floating above the substrate and the other end connecting to the circuit structure. With the above arrangement, the manufacturing process of CMOS-MEMS cantilever structure of this invention can be simplified. Furthermore, the structure of the cantilever beam is thinned down and therefore has a higher sensitivity.

Abstract: A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell.

Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

Abstract: Examples of the present invention include methods of assembling structures, such as nanostructures, at predetermined locations on a substrate. A voltage between spaced-apart electrodes supported by substrate attracts the structures to the substrate, and positional registration can be provided the substrate using topographic features such as wells. Examples of the present invention also include devices, such as electronic and optoelectronic devices, prepared by such methods.

Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.

Abstract: A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.

Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of less than about 0.4 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.

Abstract: The chip area of a semiconductor device having a plurality of standard cells is to be made smaller. A semiconductor device includes first and second standard cells. The first standard cell includes a diffusion region, a functional device region opposed to the diffusion region, and a metal layer. The second standard cell includes another diffusion region continuous with the diffusion region, another functional device region opposed to the other diffusion region, and further another diffusion region formed between the other diffusion region and the other functional device region. The metal layer and the other functional device region are coupled together electrically through the diffusion regions.

Abstract: A semiconductor device in a continuous diffusion region formed on a semiconductor substrate and having either a P-type or N-type polarity includes: a first transistor formed within the continuous diffusion region; a second transistor formed within the continuous diffusion region and in an area that is different from an area where the first transistor is formed; a third transistor formed within the continuous diffusion region and in an area between the first and second transistors, and having a gate electrode to which a fixed potential is applied; and a fourth transistor formed within the continuous diffusion region and in an area between the second and third transistors, and having a gate electrode to which a fixed potential is applied.

Abstract: An image sensor with a shared photodiode is provided. The image sensor includes at least two unit pixels, each of which includes a photodiode, a diffusion region which gathers electrons from the photodiode, a transfer transistor which connects the photodiode with the diffusion region, and a readout circuit which reads out a signal from the diffusion region. Photodiodes of neighboring unit pixels are disposed symmetrically to be adjacent to one another to form a shared photodiode. The image sensor does not have a STI region which causes a dark current restricting its performance and does not require a basic minimum design factor (a distance or an area) related to a STI region. A region corresponding to a STI region may be used as a region of a photodiode or for additional pixel scaling. Therefore, a limitation in scaling of a photodiode is overcome, and pixel performance is improved in spite of pixel scaling.

Abstract: Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described.

Abstract: A semiconductor device has a substrate with a source region and a drain region formed on the substrate. A silicide layer is disposed over the source region and drain region. A first interconnect layer is formed over the silicide layer and includes a first runner connected to the source region and second runner connected to the drain region. A second interconnect layer is formed over the first interconnect layer and includes a third runner connected to the first runner and a fourth runner connected to the second runner. An under bump metallization (UBM) is formed over and electrically connected to the second interconnect layer. A mask is disposed over the substrate with an opening in the mask aligned over the UBM. A conductive bump material is deposited within the opening in the mask. The mask is removed and the conductive bump material is reflowed to form a bump.

Abstract: A method for fabricating a semiconductor device includes: forming a plurality of photoresist patterns over a substrate structure; forming an insulation layer for a spacer over a structure including the photoresist patterns; forming a plurality of spacers on sidewalls of the photoresist patterns by anisotropically etching the insulation layer, and forming a first opening through the insulation layer; and forming second openings in the insulation layer to expose the substrate structure.

Abstract: An ESD clamping device comprises a plurality of fingers each comprising a source region of first conductivity type formed in a substrate of second conductivity type, a drain region of said first conductivity type formed in the substrate, and a gate formed over the substrate and between the source and drain regions. At least one of the fingers each has an ESD implantation region formed in the substrate and partially underlying the drain region of the finger, the ESD implantation region being a heavily doped region of said second conductivity type. Furthermore, at least one of the fingers has a gate extension portion projecting from the gate and demarcating an additional region in at least the drain region of the finger, the additional region of said second conductivity type being electrically connected to at least one of the gate and the substrate of each of the fingers.

Abstract: An active matrix substrate 40 according to the present invention includes a conductive film 44 and a wiring 80 for supplying a signal to the conductive film 44, characterized in that the wiring 80 includes a first conductive layer 61 and a second conductive layer 62 having a relatively large line width in comparison with the first conductive layer 61 and laminated so as to cover the first conductive layer 61, and the conductive film 44 is arranged in a matrix pattern, and at least a portion of the conductive film 44 is disposed overlapping the wiring 80.

Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.

Abstract: Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC).

Abstract: A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.

Abstract: A method for producing VDMOS transistors in which a specific layer arrangement and a specific method sequence allow setting up an improved gate contact when simultaneously producing source and gate contacts using a single contact hole mask (photo mask).

Abstract: The chip area of a semiconductor device having a plurality of standard cells is to be made smaller. A semiconductor device includes first and second standard cells. The first standard cell includes a diffusion region, a functional device region opposed to the diffusion region, and a metal layer. The second standard cell includes another diffusion region continuous with the diffusion region, another functional device region opposed to the other diffusion region, and further another diffusion region formed between the other diffusion region and the other functional device region. The metal layer and the other functional device region are coupled together electrically through the diffusion regions.

Abstract: A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.

Abstract: Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.

Abstract: A two terminal switching device includes a first conductive terminal, a second conductive terminal in spaced relation to the first terminal, the first terminal encompassed by the second terminal. The device also includes an electrically insulating spacer that encompasses the first terminal and provides the spaced relation between the second terminal and the first terminal. It also includes a nanotube article comprising at least one carbon nanotube, the nanotube article being arranged to overlap at least a portion of each of the first and second terminals. The device also includes a stimulus circuit in electrical communication with at least one of the first and second terminals that is capable of applying a first electrical stimulus to at least one of the first and second terminals to change the resistance of the device between the first and second terminals from a relatively low resistance to a relatively high resistance.

Abstract: A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using a monolayer or partial monolayer sequencing process. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film.

Abstract: A truss structure is provided. The truss structure comprises a substrate; and plural sub-truss groups disposed on the substrate, wherein each sub-truss group comprises plural VIAs; and plural metal layers interlaced with the plural VIAs, wherein the plural sub-truss groups are piled up on each other to form a 3-D corrugate structure.

Abstract: A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.

Abstract: Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.

Abstract: The present invention provides a method of forming a threshold voltage adjusted gate stack in which an external acid diffusion process is employed for selectively removing a portion of a threshold voltage adjusting layer from one device region of a semiconductor substrate. The external acid diffusion process utilizes an acid polymer which when baked exhibits an increase in acid concentration which can diffuse into an underlying exposed portion of a threshold voltage adjusting layer. The diffused acid reacts with the exposed portion of the threshold voltage adjusting layer providing an acid reacted layer that can be selectively removed as compared to a laterally adjacent portion of the threshold voltage adjusting layer that is not exposed to the diffused acid.

Abstract: A layout design method of a semiconductor integrated circuit includes providing a cell layout including a cell that includes a gate or a plurality of gates extending in a first direction, a plurality of diffusion layers, a first boundary of the cell in parallel with the gate or the plurality of gates, a second boundary of the cell being in an opposite side of the first boundary of the cell, a first distance, a second distance, a third distance, and a fourth distance, regenerating the cell layout to set the first distance and the second distance to a first value, or to set the third distance and the fourth distance to a second value, and generating a library data of the cell for a placement and routing tool, based on the cell layout.

Abstract: A non-volatile memory device including a memory string including a plurality of memory cells coupled in series. The non-volatile memory device includes the memory string including a first semiconductor layer and a second conductive layer with a memory gate insulation layer therebetween, a first selection transistor comprising a second semiconductor layer coupled with one end of the first semiconductor layer, a second selection transistor comprising a third semiconductor layer coupled with the other end of the first semiconductor layer, and a fourth semiconductor layer contacting the first semiconductor layer in a region where the second conductive layer is not disposed.

Abstract: A semiconductor integrated circuit has: a substrate; a basic logic cell placed on the substrate and configured to function as a part of a logic circuit; and a dummy cell placed on the substrate and not configured to function as a part of a logic circuit. The basic logic cell includes a diffusion layer formed in the substrate, and a distance from the diffusion layer to a boundary between the basic logic cell and another cell adjacent to the basic logic cell is equal to a first distance. The dummy cell includes a dummy diffusion layer that is a diffusion layer formed in the substrate, and a distance from the dummy diffusion layer to a boundary between the dummy cell and another cell adjacent to the dummy cell is equal to the first distance.

Abstract: A first gate electrode surrounding the periphery of the first gate insulating film, a second gate insulating film surrounding the periphery of the first gate electrode, a first columnar silicon layer surrounding the periphery of the second gate insulating film, a first upper part high concentration semiconductor layer of the first conductivity type formed in the upper part of the first island-shaped silicon layer, a second lower part high concentration semiconductor layer of the first conductivity type formed in the lower part of the first island-shaped silicon layer, a first upper part high concentration semiconductor layer of the second conductivity type formed in the upper part of the first columnar silicon layer, and a second lower part high concentration semiconductor layer of the second conductivity type formed in the lower part of the first columnar silicon layer.

Abstract: A design method for a semiconductor integrated circuit, includes: a first calculating step; a second calculating step; and a setting step. The first step is a step of calculating a consumption current amount of a layout target circuit based on circuit information. The second calculating step is a step of calculating a suppliable current amount per unit area in a region where a power can be supplied from a power wiring line. The setting step is a step of setting a cell size of the layout target circuit based on the consumption current amount so that a consumption current amount per unit area of the layout target circuit is smaller than the suppliable current amount per unit area.

Abstract: A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric Vt for the PMOS and NMOS FETs.

Abstract: A standard cell library includes a first power rail, a second power rail, a third power rail, a first standard cell, and second standard cells. The first power rail extends in a first direction. The second power rail extends in the first direction, and is spaced apart from the first power rail by a predetermined spacing in a second direction perpendicular to the first direction. The third power rail extends in the first direction between the first power rail and the second power rail. The first standard cell has at least one cell having a first cell height, and is arranged between the first power rail and the second power rail. The second standard cells have at least two cells, each having a second cell height, that are in contact with each other in the second direction, and are in contact with the first standard cell in the first direction.

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor includes a photodiode formed in a substrate structure, first to fourth gate electrodes formed over the substrate structure, spacers formed on both sidewalls of the first to fourth gate electrodes and filled between the third and fourth gate electrodes, a first ion implantation region formed in a portion of the substrate structure below the spacers filled between the third and fourth gate electrodes, and second ion implantation regions formed in portions of the substrate structure exposed between the spacers, the second ion implantation regions having a higher concentration than the first ion implantation region.

Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. The control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. The erase gate is disposed at least partially over and insulated from the floating gate. The erase gate includes a notch, and the floating gate includes an edge that directly faces and is insulated from the notch.