Abstract: A semiconductor arrangement includes a MOSFET having a source region, a drift region and a drain region of a first conductivity type, a body region of a second conductivity type arranged between the source region and the drift region, a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a source electrode contacting the source region and the body region. The semiconductor arrangement further includes a normally-off JFET having a channel region of the first conductivity type that is coupled between the source electrode and the drift region and extends adjacent the body region so that a p-n junction is formed between the body region and the channel region.

Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: A method of manufacturing a junction-field-effect-transistor (JFET) device, the method includes the steps of providing a substrate of a first-type impurity; forming a first well region of a second-type impurity in the substrate; forming a second well region and a third well region of the first-type impurity separated from each other in the first well region; forming a fourth well region of the first-type impurity between the second well region and the third well region; forming a first diffused region of the second-type impurity between the second well region and the fourth well region; forming a second diffused region of the second-type impurity between the third well region and the fourth well region; forming a pair of first doped regions of the second-type impurity in the first well region, and a pair of second doped regions of the first-type impurity in the second well region and the third well region respectively; forming a third doped region of the second-type impurity in the first well region between t

Abstract: In one general aspect, an apparatus can include an anode terminal, and a cathode terminal. The apparatus can include a junction field-effect transistor (JFET) portion having a channel disposed within a semiconductor substrate and defining a first portion of an electrical path between the anode terminal and the cathode terminal. The apparatus can also include a diode portion formed within the semiconductor substrate and defining a second portion of the electrical path between the anode terminal and the cathode terminal. The diode portion can be serially coupled to the channel of the JFET device.

Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.

Abstract: An integrated circuit containing a field controlled diode which includes a p-type channel region between an upper gate and a lower n-type depletion gate, a p-type anode in a p-type anode well abutting the channel region, and an n-type cathode in a p-type anode well abutting the channel region opposite from the anode well. An n-type lower gate link connects the lower gate to the surface of the substrate. A surface control element is located at the surface of the channel region between the cathode and the upper gate. A process of forming the integrated circuit containing the field controlled diode is described.

Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

Abstract: Disclosed herein are various methods for better height control of the finFET patterned fins. In one example, this invention begins by depositing or growing an oxide material, for example, silicon dioxide. This oxide material is then patterned and etched to open windows or trenches to the substrate where fins will be grown. If a common channel material is desired, it is epitaxially grown in the windows. Then, some windows are covered and one pole of fins (for example nFET) are epitaxially grown in the exposed windows. The previously masked windows are opened and the newly formed fins are masked. The alternate channel material is then grown. The masked fins are then un-masked and the oxide is recessed to allow the fins to protrude from the oxide. This invention also allows for different channel materials for NMOS and PMOS.

Abstract: A transistor arrangement includes a first transistor having a drift region and a number of second transistors, each having a source region, a drain region and a gate electrode. The second transistors are coupled in series to form a series circuit that is coupled in parallel with the drift region of the first transistor.

Abstract: A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed.

Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.

Abstract: A semiconductor device and a method for fabricating the same are described. The semiconductor device includes a well of a first conductive type, first doped regions of a second conductive type, gates of the second conductive type, second doped regions of the first conductive type, and isolation structures. The well is disposed in a substrate. The first doped regions are disposed in the well. The first doped regions are arranged in parallel and extend along a first direction. The gates are disposed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is electrically connected to one of the gates. Each of the second doped regions is disposed in the first doped regions between two adjacent gates. Each of the isolation structures is disposed in the substrate between two adjacent first doped regions.

Abstract: A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.

Abstract: The present disclosure discloses an offline low voltage DC output circuit with integrated full bridge rectifiers. The offline low voltage DC output circuit comprises two depletion high voltage pass transistors and a bridge rectifier, wherein most of the voltage is dropped across the pass transistor device. In one embodiment, the offline low voltage DC output circuit further comprises a ballast resistor to minimize substrate injection.

Abstract: A junction field effect transistor comprising: a semiconductor substrate having a first conductivity type; a channel region having a second conductivity type different from the first conductivity type, and being formed in a surface of the semiconductor substrate; a first buried region having the second conductivity type, being formed within the channel region, and having an impurity concentration higher than the channel region; a first gate region having the first conductivity type, and being formed in a surface of the channel region; and first drain/source region and a second drain/source region both having the second conductivity type, which are formed each on an opposite side of the first gate region in the surface of the channel region, in which the first buried region is not formed below the second drain/source region, but is formed below the first drain/source region.

Abstract: The present invention discloses a power device with integrated power transistor and Schottky diode and a method for making the same. The power device comprises a power transistor having a drain region, a Schottky diode in the drain region of the power transistor, and a trench-barrier near the Schottky diode. The trench-barrier is provided to reduce a reverse leakage current of the Schottky diode and minimizes the possibility of introducing undesired parasitic bipolar junction transistor in the power device.

Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The doped well and the substrate have opposite doping polarities. The high voltage semiconductor device includes an insulating device disposed over the doped well. The high voltage semiconductor device includes an elongate resistor disposed over the insulating device. A non-distal portion of the resistor is coupled to the doped well. The high voltage semiconductor device includes a high-voltage junction termination (HVJT) device disposed adjacent to the resistor.

Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.

Abstract: A hybrid device including a silicon based MOSFET operatively connected with a GaN based device.

Abstract: A method includes forming elongate structures on a first substrate, such that the material composition of each elongate structure varies along its length so as to define first and second physically different sections in the elongate structures. First and second physically different devices are then defined in the elongate structures. Alternatively, the first and second physically different sections may be defined in the elongate structures after they have been fabricated. The elongate structures may be encapsulated and transferred to a second substrate. The invention provides an improved method for the formation of a circuit structure that requires first and second physically different devices to be provided on a common substrate. In particular, only one transfer step is necessary.

Abstract: A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.

Abstract: A semiconductor device and a method for fabricating the same are described. The semiconductor device includes a well of a first conductive type, first doped regions of a second conductive type, gates of the second conductive type, second doped regions of the first conductive type, and isolation structures. The well is disposed in a substrate. The first doped regions are disposed in the well. The first doped regions are arranged in parallel and extend along a first direction. The gates are disposed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is electrically connected to one of the gates. Each of the second doped regions is disposed in the first doped regions between two adjacent gates. Each of the isolation structures is disposed in the substrate between two adjacent first doped regions.

Abstract: A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions.

Abstract: A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors.

Abstract: A semiconductor integrated circuit device includes a substrate, a well structure within the substrate, a first region, a second region, and multiple isolation regions within the well structure. The device further includes a channel region within the first region, a gate dielectric layer overlying the channel region, and a gate stack overlying the gate dielectric layer, the gate stack includes a silicide layer overlying a polysilicon layer. The device additionally includes LDD structures on sides of the channel region and spacers on sides of the gate stack. Furthermore, the device includes a source region and a drain region and a contact structure over the source region, and a junction between the contact structure and the source region being within the second region.

Abstract: Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.

Abstract: There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based isolation.

Abstract: There are disclosed herein various implementations of semiconductor devices having passive oscillation control. In one exemplary implementation, such a device is implemented to include a III-nitride transistor having a source electrode, a gate electrode and a drain electrode. A damping resistor is configured to provide the passive oscillation control for the III-nitride transistor. In one implementation, the damping resistor includes at least one lumped resistor.

Abstract: Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: A transistor arrangement includes a first transistor having a drift region and a number of second transistors, each having a source region, a drain region and a gate electrode. The second transistors are coupled in series to form a series circuit that is coupled in parallel with the drift region of the first transistor.

Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.

Abstract: A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner.

Abstract: A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.

Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.

Abstract: Various embodiments of the present invention provide circuits and methods for improved FET matching. As one example, such methods may include providing two or more transistors. Each of the transistors includes a channel that varies in cross-sectional width from the source to the drain, and the transistors are matched one to another.

Abstract: A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.

Abstract: A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage.

Abstract: A support substrate comprises first and second counter-electrodes arranged in the same plane at the level of a surface of the support substrate. An electrically insulating area separates the first and second counter-electrodes. A semi-conducting area with first and second portions is separated from the support substrate by an electrically insulating material. The electrically insulating material is different from the material forming the support substrate. The first portion of the semi-conducting area is facing the first counter-electrode. The second portion of the semi-conducting area is facing the second counter-electrode.

Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.

Abstract: A junction FET having a large gate noise margin is provided. The junction FET comprises an n? layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n? layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.

Abstract: A method for reducing low frequency noise of a transistor operable at cryogenic temperatures includes a first step in which the transistor is illuminated with a light in a state that the transistor is activated and flowed current by supplying a power at a predetermined temperature, and a second step in which the transistor is operated at the predetermined temperature after the illumination of the light.

Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

Abstract: A dynamic random access memory (DRAM) device can include a plurality of memory cells. Each memory cell can include a charge storing structure and an access device comprising an enhancement mode junction field effect transistor (JFET). The DRAM device can further include a plurality of sense amplifiers that each generates an output value in response to a signal received at respective sense amplifier inputs, and a plurality of bit lines, each bit line coupling a plurality of memory cells to at least one input of at least one of the sense amplifiers. A method can fabricate such DRAM devices.

Abstract: According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET.

Abstract: Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.

Abstract: A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors.

Abstract: A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions.