Abstract: Ferroelectric structures, including a ferroelectric field effect transistors (FeFETs), and methods of making the same are disclosed which have improved ferroelectric properties and device performance. A FeFET device including a ferroelectric material gate dielectric layer and a metal oxide semiconductor channel layer is disclosed having improved ferroelectric characteristics, such as increased remnant polarization, low defects, and increased carrier mobility for improved device performance.

Abstract: A semiconductor device includes: a substrate; a first dielectric layer over the substrate; a memory cell over the substrate in a first region of the semiconductor device, where the memory cell includes a first ferroelectric structure in the first dielectric layer, where the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer in between; and a tunable capacitor over the substrate in a second region of the semiconductor device, where the tunable capacitor includes a second ferroelectric structure, where the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer in between, where at least a portion of the second ferroelectric structure is in the first dielectric layer.

Abstract: A semiconductor device comprises a semiconductor material extending through a stack of alternating levels of a conductive material and an insulative material, and a material comprising cerium oxide and at least another oxide adjacent to the semiconductor material. Related electronic systems and methods are also disclosed.

Abstract: Transistors with switchable polarity and non-volatile configurations are provided. The transistors include a van der Waals (vdW) semiconductor layer. A ferroelectric layer with local polarization determines the type and concentration of the doping in the vdW semiconductor layer. Local program gates allow application of voltage to set or switch the polarization in the ferroelectric layer in the source and drain regions. Source and drain contacts permit either n-type or p-type transistor operations according to the carrier polarity in the vdW semiconductor layer.

Abstract: A device includes a substrate, a first layer of getter material, a first electrode, an insulator element, a second electrode, a first input-output electrode, and a second input-output electrode. The first layer of getter material is deposited on the substrate. The first electrode is formed in a first conductive layer deposited on the first layer of getter material. The first layer of getter material has a getter capacity for hydrogen that is higher than the first electrode. The insulator element is formed in a piezoelectric layer deposited on the first electrode. The second electrode is formed in a second conductive layer deposited on the insulator element. The first input-output electrode is conductively connecting to the first layer of getter material. The second input-output electrode is conductively connecting to the second electrode.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a shunting layer overlying a spin orbit torque (SOT) layer. A magnetic tunnel junction (MTJ) structure overlies a semiconductor substrate. The MTJ structure includes a free layer, a reference layer, and a tunnel barrier layer disposed between the free and reference layers. A bottom electrode via (BEVA) underlies the MTJ structure, where the BEVA is laterally offset from the MTJ structure by a lateral distance. The SOT layer is disposed vertically between the BEVA and the MTJ structure, where the SOT layer continuously extends along the lateral distance. The shunting layer extends across an upper surface of the SOT layer and extends across at least a portion of the lateral distance.

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The method for forming a semiconductor structure includes forming a semiconductor stack over a substrate, wherein the semiconductor stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatively stacked, patterning the semiconductor stack to form a first fin and a second fin adjacent to the first fin, and removing the second semiconductor layers to obtain a first group of nanosheets over the first fin and a second group of nanosheets over the second fin, wherein a lateral spacing between one of the nanosheets in the first group and a corresponding nanosheet in the second group is smaller than a vertical spacing between each of the nanosheets in the first group.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Abstract: A ferroelectric semiconductor device of the present disclosure includes a substrate having a channel structure, a trench pattern having a bottom surface and a sidewall surface in the channel structure, a dielectric layer disposed on the bottom surface and the sidewall surface of the trench pattern, and a gate electrode layer disposed on the dielectric layer. The dielectric layer includes a ferroelectric layer pattern and a non-ferroelectric layer pattern that are disposed along the sidewall surface of the trench pattern.

Abstract: One illustrative method disclosed herein includes forming at least one first layer of insulating material above an upper surface of a top electrode of a memory cell, forming a patterned etch stop layer above the at least one first layer of insulating material, wherein the patterned etch stop layer has an opening that is positioned vertically above at least a portion of the upper surface of the top electrode and forming at least one second layer of insulating material above an upper surface of the etch stop layer. The method also includes forming a conductive contact opening that extends through the etch stop layer to expose at least a portion of the upper surface of the top electrode and forming a conductive contact structure in the conductive contact opening, wherein the conductive contact structure is conductively coupled to the upper surface of the top electrode.

Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell including a gate structure including a ferroelectric layer and a channel layer adjacent to the gate structure, the channel layer including a metal oxide material. A driver circuit is configured to output a gate voltage to the gate structure of a memory cell, the gate voltage having a positive polarity and a first magnitude in in a first write operation and a negative polarity and a second magnitude in in a second write operation, and to control the second magnitude to be greater than the first magnitude.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method includes: forming a silicide layer, forming a vertical Si channel layer, wherein the vertical Si channel layer is on an upper surface of the silicide layer, the vertical Si channel layer has a first silicon phase; performing a first annealing step so as to move the silicide layer upward and change a solid phase of the vertical Si channel layer from the first silicon phase to a second silicon phase at an interface of the silicide layer and the vertical Si channel layer, wherein the second silicon phase has a conductivity higher than a conductivity of the first silicon phase.

Abstract: Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.

Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

Abstract: A memory device may include a first conductor and a second conductor; a switching layer arranged between the first conductor and the second conductor, and one or more magnetic layers. The switching layer may be configured to have a switchable resistance in response to a change in voltage between the first conductor and the second conductor. The one or more magnetic layers may be arranged such that the one or more magnetic layers provide a magnetic field through the switching layer.

Abstract: Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

Abstract: An interconnect for a semiconductor device includes: a carrier; a UV programmable chip mounted on the carrier using a first array of solder connections; a UV light source mounted on the carrier using a second array of solder connections, the UV light source being in optical communication with the UV programmable chip; and a plurality of transmission lines extending on or through the carrier and providing electrical communication between the UV programmable chip and the UV light source.

Abstract: A storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first MOS transistor. A gate of the first MOS transistor is connected to the first storage bit, a source of the first MOS transistor is connected to a first read line, and a drain of the first MOS transistor is connected to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line; or in a second state, the second read line is a read word line, and the first read line is a read bit line.

Abstract: Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

Abstract: Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

Abstract: To allow a metal oxide film composed mainly of O and at least one of Hf and Zr to exhibit ferroelectric properties. After deposition of a hafnium oxide film on a semiconductor substrate via an insulating film, the semiconductor substrate is exposed to microwaves to selectively heat the hafnium oxide film. This makes it possible to form a larger number of orthorhombic crystals in the crystals of the hafnium oxide film. The hafnium oxide film thus obtained can therefore exhibit ferroelectric properties without adding, thereto, an impurity such as Si. This means that the hafnium oxide film having a reverse size effect can be used as a ferroelectric film of a ferroelectric memory cell and contributes to the manufacture of a miniaturized ferroelectric memory cell.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor, which in turn comprises a polar layer comprising a crystalline base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV.

Abstract: A semiconductor device includes: a first electrode; a second electrode; and a dielectric layer stack positioned between the first electrode and the second electrode, the dielectric layer stack including a first anti-ferroelectric layer, a second anti-ferroelectric layer, and a ferroelectric layer between the first anti-ferroelectric layer and the second anti-ferroelectric.

Abstract: A dielectric film may be exposed to an acid solution such as hydrochloric acid, nitric acid, or sulfuric acid during a wet process after film formation. The inventors have newly found that when a dielectric film includes Zr having a lower ionization tendency than Ti in a main component of a metal oxide expressed by a general formula (Ba, Ca)(Ti, Zr)O3 is provided and satisfies at least one between relationships such that degree of orientation of (100) plane is higher than degree of orientation of (110) plane, and degree of orientation of (111) plane is higher than degree of orientation of (110) plane in a film thickness direction, the dielectric film is less likely to be damaged during a wet process, and the resistance to a wet process is improved.

Abstract: A semiconductor device may comprise a stack structure on a substrate, the stack structure including a plurality of dielectric layers and a plurality of transparent conductive oxide layers, the dielectric layers and the transparent conductive oxide layers are alternately stacked, each of the dielectric layers and a corresponding one of the transparent conductive oxide layer adjacent to each other in a vertical direction have equal horizontal widths, and a channel structure extending through the stack structure, the channel structure including an information storage layer, a channel layer inside the information storage layer, and a buried dielectric layer inside the channel layer.

Abstract: A memory device includes a plurality of memory cells. Each memory cell includes a multi-gate FeFET that has a first source/drain terminal, a second source/drain terminal, and a gate with a plurality of ferroelectric layers configured such that each of the ferroelectric layers has a respective unique switching E-field.

Abstract: A semiconductor device structure is provided. The device includes first semiconductor layers and second semiconductor layers disposed below and aligned with the first semiconductor layers. Each first semiconductor layer is surrounded by a first and fourth intermixed layers. The first intermixed layer is disposed between the first semiconductor layer and the fourth intermixed layer and includes a first and second materials. The fourth intermixed layer includes a third and fourth materials. Each second semiconductor layer is surrounded by a second and third intermixed layers. The second intermixed layer is disposed between the second semiconductor layer and the third intermixed layer and includes the first and a fifth material. The third intermixed layer includes the third and a sixth material. The second and fourth material are a dipole material having a first polarity, and the fifth and sixth material are a dipole material having a second polarity opposite the first polarity.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a capacitor comprises a crystalline polar layer comprising a base polar material substitutionally doped with a dopant. The base polar material comprises one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element of one of 4d series, 5d series, 4f series or 5f series that is different from the one or more metal elements, such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV.

Abstract: A display system and a method for forming an output buffer of a source driver are provided. The display system includes a plurality of pixels coupled to a plurality of gate lines and a plurality of source lines. A gate driver provides a plurality of gate signals to the plurality of gate lines. A source driver provides a plurality of image signals to the plurality of source lines. The source driver includes an output buffer. The output buffer includes a transistor. The transistor is either a native transistor device, a depletion-mode transistor device or a low-threshold transistor device.

Abstract: A cross-point memory device includes first conductive line structures laterally extending along a first horizontal direction, an array of memory pillar structures overlying top surfaces of the first conductive line structures, such that each of the memory pillar structures includes a respective memory element, and second conductive line structures laterally extending along a second horizontal direction and overlying top surfaces of the array of memory pillar structures. At least one of the first conductive line structures and the second conductive line structures each includes a respective aluminum-containing rail and a respective metallic cap strip in contact with a top surface of the respective aluminum-containing rail.

Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate having a first surface, a plurality of ferroelectric layers stacking over the first surface, and a plurality of metal layers stacking over the first surface of the substrate, wherein each of the metal layers is on each of the ferroelectric layers. The operations of the method for manufacturing the semiconductor structure includes providing a substrate having a first surface, and forming a plurality of stack units over the first surface of the substrate The forming of each of the stack units includes the operations of forming a ferroelectric layer and forming a metal layer on the ferroelectric layer.

Abstract: The embodiments of the present disclosure provide a method for manufacturing a capacitor array structure, a capacitor array structure and a semiconductor memory device. The method for manufacturing a capacitor array structure includes: providing a substrate; forming a capacitor structure on the substrate; wherein the capacitor structure includes a bottom electrode layer formed on the substrate, a capacitor dielectric layer formed on a surface of the bottom electrode layer, and a top electrode layer formed on a surface of the capacitor dielectric layer; and there is gaps formed by the top electrode layer; forming a filling layer to fill the gaps; forming a covering layer to cover the filling layer and the top electrode layer; wherein, the covering layer is combined with the filling layer to define a top electrode conductive layer.

Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate and at least one trench line formed within the substrate. The semiconductor device further includes a self-aligned landing pad in contact with the at least one trench line, and a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad. The method includes forming a conductive layer on and in contact with at least one trench line formed within a substrate. Magnetic tunnel junction stack layers are deposited on and in contact with the conductive layer. The magnetic tunnel junction stack layers are etched to form a magnetic tunnel junction stack, where the etching stops on the conductive layer.

Abstract: A semiconductor device includes a channel region between a source region and a drain region, a gate over the channel region, a dielectric layer over the gate, a capacitive field plate over the dielectric layer, and a word line electrically coupled to the capacitive field plate.

Abstract: A display device that performs image correction in accordance with external light environment is provided. The display device includes a host device and an optical sensor. In addition, the display device includes a processing circuit. The host device has a function of performing arithmetic processing using a neural network on software and a function of performing supervised learning with the neural network. The processing circuit has a function of performing arithmetic processing using a neural network on hardware. The optical sensor has a function of obtaining illuminance of external light. The obtained illuminance of external light is inputted to the host device, and a luminance and color tone preferred by users are regarded as teacher data, whereby learning is performed on the neural network of the host device. A weight coefficient obtained through the learning is used as a weight coefficient of the neural network of the processing circuit.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to ferroelectric based transistors and methods of manufacture. The ferroelectric based transistor includes: a semiconductor-on-insulator substrate including a semiconductor material, a buried insulator layer under the semiconductor material and a substrate material under the semiconductor channel material; a ferroelectric capacitor under the buried insulator layer and which includes a bottom electrode, a top electrode and a ferroelectric material between the bottom electrode and the top electrode; a gate stack over the semiconductor material; a first terminal contact connecting to the bottom electrode of the ferroelectric capacitor; and a second terminal contact connecting to the top electrode of the ferroelectric capacitor.

Abstract: A method for treating a layer of composition ABO3, wherein A is a first material composition consisting of at least one element selected from the group consisting of: Li, Na, K, H, Ca, Mg, Ba, Sr, Pb, La, Bi, Y, Dy, Gd, Tb, Ce, Pr, Nd, Sm, Eu, Ho, Zr, Sc, Ag, and Tl, and wherein B is a second material composition consisting of at least one element selected from the group consisting of: Nb, Ta, Sb, Ti, Zr, Sn, Ru, Fe, V, Sc, C, Ga, Al, Si, Mn, Zr, and Tl, is described. The method includes implanting an ionic species into a donor substrate of the composition ABO3, thereby forming a weakened zone delineating the layer, detaching the layer from the donor substrate along the weakened zone, and exposing the detached layer to a medium containing ions of a constituent element A, such that the ions penetrate into the layer.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a transistor formed on a silicon substrate and a capacitor electrically connected to the transistor by a conductive via. The capacitor comprises upper and lower conductive oxide electrodes on opposing sides of a polar layer, wherein the lower conductive oxide electrode is electrically connected to a drain of the transistor.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. A ferroelectric switching layer is arranged between the bottom electrode and the top electrode. The ferroelectric switching layer is configured to change polarization based upon one or more voltages applied to the bottom electrode or the top electrode. A seed layer is arranged between the bottom electrode and the top electrode. The seed layer and the ferroelectric switching layer have a non-monoclinic crystal phase.

Abstract: According to various aspects, a memory cell comprise: a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal to control the memory cell; a first memory element (FeFET1) and a second memory element (FeFET2), the first memory element comprising a first capacitive memory structure electrically connected to the first terminal and a first field-effect transistor structure coupled to the first capacitive memory structure and electrically connected to the third terminal and the forth terminal; the second memory element comprising a second capacitive memory structure electrically connected to the second terminal and a second field-effect transistor structure coupled to the second capacitive memory structure and electrically connected to the third terminal and the fifth terminal.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.

Abstract: A memory cell arrangement is provided that may include: one or more memory cells, each of the one or more memory cells including: an electrode pillar having a bottom surface and a top surface; a memory material portion surrounding a lateral surface portion of the electrode pillar; an electrode layer surrounding the memory material portion and the lateral surface portion of the electrode pillar, wherein the electrode pillar, the memory material portion, and the electrode layer form a capacitive memory structure; and a field-effect transistor structure comprising a gate structure, wherein the bottom surface of the electrode pillar faces the gate structure and is electrically conductively connected to the gate structure, and wherein the top surface of the electrode pillar faces away from the gate structure.

Abstract: An integrated chip has a memory cell that includes a magnetic tunnel junction (MTJ) device and an access selector apparatus. The MTJ device includes a free layer and a pinned layer. The access selector apparatus includes a first metal structure and a second metal structure separated by one or more non-metallic layers. The first metal structure includes a polarized magnetic layer. The polarized magnetic layer produces a magnetic field that extends through the free layer, tilting its magnetic field and thereby substantially reducing a switching time for the MTJ device. The access selector apparatus may be a bipolar selector. The polarized magnetic layer may be incorporated into an electrode of the bipolar selector. Both the access selector apparatus and the MTJ device may be formed by a stack of material layers. The resulting memory cell may be compact and have good write speed.

Abstract: Upon detecting that an occupant has donned electronic smart glasses, an occupant protection system in a vehicle takes into account that the occupant is wearing electronic smart glasses.

Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.

Abstract: A semiconductor memory device of an embodiment includes: a semiconductor layer; a gate electrode layer; a first insulating layer provided between the semiconductor layer and the gate electrode layer; a second insulating layer provided between the first insulating layer and the gate electrode layer; and an intermediate layer provided between the first insulating layer and the second insulating layer, the intermediate layer containing a first crystal of a space group Pbca (space group number 61), a space group P42/nmc (space group number 137), or a space group R-3m (space group number 166), and the intermediate layer containing hafnium (Hf), oxygen (O), and nitrogen (N).

Abstract: Techniques and mechanisms to provide a memory array comprising a 1T1C (one transistor and one capacitor) based memory cell. In an embodiment, the memory cell comprises a transistor, fabricated on a backend of a die, and a capacitor which includes a ferroelectric material. The transistor of the 1T1C memory cell is a vertical transistor. In another embodiment, the capacitor is positioned vertically over the transistor.