Abstract: An ultra-large height top electrode for MRAM is achieved by employing a novel thin metal/thick dielectric/thick metal hybrid hard mask stack. Etching parameters are chosen to etch the dielectric quickly but to have an extremely low etch rate on the metals above and underneath. Because of the protection of the large thickness of the dielectric layer, the ultra-large height metal hard mask is etched with high integrity, eventually making a large height top electrode possible.

Abstract: A display device having an improved display characteristics and reduced manufacturing cost is provided. The display device includes a plurality of pixels arranged on a surface of a substrate. The plurality of pixels each include: a light-emitting element; a driving transistor; a selecting transistor; and a retention capacitor. The driving transistor has a bottom-gate structure. The driving transistor has a semiconductor layer containing a first semiconductor. The retention capacitor has a first electrode and a second electrode. The first electrode doubles as a gate of the driving transistor. The second electrode is disposed at a lower layer than the first electrode and contains a second semiconductor.

Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

Abstract: The magnetoresistance effect element includes a semiconductor layer, a first ferromagnetic layer and a second ferromagnetic layer. The semiconductor layer has a first region, a second region, and a third region. The first ferromagnetic layer is provided on the first region, the second ferromagnetic layer is provided on the second region, and the third region is sandwiched between the first region and the second region in the first direction. The third region has n-type conductivity, and crystal orientations of the semiconductor material in the first direction are substantially the same in the first region, the second region, and the third region. An interatomic distance of the third region in an upper surface neighboring region including the upper surface is larger than an interatomic distance of the first region in the upper surface neighboring region.

Abstract: The invention relates to a method for manufacturing a microelectronic circuit. A substrate is provided. A source contact, a bulk contact and a drain contact are each produced for a transistor and for a memory transistor. In a respective common step, an insulating layer of the transistor and an insulating layer of the memory transistor as well as a metal layer of the transistor and a metal layer of the memory transistor are produced. At least one capacitor is produced as part of the memory transistor. Gate contacts connected to the metal layer of the transistor and connected to a metal layer of the capacitor of the memory transistor, respectively, are produced. Furthermore, the invention relates to a microelectronic circuit.

Abstract: The present disclosure provides a magnetic random access memory structure, including an array region, and a logic region adjacent to the array region. The logic region includes a bottom electrode via, a magnetic tunneling junction layer over the bottom electrode via, a top electrode over the MTJ, a conformable oxide layer over the MTJ and the top electrode, and a silicon oxide layer over the conformable oxide layer. The conformable oxide layer and the silicon oxide layer extend from the array region to the logic region.

Abstract: Structures for a non-volatile memory element and methods of fabricating a structure for a non-volatile memory element. The structure includes a bottom electrode, a seed layer on the bottom electrode, and a magnetic-tunneling-junction layer stack on the seed layer. The seed layer is composed of a nickel-chromium-ruthenium alloy including ruthenium in an amount ranging from seven atomic percent by weight to eighty-four atomic percent by weight.

Abstract: In a ferroelectric memory having a ferroelectric film between a gate electrode and a semiconductor substrate, dielectric breakdown of a gate insulating film is prevented and the polarization performance of the ferroelectric film is enhanced to improve the performance of a semiconductor device. In a memory cell including a field effect transistor including a control gate electrode formed over the semiconductor substrate, between the control gate electrode and a main surface of the semiconductor substrate, a paraelectric film and the ferroelectric film are formed by being stacked in this order over the main surface of the semiconductor substrate.

Abstract: A semiconductor device includes a first word line and a second word line extending abreast of each other in a first direction. A bit line extends between the first word line and the second word line in a second direction intersecting the first direction. A lower electrode is formed on one surface of the first word line. An ovonic threshold switch (OTS) is formed on the lower electrode. An intermediate electrode is formed on the OTS. A phase change memory (PCM) is formed on the intermediate electrode, and an upper electrode is formed between the first PCM and a surface of the bit line. The width of the first upper electrode in the second direction is narrower than the width of the first intermediate electrode in the second direction.

Abstract: Various means for improvement in signal-to-noise ratio (SNR) for a magnetic field sensor are disclosed for low power and high resolution magnetic sensing. The improvements may be done by reducing parasitic effects, increasing sense element packing density, interleaving a Z-axis layout to reduce a subtractive effect, and optimizing an alignment between a Z-axis sense element and a flux guide, etc.

Abstract: A replacement gate structure (i.e., functional gate structure) is formed and recessed to provide a capacitor cavity located above the recessed functional gate structure. A ferroelectric capacitor is formed in the capacitor cavity and includes a bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure. The bottom electrode structure has a topmost surface that does not extend above the U-shaped ferroelectric material liner. A contact structure is formed above and in contact with the U-shaped ferroelectric material liner and the top electrode structure of the ferroelectric capacitor.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

Abstract: A method of manufacturing a ferroelectric element includes forming an insulating film on one side of a metal substrate by an electron beam (EB) vapor deposition method or a sputtering method; forming a metal film on the insulating film by the sputtering method; and forming a ferroelectric film on the metal film by a sol-gel method. The metal substrate includes iron (Fe) and nickel (Ni), and a content of the nickel (Ni) is greater than or equal to 30% and less than or equal to 40%.

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first to fourth magnetic layers, first and second intermediate layers, and a controller. The conductive layer includes first, to fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first intermediate layer is provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the fourth portion and the third magnetic layer. The second intermediate layer is provided between the third and fourth magnetic layers. The controller is electrically connected to the first and second portions. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.

Abstract: To provide a magnetic memory for storing multi-level information capable of reading while sufficiently securing a read margin. Provided is a magnetic memory including: first and second magnetic storage elements that are provided between a first wiring and a second wiring crossing each other, and are electrically connected in series; a third wiring electrically connected between the first and second magnetic storage elements; a first determination unit that determines a magnetization state of the first magnetic storage element on the basis of a current flowing to the first magnetic storage element through the third wiring; and a second determination unit that determines a magnetization state of the second magnetic storage element on the basis of a current flowing to the first and second magnetic storage elements through the first wiring, in which the determination state of the second determination unit is changed on the basis of the determination result of the first determination unit.

Abstract: A perpendicularly magnetized spin-orbit magnetic device including a heavy metal layer, a magnetic tunnel junction, a first antiferromagnetic layer, a first block layer and a first stray field applying layer is provided. The magnetic tunnel junction is disposed on the heavy metal layer. The first block layer is disposed between the magnetic tunnel junction and the first antiferromagnetic layer. The first stray field applying layer is disposed between the first antiferromagnetic layer and the first block layer. The magnetic tunnel junction comprises a free layer, a tunneling barrier layer, and pinned layer. The tunneling barrier layer is disposed on the free layer. The pinned layer is disposed on the tunneling barrier layer. A film plane area of the free layer is greater than a film plane area of the tunneling barrier layer and a film plane area of the pinned layer.

Abstract: A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.

Abstract: Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another.

Abstract: A method of fabricating a semiconductor device having two dimensional (2D) lateral hetero-structures includes forming alternating regions of a first metal dichalcogenide film and a second metal dichalcogenide film extending along a surface of a first substrate. The first metal dichalcogenide and the second metal dichalcogenide films are different metal dichalcogenides. Each second metal dichalcogenide film region is bordered on opposing lateral sides by a region of the first metal dichalcogenide film, as seen in cross-sectional view.

Abstract: A dielectric composition with high voltage resistance and favorable reliability, and an electronic component using the dielectric composition. The dielectric composition contains, as a main component, a tungsten bronze type composite oxide represented by a chemical formula (Sr1.00?s?tBasCat)6.00?xRx(Ti1.00?aZra)x+2.00(Nb1.00?bTab)8.00?xO30.00 in which the R is at least one element selected from Y, La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and s, t, x, a, and b satisfy 0.50?s?1.00, 0?t?0.50, 0.50?s+t?1.00, 0.50<x?1.50, 0.30?a?1.00, and 0?b?1.00. At least one or more elements selected from Mn, Mg, Co, V, W, Mo, Si, Li, B, and Al are contained as a sub component in 0.10 mol or more and 20.00 mol or less with respect to 100 mol of the main component.

Abstract: A magnetoresistive random access memory (MRAM) memory cell comprises a pinned layer having fixed direction of magnetization that is perpendicular to a plane of the pinned layer, a first free layer having a direction of magnetization that can be switched and is perpendicular to a plane of the first free layer, a tunnel barrier positioned between the pinned layer and the first free layer, a second free layer having a direction of magnetization that can be switched, and a spacer layer positioned between the first free layer and the second free layer. Temperature dependence of coercivity of the second free layer is greater than temperature dependence of coercivity of the first free layer.

Abstract: A technique relates to a magnetic device. A configuration in a memory layer of the magnetic device is adjusted, the configuration affecting stochastic fluctuations in a free magnetic layer of a magnetic tunnel junction coupled to the memory layer. The stochastic fluctuations are used to define a random number according to the configuration in the memory layer.

Abstract: [Object] provide a dielectric composition with high voltage resistance and favorable reliability, and an electronic component using the dielectric composition. [Solving Means] A dielectric composition contains, as a main component, a tungsten bronze type composite oxide represented by a chemical formula (Sr1.00?s?tBasCat)6.00?xRx(Ti1.00?aZra)x+2.00(Nb1.00?bTab)8.00?xO30.00, in which the R is at least one element selected from Y, La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and s, t, x, a, and b satisfy 0.70?s?1.00, 0?t?0.30, 0.70?s+t?1.00, 0?x?0.50, 0.10?a?1.00, and 0?h?1.00. At least one or more elements selected from Mn, Mg, Co, V, W, Mo, Si, Li, B, and Al are contained as a sub component in 0.10 mol or more and 20.00 mol or less with respect to 100 mol of the main component.

Abstract: According to one embodiment, a magnetic device includes a first memory cell including a magnetoresistive effect element, a selector, and a first barrier material disposed between the selector and the magnetoresistive effect element, wherein the first barrier material has a thermal conductivity of 5 W/mK or lower.

Abstract: A method is presented for reducing dielectric gouging during etching processes of a magnetoresistive random access memory (MRAM) structure including an MRAM region and a non-MRAM region. The method includes forming protective layers in the MRAM region to preserve integrity of underlying dielectric layers, forming a bottom electrode in direct contact with the protective layers, and constructing an MRAM pillar over the bottom electrode, wherein the MRAM pillar includes a magnetic tunnel junction (MTJ) stack and a top electrode.

Abstract: Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.

Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. The method first provides an electrically conductive structure embedded in an interconnect dielectric material layer of a magnetoresistive random access memory device. A conductive landing pad is located on a surface of the electrically conductive structure. A multilayered magnetic tunnel junction (MTJ) structure and an MTJ cap layer is formed on the landing pad. Then there is formed a first conductive layer on top the MTJ cap layer and a second conductive metal layer formed on top the first conductive layer. A pillar mask structure is then patterned and formed on the second conductive layer. The resulting structure is subject to lithographic patterning and etching to form a patterned bilayer metal hardmask pillar structure on top the MTJ cap layer. Subsequent etch processing forms an MTJ stack having sidewalls aligned to the patterned bilayer metal hardmask pillar.

Abstract: A dielectric composition with high voltage resistance and favorable reliability, and an electronic component using the dielectric composition. The dielectric composition contains, as a main component, a tungsten bronze type composite oxide represented by a chemical formula (Sr1.00-(s+t)BasCat)6.00-xRx(Ti1.00-aZra)x+2.00(Nb1.00-bTab)8.00-xO30.00, in which the R is at least one element selected from Y, La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and s, t, x, a, and b satisfy 0.50?s?1.00, 0?t?0.30, 0.50?s+t?1.00, 1.50<x?3.00, 0.20?a?1.00, and 0?b?1.00. At least one selected from Mn, Mg, Co, V, W, Mo, Si, Li, B, and Al is contained as a sub component in 0.10 mol or more and 20.00 mol or less with respect to 100 mol of the main component.

Abstract: A magnetoresistive random access memory and a method for manufacturing the same are provided, with which a stress layer covers a part of the protective layer along a direction of a current in the spin-orbit coupling layer, so that a stress is generated on the part of the magnetic layer locally due to the stress layer, thus a lateral asymmetric structure is formed in a direction perpendicular to the current source. In a case that a current is supplied to the spin-orbit coupling layer, the spin-orbit coupling effect in the magnetic layer is asymmetric due to the stress on the part of the magnetic layer, thereby realizing a deterministic switching of the magnetic moment under the function of the stress.

Abstract: The invention provides a magnetoresistance element with a configuration such that a stable switching action is possible with a current flowing in response to the application of a unipolar electrical pulse, and a non-volatile semiconductor storage device using the magnetoresistance element. A magnetoresistance element 1-1 includes a magnetic tunnel junction portion 13 configured by sequentially stacking a perpendicularly magnetized first magnetic body 22, an insulation layer 21, and a perpendicularly magnetized second magnetic body 200. The second magnetic body 200 has a configuration wherein a ferromagnetic layer and a rare earth-transition metal alloy layer are stacked sequentially from the insulation layer 21 side interface.

Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.

Abstract: The present invention discloses a molecular beam epitaxy under vector strong magnetic field and an in-situ characterization apparatus thereof. The apparatus mainly consists of an inverted T-shaped ultrahigh vacuum growth and characterization chamber with a compact structure and a strong magnet. The inverted T-shaped vacuum chamber portion, which disposed in the room-temperature chamber of the strong magnet, includes a compact epitaxial growth sample stage, a device capable of rotating angle between the growth and magnetic field directions, and an in-situ characterization apparatus. The portion disposed below the strong magnet includes a molecular beam source component such as evaporation source, plasma source etc., and a vacuum-pumping system.

Abstract: A method for forming an interconnect structure is provided. The method includes: forming a dielectric layer on a substrate, and forming an opening in the dielectric layer; forming a first metal layer, a second metal layer, and a third metal layer sequentially over the dielectric layer. The opening of the dielectric layer is filled with the first metal layer to form a conductive via. The method also includes: performing one or multiple etch operation to etch the first metal layer, the second metal layer, and the third metal layer, so as to form a metal line corresponding to the first metal layer, an intermediate metal layer corresponding to the second metal layer, and a metal pillar corresponding to the third metal layer. In particular, the width of the metal line is greater than the width of the metal pillar.

Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.

Abstract: A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a lateral barrier layer connected to the bottom contact, the memory layer, and the conductive top electrode, where the lateral barrier layer is configured to substantially prevent conduction of ions or vacancies from the bottom contact, the memory layer, and the conductive top electrode to the lateral barrier layer.

Abstract: A semiconductor device includes a stack structure having a plurality of interlayer insulation layers and a plurality of gate electrode layers which are alternately stacked on a substrate, a ferroelectric insulation layer and a channel layer sequentially stacked on a sidewall of a trench that penetrates the stack structure, and a capping oxide pattern disposed between the ferroelectric insulation layer and each of the plurality of interlayer insulation layers. The capping oxide pattern and the ferroelectric insulation layer include the same metal oxide material.

Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The conductive member includes a first layer. The first layer includes at least one selected from the group consisting of HfN having a NaCl structure, HfN having a fcc structure, and HfC having a NaCl structure. The first magnetic layer is separated from the first layer in a first direction. The second magnetic layer is provided between the first layer and the first magnetic layer. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer.

Abstract: An electronic device includes a driving circuit suitable for driving an output node with an input voltage signal based on a control voltage applied to a control node, a boost circuit suitable for boosting voltage of the output node based on an output boost signal, and a compensating circuit suitable for applying the control voltage to the control node based on control signals to compensate for voltage drop caused by the driving circuit.

Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes.

Abstract: A device is disclosed that includes a driver and a plurality of resistive memory cells each being electrically connected to the driver through a first line. The driver has a variable resistance corresponding to various locations of a conducted resistive memory cell, relative to the driver, in the plurality of resistive memory cells.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to rounded shaped transistors and methods of manufacture. The structure includes a gate structure composed of a metal electrode and a rounded ferroelectric material which overlaps an active area in a width direction into an isolation region.

Abstract: A ferroelectric memory device according to an embodiment includes a base conduction layer, a channel layer extending in a vertical direction from the base conduction layer, a ferroelectric layer disposed on the channel layer, a plurality of ferroelectric memory cell transistor stacked in a vertical direction on the base conduction layer, a control transistor disposed over the plurality of ferroelectric memory cell transistors, and a bit line pattern electrically connected to the channel layer.

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.

Abstract: A MLU cell for sensing an external magnetic field, including a magnetic tunnel junction including a sense layer having a sense magnetization adapted to be oriented by the external magnetic field; a reference layer having a reference magnetization; a tunnel barrier layer; a biasing layer having a biasing magnetization and a biasing antiferromagnetic layer pinning the biasing magnetization substantially parallel to the pinned reference magnetization at a low threshold temperature and freeing it at a high threshold temperature. A biasing coupling layer is between the sense layer and the basing layer and configured for magnetically coupling the biasing layer and the sense layer such that the sense magnetization is oriented substantially perpendicular to the pinned biasing magnetization and to the pinned reference magnetization. The present disclosure further concerns a magnetic sensor device for sensing an external magnetic field, including a plurality of the MLU cells.

Abstract: An array, such as an MRAM (Magnetic Random Access Memory) array formed of a multiplicity of layered thin film devices, such as MTJ (Magnetic Tunnel Junction) devices, can be simultaneously formed in a multiplicity of horizontal widths in the 60 nm range while all having top electrodes with substantially equal thicknesses and coplanar upper surfaces. This allows such a multiplicity of devices to be electrically connected by a common conductor without the possibility of electrical opens and with a resulting high yield.

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

Abstract: A display panel includes a first conductive layer including a first layer, a second layer, and a third layer sequentially stacked, and a second conductive layer on the first conductive layer and contacting the third layer. The first layer includes a first metal. The second layer includes the first metal and oxygen in a first composition ratio. The third layer includes the first metal and oxygen at a second composition ratio. The second composition ratio is smaller than the first composition ratio. Conductivity of the third layer is higher than conductivity of the second layer. The first composition ratio is a ratio of an atom percent of the first metal to an atom percent of oxygen in the second layer. The second composition ratio is a ratio of an atom percent of the first metal to an atom percent of oxygen in the third layer.

Abstract: A magnetic tunnel junction device and a magnetic memory device. The magnetic tunnel junction device includes a magnetic tunnel junction including a fixed magnetic body, an insulator, and a free magnetic body sequentially stacked and a conducting wire disposed adjacent the free magnetic body of the magnetic tunnel junction to apply in-plane current. The fixed magnetic body has a fixed magnetization direction and is a thin film including a material magnetized directionally perpendicular to a film surface. The free magnetic body has a structure of [auxiliary free magnetic layer/free non-magnetic layer]N/main free magnetic layer, where N is a positive integer greater than or equal to 2 and indicates that an [auxiliary free magnetic layers/free non-magnetic layers] structure is stacked repeatedly N times.