Abstract: A method of forming a high energy density capacitor comprises depositing a first metal layer on a substrate, depositing a first layer of polarizable dielectric material comprised of a high K dielectric material on said first metal layer, and applying a momentary high voltage electric field of positive or negative polarity above said first layer of polarizable dielectric material forming an electret. The method further comprises depositing a second metal layer on said first layer of polarizable dielectric material, depositing a second layer of polarizable dielectric material comprised of a high K dielectric material onto said second metal layer, and applying a second momentary high voltage electric field of opposing polarity above said second layer of polarizable dielectric material to align dipoles of the second layer into one or more electrets that will oppose a main electric field created as the capacitor is charging.

Abstract: A first amorphous film containing hafnium, oxygen and a first element such as zirconium is formed, a plurality of grains containing a second element different from any of hafnium, oxygen and the first element are formed on the first amorphous film, a second amorphous film made of the same material as the first amorphous film is formed on the plurality of grains and on the first amorphous film, and a metal film is formed on the second amorphous film. Thereafter, by performing heat treatment, the first amorphous film is crystallized to form a first orthorhombic ferroelectric film and the second amorphous film is crystallized to form a second orthorhombic ferroelectric film.

Abstract: A dielectric membrane may be exposed to an acid solution such as hydrochloric acid, nitric acid, or sulfuric acid during a wet process after membrane formation. The inventors have newly found that when a dielectric membrane includes Ca having a lower ionization tendency than Ba and Zr having a lower ionization tendency than Ti in a main component of a metal oxide expressed by a general formula (Ba, Ca)(Ti, Zr)O3 and satisfies at least one of degree of orientation of (100) plane>degree of orientation of (110) plane and degree of orientation of (111) plane>degree of orientation of (110) plane in a membrane thickness direction, the dielectric membrane is less likely to be damaged during a wet process, and the resistance to a wet process is improved.

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

Abstract: A method comprising: providing a substrate comprising one or more electronic structures; providing a layer of perovskite overlaying the one or more electronic structures; coating a layer of photoresist material overlaying the layer of perovskite; aligning a mask with the one or more electronic structures and patterning the photoresist material; and using the same etchant to remove sections of the patterned photoresist material and the perovskite underneath the sections of the photoresist material.

Abstract: A package structure includes a substrate, a first capacitor, a System on Chip unit and a wiring layer. The first capacitor is provided on the substrate. The System on Chip unit is bonded with the first capacitor in a first dielectric layer. The wiring layer is configured to electrically couple the first capacitor and the System on Chip unit. The wiring layer is provided on the first dielectric layer through a second dielectric layer.

Abstract: A memory cell is provided that may include: a field-effect transistor structure including a channel and a gate structure disposed adjacent to the channel, the gate structure including: one or more remanent-polarizable layers, a gate electrode, wherein the one or more remanent-polarizable layers are disposed between the gate electrode and the channel, and one or more charge storage structures disposed between at least one of the one or more remanent-polarizable layers and the channel and/or the one or more remanent-polarizable layers and the gate electrode, the one or more charge storage structures are configured to stabilize a polarization state associated with the one or more remanent-polarizable layers by trapping charge in the one or more charge storage structures.

Abstract: A ferroelectric memory device includes a substrate having a source region and a drain region, a ferroelectric structure having a first ferroelectric material layer, an electrical floating layer, and a second ferroelectric material layer sequentially stacked on the substrate, and a gate electrode layer disposed on the ferroelectric structure. A coercive electric field of the first ferroelectric material layer is different from that of the second ferroelectric material layer, and the electrical floating layer comprises a conductive material.

Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

Abstract: Technical solutions are described for forming a semiconductor device for a crosspoint array that implements a pre-programmed neural network. An example method includes sequentially depositing a semiconducting layer, a top insulating layer, and a shunting layer onto a base insulating layer. The method further includes etching selective portions of the top insulating layer corresponding to resistance values associated with weights of the crossbar that implements the neural network.

Abstract: Disclosed is a three-dimensional non-volatile ferroelectric memory including a ferroelectric memory array structure, wherein the ferroelectric memory array structure includes multiple layers of ferroelectric memory cell array disposed in a stacked way, and each layer of the ferroelectric memory cell array includes ferroelectric memory cells arranged in rows and columns; wherein word lines and bit lines which are substantially orthogonal to each other are oppositely disposed on two sides of the corresponding ferroelectric memory cell respectively, and a reference ferroelectric body is disposed adjacent to the corresponding ferroelectric memory cell. A polarization direction of an electric domain in the ferroelectric memory cell is not perpendicular to an electric field direction of a write voltage signal applied to the word line and the bit line; and when the write voltage signal is applied between the word line and the bit line.

Abstract: To provide a magnetic storage element, a magnetic storage device, and an electronic device which store multi-value information with a simpler structure.

Abstract: A display panel having a low-resistance conductive layers is disclosed. An example display panel includes a first conductive layer having a first layer, a second layer, a third layer, a fourth layer, and a fifth layer that are sequentially stacked with the first layer being electrically conductive with the fifth layer, and a second conductive layer that is disposed on the first conductive layer and that in contact with the fifth layer. The first layer and the third layer include a first metal. Further, the second layer includes a second metal that is different from the first metal. Still further, the fourth layer includes the first metal and oxygen in a first composition ratio, and the fifth layer includes the first metal and oxygen in a second composition ratio with the first composition ratio and the second composition ratio being different from each other.

Abstract: A semiconductor device includes a stack structure having a plurality of interlayer insulation layers and a plurality of gate electrode layers which are alternately stacked on a substrate, a ferroelectric insulation layer and a channel layer sequentially stacked on a sidewall of a trench that penetrates the stack structure, and a capping oxide pattern disposed between the ferroelectric insulation layer and each of the plurality of interlayer insulation layers. The capping oxide pattern and the ferroelectric insulation layer include the same metal oxide material.

Abstract: An ultra-broad spectrum detector integrated with functions of a two-dimensional semiconductor and a ferroelectric material, where the device includes a substrate, a two-dimensional semiconductor, a source electrode, a drain electrode, a ferroelectric material and a gate electrode; the two-dimensional semiconductor, the source electrode and the drain electrode are arranged on an upper surface of the substrate, and the source electrode and the drain electrode are respectively arranged at two ends of an upper surface of the two-dimensional semiconductor; two sides of the two-dimensional semiconductor are respectively connected with the lower-layer metal of the source electrode and the lower-layer metal of the drain electrode; the ferroelectric material is arranged on the upper surfaces of the two-dimensional semiconductor, the source electrode and the drain electrode; and the lower surface of the gate electrode is connected with the upper surface of the ferroelectric material.

Abstract: A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.

Abstract: A semiconductor device includes a substrate including first and second active regions, first and second active patterns disposed on the first and second active regions, respectively, first and second gate electrodes crossing the first and second active patterns, respectively, a first gate insulating pattern interposed between the first active pattern and the first gate electrode, and a second gate insulating pattern interposed between the second active pattern and the second gate electrode. The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern disposed on the first dielectric pattern. The second gate insulating pattern includes a second dielectric pattern. A threshold voltage of a transistor in the first active region is different from a threshold voltage of a transistor in the second active region.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode, a magnetic junction on the conductive layer and a second electrode above the magnetic junction. The magnetic junction includes a magnetic structure including a first magnetic layer including cobalt, a non-magnetic layer including platinum or tungsten on the first magnetic layer and a second magnetic layer including cobalt on the non-magnetic layer. The magnetic junction further includes an anti-ferromagnetic layer on the magnet structure, a fixed magnet above the anti-ferromagnetic layer, a free magnet above the fixed magnet and a tunnel barrier between the fixed magnet and the free magnet.

Abstract: Techniques are disclosed for forming integrated circuit (IC) devices that include ferroelectric field-effect transistors (FE-FETs) having a top gate and a bottom gate (or, generally, a dual-gate configuration). The disclosed FE-FET devices may be formed in the back end of the IC structure and may be implemented with various materials that exhibit ferroelectric properties when processed at temperatures within the thermal budget of the back-end processing. The disclosed back-end FE-FET devices can achieve greater than two resistance states, depending on the direction of poling of the top and bottom gates, thereby enabling the formation of 3-state and 4-state memory devices, for example. Additionally, as will be appreciated in light of this disclosure, the disclosed back-end FE-FET devices can free up floor space in the front-end, thereby providing space for additional devices in the front-end.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

Abstract: Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 ?. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.

Abstract: A memory device may be provided that includes: a substrate; a coupling layer which is located on the substrate and has electrical conductivity; a meta-atomic layer which is located on or under the coupling layer; a memory layer which is located on the meta-atomic layer; and an electrode layer which is located on the memory layer and has electrical conductivity. The memory layer is composed of a material which produces spontaneous polarization at a voltage equal to or higher than a predetermined voltage. Through this, the memory device can be electrically driven and can continuously maintain modulated optical characteristics. Also, the memory device according to the embodiment of the present invention can modulate optical characteristics by multiple electrical inputs.

Abstract: A ferroelectric memory device includes an alternating stack of insulator layers and electrically conductive layers and located over a top surface of a substrate, a memory stack structure vertically extending through the alternating stack and including a ferroelectric material layer, a front-side gate dielectric contacting the ferroelectric material layer, and a vertical semiconductor channel contacting the front-side gate dielectric, a backside gate dielectric contacting the vertical semiconductor channel, and a backside gate electrode contacting the backside gate dielectric. Portions of the ferroelectric material layer adjacent to the electrically material layers can be programmed with polarization states to store data.

Abstract: In an embodiment, a ferroelectric memory element includes a first electrode layer, a ferroelectric structure disposed on the first electrode layer, and a second electrode layer disposed on the ferroelectric structure. The ferroelectric structure includes a ferroelectric material layer having a concentration gradient of a dopant.

Abstract: A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer.

Abstract: Disclosed is a multilayer insulator, a metal-insulator-metal (MIM) capacitor with the same, and a fabricating method thereof. The capacitor includes: a first electrode; an insulator disposed on the first electrode, the insulator including: a laminate structure in which an aluminum oxide (Al2O3) layer and a hafnium oxide (HfO2) layer are laminated alternately in an iterative manner and a bottom layer and a top layer are formed of the same material; and a second electrode disposed on the insulator.

Abstract: The semiconductor memory device of the embodiment includes a stacked body including interlayer insulating layers and gate electrode layers alternately stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; a first insulating layer provided between the semiconductor layer and the gate electrode layers; conductive layers provided between the first insulating layer and the gate electrode layers; and second insulating layers provided between the conductive layers and the gate electrode layers and the second insulating layers containing ferroelectrics. Two of the conductive layers adjacent to each other in the first direction are separated by one of the interlayer insulating layers interposed between the two of the conductive layers, and a first thickness of one of the gate electrode layers in the first direction is smaller than a second thickness of one of the conductive layers in the first direction.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a variable resistance element that exhibits different resistance states for storing data; and a lower contact plug coupled to the variable resistance element and disposed under the variable resistance element, and wherein a width of the lower contact plug increases from a top surface of the lower contact plug to a bottom surface of the lower contact plug.

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.

Abstract: In a semiconductor pressure sensor element, a first hydrogen permeation protection film is provided on a principal surface side of a first silicon substrate, and a second hydrogen permeation protection film is provided on a principal surface side of a second silicon substrate. The permeation paths of the hydrogen fluxes shown by the arrows A and B in FIG. 9 are blocked by the films. Also, a trench surrounding a reference pressure chamber is provided, and the first hydrogen permeation protection film and a third hydrogen permeation protection film are joined at the bottom portion of the trench, thereby blocking the permeation path of the hydrogen flux shown by the arrow C in FIG. 9. Furthermore, by providing a hydrogen storage chamber, hydrogen is trapped before the hydrogen reaches the reference pressure chamber.

Abstract: A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.

Abstract: Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.

Abstract: A memory device includes memory cells, the memory cells each including a first gate, a second gate electrically isolated from the first gate, a first gate insulating layer including a data storage layer having a ferroelectric material and disposed between the first gate and a channel region, a second gate insulating layer disposed between the second gate and the channel region, a first switching cell connected between the memory cells and a source line, and a second switching cell connected between the memory cells and a bit line. The second switching cell includes a third gate, a fourth gate, a third gate insulating layer not including a data storage layer having the ferroelectric material and the third gate disposed between the third gate and the channel region, and a fourth gate insulating layer disposed between the fourth gate and the channel region.

Abstract: A method for tuning the frequency of THz radiation is provided. The method utilizes an apparatus comprising a spin injector, a tunnel junction coupled to the spin injector, and a ferromagnetic material coupled to the tunnel junction. The ferromagnetic material comprises a Magnon Gain Medium (MGM). The method comprises the step of applying a bias voltage to shift a Fermi level of the spin injector with respect to the Fermi level of the ferromagnetic material to initiate generation of non-equilibrium magnons by injecting minority electrons into the Magnon Gain Medium. The method further comprises the step of tuning a frequency of the generated THz radiation by changing the value of the bias voltage.

Abstract: A structure and operation method of a spin device using a magnetic domain wall movement by spin orbit torque are provided. It is possible to invert the magnetization of free layer of the device at a low value of current by using the spin orbital torque, and the structure of the device is simpler than that of the conventional CMOS. Further, a spin synapse device to which a free layer of multiaxial anisotropy is applied in addition to movement of a magnetic domain wall is provided. Since the magnetoresistance can be adjusted according to the angle of the pinned layer and the free layer, it is easy to apply multi-bit and it can be applied to artificial synapse technology.

Abstract: In one embodiment, a device is described for using ferroelectric material in a memory cell. In another embodiment, a method of operating a ferroelectric memory cell is described. Other embodiments are likewise described.

Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a semiconductor device comprises: a first pillar magnetic tunnel junction (pMTJ) memory cell that comprises a first pMTJ located in a first level in the semiconductor device; and a second pillar magnetic tunnel junction (pMTJ) memory cell that comprises a second pMTJ located in a second level in the semiconductor device, wherein the second pMTJ location with respect to the first pMTJ is coordinated to comply with a reference pitch for the memory cell. A reference pitch is associated a first switch coupled to the first pMTJ and the second pitch reference component is a second switch coupled to the second pMTJ. The first switch and second switch can be transistors. The reference pitch coordination facilitates reduced pitch between memory cells and increased information storage capacity of bits per memory device area.

Abstract: A material may include at least one of BixSe(1-x), BixTe(1-x), or SbxTe(1-x), where x is greater than 0 and less than 1. In some examples, the material exhibits a Spin Hall Angle of greater than 3.5 at room temperature. The disclosure also describes examples of devices that include a spin-orbit torque generating layer, in which the spin-orbit torque generating layer includes at least one of BixSe(1-x), BixTe(1-x), or SbxTe(1-x), where x is greater than 0 and less than 1. In some examples, the spin-orbit torque generating layer exhibits a Spin Hall Angle of greater than 3.5 at room temperature.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may include forming a control device within a substrate. A first plurality of interconnect layers are formed within a first inter-level dielectric (ILD) structure over the substrate. A first memory device and a second memory device are formed over the first ILD structure. A second plurality of interconnect layers are formed within a second ILD structure over the first ILD structure. The first plurality of interconnect layers and the second plurality of interconnect layers couple the first memory device and the second memory device to the control device.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a control device arranged within a substrate and having a terminal. A first memory device is coupled between the terminal of the control device and a first bit-line. A second memory device is coupled between the terminal of the control device and a second bit-line.

Abstract: An integrated circuit comprises a ferroelectric memory cell comprising a ferroelectric film comprising a binary oxide ferroelectric with the formula XO2 where X represents a transition metal. The ferroelectric film is a polycrystalline film having a plurality of crystal grains, wherein the crystal grains are oriented along a predetermined crystal axis, or the ferroelectric film is a monocrystalline film, wherein the ferroelectric film comprises additives promoting formation of the crystal structure of the monocrystalline film and/or wherein the memory cell comprises a crystallinity-promoting layer that is directly in contact with the ferroelectric film and promotes formation of the crystal structure of the monocrystalline film.

Abstract: A storage memory device includes a vertical field effect transistor including a semiconductor substrate; a pillar extending upwardly from the substrate and containing a source, a drain, and a channel disposed therebetween; a first insulating layer surrounding the channel; a stacked structure surrounding the first insulating layer; and a gate unit. The stacked structure includes a charge trapping layer and a composite element. The composite element includes a ferroelectric layer made of a doped hafnium oxide-based material that has a predominantly orthorhombic phase and exhibits a negative capacitance; and an antiferroelectric layer made of a zirconium oxide-based material that has a predominantly tetragonal phase.

Abstract: A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of pass gate electrodes, and ferroelectric material portions located between the semiconductor channel and the plurality of word lines.

Abstract: An electronic device includes a capacitor and a passivation layer covering the capacitor. The capacitor includes a first electrode, a dielectric layer disposed over the first electrode and a second electrode disposed over the dielectric layer. An area of the first electrode is greater than an area of the dielectric layer, and the area of the dielectric layer is greater than an area of the second electrode so that a side of the capacitor has a multi-step structure.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.

Abstract: A semiconductor device according to an embodiment includes a first electrode, a dielectric layer structure disposed on the first electrode and having a ferroelectric layer and a non-ferroelectric layer, and a second electrode disposed on the dielectric structure. The ferroelectric layer has positive and negative coercive electric fields having different absolute values. The dielectric structure has a non-ferroelectric property.

Abstract: There is disclosed a method of manufacturing a ferroelectric memory device according to one embodiment. In the method, a substrate is prepared. An interfacial insulating layer is formed on the substrate. A ferroelectric material layer is formed on the interfacial insulating layer. An interfacial oxide layer including a first metal element is formed on the ferroelectric material layer. A gate electrode layer including a second metal element is formed on the interfacial oxide layer. The ferroelectric material layer and the interfacial oxide layer are subjected to a crystallization heat treatment to form a ferroelectric layer and a ferroelectric interfacial layer. The interfacial oxide layer reacts with the gate electrode layer so that the ferroelectric interfacial layer includes the first and second metal elements.

Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.