Abstract: Conventional capacitors constituted of a FET incur degradation in frequency response. A semiconductor integrated circuit includes a semiconductor substrate, an N-type FET, a P-type FET, and capacitors. The N-type FET includes N-type impurity diffusion layers, a P-type impurity-implanted region, a gate insulating layer, and a gate electrode. The P-type FET includes P-type impurity diffusion layers, an N-type impurity-implanted region, a gate insulating layer, and a gate electrode. The capacitor includes N-type impurity diffusion layers, an N-type impurity-implanted region, a capacitance insulating layer, and an upper electrode. The capacitor includes P-type impurity diffusion layers, a P-type impurity-implanted region, a capacitance insulating layer, and an upper electrode.

Abstract: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: The invention relates to a trench capacitor, in particular for use in a semiconductor memory cell, comprising a trench (2), embodied in a substrate (1), a first region (1a), provided in the substrate (1), as first capacitor electrode, a dielectric layer (10) on the trench wall as capacitor dielectric and a metallic filler material (30?) provided in the trench (2) as second electrode. Above the conducting metallic filling material (30?) a dielectric filling material (35) is provided in the trench (2) with a cavity (40) provided for mechanical tensions. The invention further relates to a corresponding method of production.

Abstract: A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least one common type of atoms for allowing the first and second hydrogen barrier films to adhere to each other.

Abstract: A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.

Abstract: A trench (12) of a semiconductor memory cell (1) has an insulation collar (44), which is open toward the substrate (42) on just one side (50). On the other side (52), the insulation collar (44, 47, 55) rises all the way up to the insulation cover (62). There is therefore no need for a shallow trench isolation. The contact (70) which is buried on one side is formed by oblique implantation, for example with N2 or argon, the implantation taking place from a fixedly predetermined direction with an angle of inclination of between 15 and 40°. The implantation substances effect different etching or oxidation properties, etc., of the implanted materials. In combination with this method, it becomes possible to realize a new layout for the semiconductor memory cell (1), in which the structures for forming the active areas form long lines (31) extending over a plurality of adjacent semiconductor memory cells.

Abstract: A field-effect transistor (FET) structure and method of formation thereof is presented. The FET structure includes first and second source/drain regions formed in a semiconductor substrate to define a channel region. A gate insulation layer is formed at a surface of the channel region. A control layer is formed at a surface of the gate insulation layer. A diode doping region is formed to realize a diode in the semiconductor substrate. An electrically conductive diode connection layer connects the diode doping region to the control layer. A depression is formed in the semiconductor substrate. The diode doping region is formed at a bottom of the depression and the diode connection layer is formed in the depression to dissipate excess charge carriers in the semiconductor substrate.

Abstract: A semiconductor device comprises bit line landing pads and storage landing pads disposed on both sides of the bit line landing pads overlying a substrate. A bit line interlayer insulating layer overlies the bit line and storage landing pads. A plurality of bit line patterns are disposed on the bit line interlayer insulating layer. The bit line patterns each include a bit line and a bit line capping layer pattern. Line insulating layer patterns are placed on a top surface of the bit line interlayer insulating layer. Upper contact holes are placed in a region between the bit line patterns and higher than upper surfaces of the bit lines. Contact hole spacers cover the side walls of the upper contact holes. Lower contact holes are self-aligned with the upper contact holes and extend through the line insulating layer patterns and the bit line interlayer insulating layer, thereby exposing the storage node landing pads.

Abstract: A semiconductor device has a capacitive element including a first conductive film formed on the bottom and wall surfaces of an opening formed in an insulating film on a substrate, a dielectric film formed on the first conductive film, and a second conductive film formed on the dielectric film. The dielectric film of the capacitive element is crystallized. The first and second conductive films are made of a polycrystal of an oxide, a nitride or an oxynitride of a noble metal.

Abstract: Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least one common type of atoms for allowing the first and second hydrogen barrier films to adhere to each other.

Abstract: A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area of the upper surface, and at least a part of the charge storage layer being provided in the trench, first insulating layer between the lower surface of the charge storage layer and a bottom surface of the trench, second insulating layer between a side surface of the trench and a side surface of the charge storage layer and between the side surface of the trench and a side surface of the first insulating layer, third insulating layer on the charge storage layer, and a control gate electrode on the third insulating layer.

Abstract: A semiconductor device includes a conductive film that is filled in a trench formed in a semiconductor substrate via a first insulating film. The conductive film has a first portion and a second portion with an upper surface higher than the first portion. A second insulating film provided on the first portion of the conductive film has a first portion and a second portion whose upper surface is higher than the surface of the semiconductor substrate. The first portion of the second insulating film contacts the second portion of the second insulating film and has an upper surface lower than the surface of the second portion of the conductive film. A first gate electrode and a second gate electrode are provided on the second insulating film and above the semiconductor substrate, respectively. A connection conductive layer extends on the conductive film and on one of source/drain diffusion layers.

Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

Abstract: Arrangement of capacitors which, without taking up an additional area in the semiconductor substrate, have an increased capacitance compared with conventional capacitors in DRAM memory cells. The arrangement of capacitors according to the invention is based on a combination of two or more separately arranged individual capacitors in or on a substrate to form two or more capacitors arranged one in the other or one above the other. In this case, an outer capacitor encloses at least one or a plurality of inner. capacitors or a substantial part of an upper capacitor lies above a lower capacitor. A method for fabricating the arrangement of capacitors also is described.

Abstract: A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.

Abstract: A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the lower portion of the sidewall of the pillar, a second plate as an upper electrode at the periphery of the first plate, a third plate at the periphery of the second plate electrically connected with the first plate to form a lower electrode, and a dielectric layer separating the second plate from the first and third plates. A DRAM array based on the DRAM cell and a method for fabricating the DRAM array are also described.

Abstract: A semiconductor device includes a first semiconductor layer formed above a first region of a supporting substrate with a buried oxide layer disposed therebetween and a second semiconductor layer formed on a second region of the supporting substrate. An interface between the supporting substrate and the second semiconductor layer is placed in substantially the same depth position as the undersurface of the buried oxide layer or in a position deeper than the buried oxide layer.

Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.

Abstract: The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

Abstract: The present invention provides collarless trench semiconductor memory devices having minimized vertical parasitic FET leakage and methods of forming the same.

Abstract: A memory cell, array and device include an active area formed in the substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.

Abstract: The methods and structures of the present invention involve providing a vertical dynamic random access memory (DRAM) cell device comprising a buried strap which can be laterally constrained, thereby maintaining freedom from cross talk, even at 6F2 scaling, in the absence of adjacent Shallow Trench Isolation (STI). The methods and structures of the present invention involve the further recognition that the STI can therefore be vertically confined, freed of any need to extend down below the level of the buried strap. The reduction of the buried strap to 1F width and the concomitant reduction in the depth of the STI together permit a significantly reduced aspect ratio, permitting critically improved manufacturability.

Abstract: A method for forming, within a double well formation, an array of DRAM memory cells isolated from each other by shallow trench isolation (STI), each cell comprising a MOSFET access transistor and a storage trench capacitor. A top plate of said capacitor is the trench wall within a deep N-well portion of the double well and the bottom plate is formed of a doped polysilicon layer within the trench, which layer is partially separated from the trench sidewalls by a dielectric layer whose upper portion is removed to allow the formation of a autodiffused doped channel between said polysilicon plate and the source region of the access transistor. The method uses a single dielectric layer deposition to serve as both a gate dielectric for the MOSFET and a capacitor dielectric and requires only a single deposition of polysilicon to serve as both the transistor gate electrode and a capacitor plate.

Abstract: The invention provides a semiconductor device and a method for manufacturing the same that are capable of improving the product performance and operational efficiency of a cross-point FeRAM, as well as increasing the area of capacitors included in the cross-point FeRAM. An upper electrode supporting layer forming mask for forming an upper electrode supporting layer can be made of a hard mask material. By making use of the upper electrode supporting layer forming mask remaining unremoved in forming and processing a lower electrode layer, prior to forming an upper electrode layer, a region where a ferroelectric capacitor is formed can be made larger than an area occupied by an intersection of the upper electrode layer and the lower electrode layer.

Abstract: A semiconductor device includes a heavily doped layer 25 of p-type formed in the surface of an n-type well 21, an intermediately doped layer 26 of p-type formed to adjoin and surround the heavily p-doped layer 25, and an isolation region 22 formed to surround the heavily p-doped layer 25 and the intermediately p-doped layer 26. The heavily p-doped layer 25 has a higher dopant concentration than the well 21. The intermediately p-doped layer 26 has a higher dopant concentration than the well 21 and a lower dopant concentration than the heavily p-doped layer 25.

Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.

Abstract: A memory device has a plurality of memory cells, wherein each memory cell has a trench capacitor formed in a semiconductor substrate and an access transistor for it. Each access transistor has a first contact region connected to an internal electrode of the trench capacitor, a second contact region to a bit line and a control electrode region, wherein the control electrode regions of neighboring access transistors are connected by a word line formed in the semiconductor substrate.

Abstract: A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

Abstract: On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain field limiting layer and a source/drain region are formed. The one and another MOS transistors are connected in series through the source/drain region common to the two transistors. Accordingly, a semiconductor device can be provided in which increase in pattern layout area is suppressed when elements including a high-breakdown voltage MOS transistor are to be connected in series.

Abstract: A ferroelectric capacitor device, such as an FeRAM device is formed of a substrate having one or more contact plugs extending therethrough, and a first interlayer dielectric layer formed on the substrate. A spacer layer is formed on the first interlayer dielectric layer, a first oxygen barrier layer is formed on the spacer layer and a buffer layer is formed on the first oxygen barrier layer. A layer of liner material is formed on the buffer layer between the buffer layer and the contact plugs and a dielectric layer is sandwiched between a first electrode and a second electrode. A second oxygen barrier layer is applied to the device. The spacer layer should prevent any oxidation from reaching the interface between the liner material and the contact plugs as this interface is located beneath the first oxygen barrier layer. As a result, the electrical contact is not damaged.

Abstract: A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.

Abstract: Afin-type trench capacitor structure includes a buried plate diffused into a silicon substrate. The buried plate, which surrounds a bottle-shaped lower portion of the trench capacitor structure, is electrically connected to an upwardly extending annular poly electrode, thereby enabling the buried plate and the annular poly electrode to constitute a large-area capacitor electrode of the trench capacitor structure. A capacitor storage node consisting of a surrounding conductive layer, a central conductive layer and a collar conductive layer encompasses the upwardly extending annular poly electrode. A first capacitor dielectric layer isolates the capacitor storage node from the buried plate. A second capacitor dielectric layer and a third capacitor dielectric layer isolate the upwardly extending annular poly electrode from the capacitor storage node.

Abstract: Embodiments of the present invention include a method for manufacturing a semiconductor device and a semiconductor device, in which, when a DRAM and a MOS field effect transistor that becomes a component of a logic circuit are mix-mounted on the same chip, the DRAM and the MOS field effect transistor can be provided with designed performances. After a capacitor 700 of the DRAM is formed, silicide layers 19a and 19b are formed over N+ type source/drain regions 41c and 41d of MOS field effect transistors 200c, 200d and 200e that are located in peripheral circuit region 2000 and logic circuit region 3000.

Abstract: The present invention discloses a semiconductor device, comprising: bit line landing pads formed over a semiconductor substrate; storage landing pads formed on both sides of the bit line landing pads; a bit line interlayer insulator formed over the whole surface of the semiconductor substrate having the landing pads; a plurality of parallel bit line patterns arranged on the bit line interlayer insulator; bit line insulating layer patterns filling in gate regions between the bit line patterns; upper contact holes formed in the bit line insulating layer patterns to expose side walls of the bit line patterns and located higher than upper surfaces of the bit line patterns; contact hole spacers covering the side walls of the upper contact holes; lower contact holes penetrating the bit line insulating layer patterns and the bit line interlayer insulator below holes surrounded by the contact hole spacers to expose the storage node landing pads and self-alighed with the upper contact holes; and storage node contact p

Abstract: A capacitor formed in a substrate including a recess dug into a substrate; a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; a second layer of a conductive material covering the first layer; a third layer of a conductive or insulating material filling the recess; trenches crossing the third layer; a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges thereof; a fifth layer of a dielectric material covering the fourth layer; and a sixth layer of a conductive material covering the fifth layer.

Abstract: A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.

Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

Abstract: A method for making a power MOSFET includes forming a trench in a semiconductor layer, forming a gate dielectric layer lining the trench, forming a gate conducting layer in a lower portion of the trench, and forming a dielectric layer to fill an upper portion of the trench. Portions of the semiconductor layer laterally adjacent the dielectric layer are removed so that an upper portion thereof extends outwardly from the semiconductor layer. Spacers are formed laterally adjacent the outwardly extending upper portion of the dielectric layer, the spacers are used as a self-aligned mask for defining source/body contact regions.

Abstract: Storage nodes for semiconductor memory devices may be fabricated by repeatedly forming conductive and insulating spacers on mold oxide layer pattern sidewalls, to thereby obtain fine line patterns which can increase the surface area of the storage node electrodes. Supporters also may be provided that are configured to support at least one freestanding storage node electrode, to thereby reduce or prevent the storage node electrode from falling or bending towards an adjacent storage node electrode.

Abstract: Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. In one embodiment, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors.

Abstract: A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

Abstract: A power divider having metal capacitors is disclosed to detect and divide a frequency signal. The divide includes a first capacitor including first and second electrodes formed at a first portion of a substrate, a second capacitor including first and second electrodes formed at a second portion of the substrate, a first metal line connected to the second electrode of the first capacitor, a second metal line connected to the second electrode of the second capacitor, a poly resistor connected to a contact area of the first capacitor and to a contact area of the second capacitor, and a third metal line connected to the first and second metal lines to divide a signal flown through the first and second metal lines.

Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

Abstract: In a nonvolatile memory cell, the floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.

Abstract: A method of forming a capacitor includes forming first and second capacitor electrodes over a substrate. A capacitor dielectric region is formed intermediate the first and second capacitor electrodes, and includes forming a silicon nitride comprising layer over the first capacitor electrode. A silicon oxide comprising layer is formed over the silicon nitride comprising layer. The silicon oxide comprising layer is exposed to an activated nitrogen species generated from a nitrogen-containing plasma effective to introduce nitrogen into at least an outermost portion of the silicon oxide comprising layer. Silicon nitride is formed therefrom effective to increase a dielectric constant of the dielectric region from what it was prior to said exposing. Capacitors and methods of forming capacitor dielectric layers are also disclosed.