Abstract: A test structure of a DRAM array includes a substrate. A transistor is formed on the substrate and has a first region and a second region as source/drain regions thereof. A deep trench capacitor is formed adjacent to the transistor and has a first width. A shallow trench isolation is formed in a top portion of the deep trench capacitor and has a second width. The second width is substantially shorter than the first one. A third region is formed adjacent to the deep trench capacitor. A first contact is formed on the substrate and contacts with the first region. A second contact is formed on the substrate and contacts with the third region.

Abstract: A semiconductor device having an analog capacitor and a method of fabricating the same are disclosed. The semiconductor device includes a bottom plate electrode disposed at a predetermined region of a semiconductor substrate, and an upper plate electrode having a region overlapped with the bottom plate electrode thereon. The upper plate electrode and the bottom plate electrode are formed of a metal compound. A capacitor dielectric layer is interposed between the bottom plate electrode and the upper plate electrode. A bottom electrode plug and an upper electrode plug are connected to the bottom plate electrode and the upper plate electrode through the interlayer dielectric layer.

Abstract: A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

Abstract: The invention relates to a DRAM memory cell having a trench filled with conductive material connected to a selection transistor by a connection having a vertical insulation collar arranged perpendicularly to a layer sequence of the memory cell. The vertical insulation collar is connected to a lateral insulation collar of the trench. This lateral insulation collar essentially extends perpendicular to the vertical insulation collar or is arranged laterally with respect to the vertical insulation collar. It is thus possible to provide a memory cell, a wafer and a semiconductor component that have a high integration density and a sufficient dielectric strength, and that efficiently suppress parasitic transistors. A method for fabricating a lateral insulating collar for a memory cell is also described.

Abstract: A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

Abstract: A method of patterning a metal surface by electro-mechanical polishing is disclosed. A metal surface is placed in fluid communication with an abrasive surface of a pad. The two surfaces are moved relative to each other, in acidic fluid which contains abrasive particles. An electrical circuit is formed between the metal surface and abrasive pad and a current is supplied to the circuit. The patterned surface then is processed into a useful feature such as a bottom electrode for a DRAM capacitor.

Abstract: A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.

Abstract: A semiconductor device includes a first semiconductor layer formed above a first region of a supporting substrate with a buried oxide layer disposed therebetween and a second semiconductor layer formed on a second region of the supporting substrate. An interface between the supporting substrate and the second semiconductor layer is placed in a position deeper than the buried oxide layer.

Abstract: A method for manufacturing a trench capacitor includes the step of etching a shallow isolation trench in a two-step process flow. During a first etching step, an etch chemistry based on chlorine or bromine performs a highly selective etch for silicon. During a second step, the etch chemistry is based on SiF4 and O2 which rather equally etches polysilicon and the collar isolation. On top of the wafer, the deposition of silicon oxide on the hard mask predominates and avoids an erosion of the hard mask. On the bottom of the trench the conformal etching of polysilicon and collar isolation predominates. The method provides an economic process flow and is suitable for small feature sizes.

Abstract: A semiconductor device includes a group of capacitors and a trench. Each capacitor includes a first conductive material layer, a dielectric layer, and a second conductive material layer. The dielectric layer is located between the first and second conductive material layers. The first conductive material layer coats an inside surface of a cup-shaped opening formed in an insulating layer. The trench is formed in the insulating layer. The trench extends between and crosses each of the capacitors in the group. The dielectric layer and the second conductive material layer are formed over the first conductive material layer in the cup-shaped openings and over an inside surface of the trench. The second conductive material layer extends between the capacitors of the group via the trench. Also, the second conductive material layer forms top electrodes for the capacitors of the group.

Abstract: A method for forming a storage node contact plug of a dynamic random access memory includes forming insulating layers on an overall surface of a semiconductor substrate having a plurality of buried contact plugs, etching the insulating layers down to a top surface of the buried contact plugs to form first contact holes on the buried contact plugs, forming a photoresist pattern on the insulating layers and the first contact holes, etching the insulating layers to form second contact holes on the second insulating layer, and filling the first and second contact holes with conductive material.

Abstract: A semiconductor device comprises a semiconductor substrate having first conductivity type, a trench capacitor, provided in the substrate, having a charge accumulation region, a gate electrode provided on the substrate via a gate insulating film, a gate side wall insulating film provided on a side surface of the gate electrode, drain and source regions, provided in the substrate, having a second conductivity type, an isolation insulating film provided adjacent to the trench capacitor in the substrate to cover an upper surface of the charge accumulation region, a buried strap region having the second conductivity type, the buried strap region being provided to electrically connect an upper portion of the charge accumulation region to the source region in the substrate, and a pocket implantation region having the first conductivity type, the pocket implantation region being provided below the drain and source regions and being spaced apart from the strap region.

Abstract: A non-volatile memory cell is fabricated using a conventional logic process, with minor modifications. The cell is fabricated by forming a shallow trench isolation (STI) region in a well region of a semiconductor substrate. A recessed region is formed in the STI region, wherein the recessed region extends into the STI region and exposes a sidewall region in the well region. A capacitor region is formed in the sidewall region. A dielectric layer is formed over the well region, including the sidewall region. A gate electrode is then formed over the dielectric layer, wherein a portion of the gate electrode extends into the recessed region. An access transistor of the cell is then formed in a self-aligned manner with respect to the gate electrode. A capacitor structure is formed by the gate electrode (in the recessed region), the dielectric layer on the sidewall region, and the capacitor region.

Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

Abstract: A ferroelectric memory comprising a select transistor and a ferroelectric capacitor is characterized in that the ferroelectric capacitor includes a dummy capacitor and a memory capacitor the first electrodes (storage node electrodes) of which are connected to one of the source and drain of the select transistor and which draw the same hysteresis curve, the second electrodes of the dummy capacitor and the memory capacitor are connected to a first plate line and a second plate line, and the potentials of these plate lines are set so as to polarize the dummy capacitor and the memory capacitor in opposite directions to each other with respect to the first electrode.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a first electrically insulating layer having a conductive plug therein, on a semiconductor substrate, and then forming second and third electrically insulating layers of different materials on the first electrically insulating layer. A contact hole is then formed to extend through the second and third electrically insulating layers and expose the conductive plug. Next, a conductive layer is formed in the contact hole and on the third electrically insulating layer. A step is then performed to planarize the conductive layer to define a U-shaped electrode in the contact hole. The third electrically insulating layer is then etched-back to expose upper portions of outer sidewalls of the U-shaped electrode, using the second electrically insulating layer as an etch stop layer. However, the second electrically insulating layer is not removed but is left to act as a supporting layer for the U-shaped electrode.

Abstract: A method for forming, within a double well formation, an array of DRAM memory cells isolated from each other by shallow trench isolation (STI), each cell comprising a MOSFET access transistor and a storage trench capacitor. A top plate of said capacitor is the trench wall within a deep N-well portion of the double well and the bottom plate is formed of a doped polysilicon layer within the trench, which layer is partially separated from the trench sidewalls by a dielectric layer whose upper portion is removed to allow the formation of a autodiffused doped channel between said polysilicon plate and the source region of the access transistor. The method uses a single dielectric layer deposition to serve as both a gate a gate dielectric for the MOSFET and a capacitor dielectric and requires only a single deposition of polysilicon to serve as both the transistor gate electrode and a capacitor plate.

Abstract: Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.

Abstract: In SOI integrated circuits having trench capacitor DRAM arrays, the decreasing thickness of the insulating layer causes cross-talk between the passing wordline traveling over the trench capacitor. Increasing the depth of the recess at the top of the trench and undercutting the insulating layer laterally permits the buried strap from the capacitor center electrode to make contact to the back side of the SOI layer, thereby increasing the vertical separation between the passing wordline and the strap.

Abstract: A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

Abstract: The invention is a storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewall of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is formed in the recess and the top surface of the barrier layer is recessed below the top surface of the oxide or oxide/nitride layer. The process continued with a formation of an oxidation resistant conductive layer and the deposition of a further oxide layer to fill remaining portions of the recess.

Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two- and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

Abstract: A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.

Abstract: Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.

Abstract: A semiconductor memory having memory cells, each memory cell includes a selection transistor and a trench capacitor. The selection transistor is formed in the form of a vertical transistor. In such a case, two word lines are separated only by a connecting channel that enables an electrically conductive connection between a trench filling of the trench capacitor and a bit line.

Abstract: Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.

Abstract: A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.

Abstract: Disclosed are a DRAM cell having independent and asymmetric source/drain regions and a method of forming the same. The DRAM cell has an asymmetric structure in which source junctions are thick and drain junctions are thin. Therefore, the source/drain junctions have an asymmetric configuration via separate ion injection steps independent from each other, thereby preventing leakage current due to punch-through. Also, it is not necessary to form an ion injection layer for restraining punch-through, and a relatively low value of electric field is applied to the junctions to prolong refresh time. Further, the relatively thick spacer can be formed adjacent to the source regions thereby decreasing GIDL and further reducing electric field.

Abstract: A capacitor of a semiconductor device is provided which includes a semiconductor substrate and insulating interlayer formed on the semiconductor substrate. The insulating interlayer has a contact hole which exposes a portion of the semiconductor substrate. A plug fills in the contact hole and the plug comes into contact with the semiconductor substrate. A contact layer is formed on the insulating interlayer. The contact layer comes into contact with the plug. First and second barrier layers are formed on the surface and sides of the contact layer, and a lower electrode is formed on the first barrier layer. A dielectric layer formed on the second barrier layer and lower electrode, and an upper electrode is formed on the dielectric layer.

Abstract: A self-aligned trench-type DRAM structure comprising a self-aligned DRAM capacitor structure and a self-aligned DRAM transistor structure are disclosed by the present invention, in which the self-aligned DRAM capacitor structure comprises a deep-trench capacitor region and a shallow-trench-isolation region being defined by a spacer technique and the self-aligned DRAM transistor structure comprises a scalable gate-stack region and a common-drain region being defined by another spacer technique. The self-aligned trench-type DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized conductive-gate islands and a plurality of common-drain conductive bit-lines.

Abstract: A method of manufacturing an electronic device includes the steps of: (a) preparing a (001) oriented ReO3 layer; and (b) forming a (001) oriented oxide ferroelectric layer having a perovskite structure on the ReO3 layer. Preferably, the step (a) includes the steps of: (a-1) preparing a (001) oriented MgO layer; and (a-2) forming a (001) oriented ReO3 layer on the MgO layer. An electronic device capable of obtaining a ferroelectric layer of a large polarization and a method of manufacturing the same are provided.

Abstract: A method for fabricating a semiconductor device that forms a capacitor and metal interconnection in the same level, simultaneously using a damascene process for forming a metal interconnection. A capacitor structure having the high capacitance needed for logic elements is obtained without increasing the number of layers for fabricating the capacitor by forming a three-dimensional capacitor in the damascene pattern while maintaining the conventional processes in a damascene interconnection process.

Abstract: Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells. Adjacent memory cells are isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual memory cells is less than 8F2, where “F” is no greater than 0.25 micron.

Abstract: A vertical transistor DRAM structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type shallow-trench-isolation region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions being formed under a common-drain diffusion region in another side portion of the deep-trench region. The vertical transistor DRAM structure is, used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated. with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.

Abstract: A semiconductor memory comprises: a substrate; and one or more memory cells constituted of at least one island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate and has an insulating film allowing an electric charge to pass at least in a part of a region between the charge storage layer and the island-like semiconductor layer.

Abstract: A dynamic random access memory cell comprising: a trench capacitor formed in a silicon substrate; a vertical MOSFET formed in a silicon substrate above the trench capacitor, the vertical MOSFET having a gate electrode, a first source/drain region extending from a surface of the silicon substrate into the silicon substrate, a buried second source/drain region electrically contacting the trench capacitor, a channel region formed in the silicon substrate between the first source/drain region and the buried second source/drain region and a gate oxide layer disposed between the gate electrode and the channel region; the first source/drain region also belonging to an adjacent vertical MOSFET, the adjacent vertical MOSFET having a buried third source/drain region electrically connected to an adjacent trench capacitor, the buried second and third source/drain regions extending toward one another; and a punch through prevention region disposed between the buried second and third source/drain regions.

Abstract: A semiconductor memory device includes a conductive layer filling a contact hole, a bottom electrode having a depression and electrically connected to the conductive layer, a dielectric film formed on the bottom electrode along the depression, and a top electrode formed on the dielectric film. The conductive layer and the dielectric film directly contact each other at a top surface of the conductive layer. The conductive layer contains polycrystalline silicon and dopant having a relatively low concentration and the bottom electrode contains polycrystalline silicon and dopant having a relatively high concentration. The semiconductor memory device can thus have a capacitor small in size and still sufficiently large in capacitance.

Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.

Abstract: The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

Abstract: The present invention provides a highly reliable semiconductor device including a silicon substrate, floating gate electrodes with side walls formed on first surface of silicon substrate with a gate insulator film disposed therebetween, first and second side-wall insulator layers formed on side walls and on a portion of first surface, and a nitrogen-containing extending from the portion of silicon substrate that is in the vicinity of second surface to the portion of silicon substrate that is in the vicinity of the interface between first and second side-wall insulator layers and silicon substrate.

Abstract: A self-aligned vertical transistor DRAM structure comprising a self-aligned trench structure and a self-aligned common-drain structure are disclosed by the present invention, in which the self-aligned trench structure comprises a deep-trench capacitor region having a vertical transistor and a second-type shallow-trench-isolation region being defined by a spacer technique and the self-aligned common-drain structure comprises a common-drain region being defined by another spacer technique. The self-aligned vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: In an integrated circuit, particularly an integrated circuit for radio frequency applications, a semiconductor structure for isolation of semiconductor devices that includes a semiconductor substrate, at least one shallow trench extending vertically into the substrate, a deep trench laterally located within the shallow trench, where the deep trench extends vertically further into the substrate. The deep trench is self aligned to the shallow trench with a controlled lateral distance between an edge of the shallow trench and an edge of the deep trench and the lateral extensions of the shallow and deep trenches, respectively, are independently chosen.

Abstract: A vertical one-transistor, floating-body DRAM cell is fabricated by forming an isolation region in a semiconductor substrate, thereby defining a semiconductor island in the substrate. A buried source region is formed in the substrate, wherein the top/bottom interfaces of the buried source region are located above/below the bottom of the isolation region, respectively. A recessed region is etched into the isolation region, thereby exposing sidewalls of the semiconductor island, which extend below the top interface of the buried source region. A gate dielectric is formed over the exposed sidewalls, and a gate electrode is formed in the recessed region, over the gate dielectric. A drain region is formed at the upper surface of the semiconductor island region, thereby forming a floating body region between the drain region and the buried source region. Dielectric spacers are formed adjacent to the gate electrode, thereby covering exposed edges of the gate dielectric.

Abstract: A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.

Abstract: A method for fabricating a semiconductor device and a semiconductor formed by this method, the method including, the steps of sequentially forming a pad oxide film, a polysilicon film, and an antioxidation film on an active region of a semiconductor substrate such that a field region is exposed; etching an exposed portion of the surface of the substrate to a predetermined thickness to form a trench within the substrate; forming a first insulation film along the inner face of the trench by using an oxidation process; forming a stress buffer film on the entire surface of the resultant structure; forming a second insulation film on the stress buffer film such that the trench is sufficiently filled; making the second insulation film planar such that the remaining antioxidation film has a predetermined thickness on the active region of the substrate so as to form a shallow trench isolation within the trench; and sequentially removing the remaining antioxidation film, the polysilicon film, and the pad oxide film.

Abstract: Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.

Abstract: A semiconductor device includes a capacitor formed to have an approximately elliptical cross-sectional shape and extending upwards from upper surface of each said storage node contact. When an arrangement of capacitors is seen vertically from above, rows of capacitors are formed such that, along direction of a major axis of the approximate ellipse, a plurality of capacitors are aligned with regular intervals. When arbitrary one of said capacitor rows is taken as a first capacitor row, a second capacitor row is arranged in parallel therewith, and the capacitors in the first capacitor row and the second capacitor row are aligned out of phase with each other by length corresponding approximately to a sum of width of one transfer gate and width of one space between transfer gates.

Abstract: Within a method for fabricating a capacitor structure, and a capacitor structure fabricated employing the method, there is formed within an isolation region adjoining an active region of a semiconductor substrate a laterally asymmetric trench which leaves exposed an upper sidewall portion of the active region of the semiconductor substrate. There is then formed within the laterally asymmetric trench a capacitor node layer which contacts the exposed upper sidewall portion of the active region of the semiconductor substrate and extends above the active region of the semiconductor substrate. The capacitor may be a storage capacitor with increased capacitance fabricated within a memory cell structure of decreased dimensions.

Abstract: An improved gate structure for a MOSFET device exhibits a reduced level of 1/f noise or “flicker noise”, while maintaining the control of boron penetration into the substrate of the MOSFET device. The gate structure for the MOSFET device includes a gate electrode and a gate oxide layer wherein nitrogen is selectively implanted into the gate oxide/device substrate interface prior to oxidation of the gate oxide layer. The nitrogen is selectively implanted so that the nitrogen is implanted into thin gate oxide regions and masked from thick gate oxide regions so that the benefits of controlling the boron penetration are realized while the 1/f noise is reduced due to the selective implantation of the nitrogen.