Abstract: A semiconductor device comprising a gate having an approximately 0.05 &mgr;m channel length, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the oxide layer; and gate and drain regions on opposite sides of the halo implant and below the oxide layer.

Abstract: An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width.

Abstract: A method of forming a semiconductor device, includes forming at least one conductive island having a predetermined sidewall angle in a conductive substrate, forming a dielectric material over the at least one island, forming a conductive material over the dielectric material, and forming a contact to the conductive material and the at least one island.

Abstract: A semiconductor memory including a ferroelectric gate capacitor structure includes an insulating interlayer formed on the surface of a semiconductor substrate. The insulating interlayer includes a hole at a position corresponding to a channel region. In the channel length direction, the hole extends across the channel region. A ferroelectric gate capacitor structure is formed in the hole. The ferroelectric gate capacitor structure includes a dielectric film, ferroelectric film, and upper electrode formed in this order from the substrate side.

Abstract: Methods for forming materials containing both zirconium and platinum, such as platinum-zirconium films, and articles containing such materials. The resultant films can be used as electrodes in an integrated circuit structure, particularly in a memory device such as a ferroelectric memory device. The platinum-zirconium materials can also be used in catalyst materials.

Abstract: A method for passivating surface states in an integrated circuit structure having a gate conductor with a gate dielectric layer. The method comprises the step of fabricating a solid state source of fluorine in close proximity to the gate dielectric layer. In addition, an integrated circuit structure is provided. The structure comprises a substrate having a gate dielectric layer on the substrate and a gate conductor on the substrate above the gate dielectric layer. The gate conductor further comprises an edge and a solid state source of fluorine in close proximity to the gate dielectric layer.

Abstract: In a SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method, a multilayer barrier layer with a potential barrier and a diffusion barrier is used to reliably prevent diffusion of impurities between element layers. This allows semiconductor circuits to be produced with smaller structure sizes and with a higher integration density.

Abstract: A p type well region, a field insulation film, a gate insulation film, and a gate-use poly-Si layer are formed on the surface of a silicon substrate, after which a laminate of a silicon nitride layer and a resist layer is used as a mask in ion implantation, which forms a low-concentration source region, Source contact region, drain region, and drain contact region. Side spacers are formed on both side walls of the gate-use poly-Si layer, after which the laminate of the gate-use poly-Si layer, the side spacers, and the gate insulation film is used along with the field insulation film as a mask to perform ion implantation via the silicon nitride layer, which forms a high-concentration source region and drain region. After a silicide conversion treatment, the unreacted metal is removed, which forms a silicide layer.

Abstract: A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.

Abstract: A depression extends from a main surface of the substrate to the inside of said substrate and has an upper area and an adjacent lower area. A cross-section of the upper area, parallel to the main surface, is provided with at least one corner. A cross-section of the lower area, parallel to the main surface, matches the cross-section of the upper area, particularly in the vicinity the upper area, with the following difference: each corner is rounded, whereby the cross section of the lower area is smaller than the cross-section of the upper area. In order to produce the indentation, the upper area is provided with an auxiliary spacer that is rounded by isotropic etching. The lower area is produced by selectively etching the substrate to form an auxiliary spacer.

Abstract: A trench capacitor for use in a semiconductor memory cell is formed in a substrate. The trench capacitor includes a trench having an upper region and a lower region, an insulation collar formed in the upper region on a trench wall of the trench, and a buried well, through which the lower region of the trench at least partly extends. The trench capacitor further includes, as an outer capacitor electrode, a conductive layer lining the lower region of the trench and the insulation collar, a dielectric layer lining the conductive layer, and a conductive trench filling which is filled into the trench as an inner capacitor electrode. A method of fabricating a trench capacitor is also provided.

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

Abstract: A technology of preventing the threshold voltage of the transistor of a cell region from increasing and the refresh characteristic of the transistor of the cell region from deteriorating, while maintaining the characteristic of the transistor of core circuit/peripheral circuit regions of a semiconductor memory device, is provided. A semiconductor memory device comprises a first transistor comprised of a first gate, a first gate insulating film, a first source region, and a first drain region formed in core circuit/peripheral circuit regions of a semiconductor memory device having a cell region and core circuit/peripheral circuit regions, a planarized interlayer dielectric film which covers the first transistor, and a second transistor formed in the cell region, including a second source region, a second drain region, a second gate having a height corresponding to the height of the interlayer dielectric film, and a second gate insulating film.

Abstract: The invention includes buried bit line memory circuitry, methods of forming buried bit line memory circuitry, and semiconductor processing methods of forming conductive lines. In but one implementation, a semiconductor processing method of forming a conductive line includes forming a silicon comprising region over a substrate. A TiNx comprising layer is deposited over the silicon comprising region, where “x” is greater than 0 and less than 1. The TiNx comprising layer is annealed in a nitrogen containing atmosphere effective to transform at least an outermost portion of the TiNx layer over the silicon comprising region to TiN. After the annealing, an elemental tungsten comprising layer is deposited on the TiN and at least the elemental tungsten comprising layer, the TiN, and any remaining TiNx layer is patterned into conductive line. In one implementation, a method such as the above is utilized in the fabrication of buried bit line memory circuitry.

Abstract: A container capacitor having a recessed conductive layer. The recessed conductive layer is typically made of polysilicon. The recessed structure reduces the chances of polysilicon “floaters,” which are traces of polysilicon that remain on the surface of the substrate, coupling adjacent capacitors together to create short circuits. The disclosed method of creating such a recessed structure uses successive etches. One of these etches selectively isolates a rim of the polysilicon within the container to recess the rim, while the remainder of the polysilicon in the container is protected by photoresist.

Abstract: A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a metallic storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. Preferably, the trench has an aspect ratio of greater than 50. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness.

Abstract: A trench capacitor has an insulation collar that is formed non-conformally in the upper region of a trench in such a way that a layer thickness in an upper section of the insulation collar is greater than a layer thickness in a lower section of the insulation collar. This results in a trench capacitor having improved leakage current properties. A simplified and cost-effective method of fabricating a trench capacitor is also provided.

Abstract: A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.

Abstract: A method of forming a pair of capacitors having a common capacitor electrode includes forming a pair of spaced first capacitor electrodes within insulating material. The first electrodes have uppermost surfaces which are below an uppermost surface of the insulating material. Some of the insulating material is removed about the first capacitor electrodes and a path is provided within the insulating material lower than its uppermost surface between the spaced first electrodes. A capacitor dielectric layer is formed over the first capacitor electrodes. A second capacitor electrode layer is formed over the capacitor dielectric layer common to the spaced first capacitor electrodes and within the path. A method of forming DRAM circuitry includes forming an array of capacitor storage node electrodes over a substrate. A capacitor cell plate pattern is formed over the substrate. Conductive material is deposited over the substrate and into the capacitor cell plate pattern.

Abstract: A scalable vertical DRAM cell structure comprising a scalable trench region and a self-aligned common-drain diffusion region are disclosed by the present invention, in which the scalable trench region comprises a deep-trench region having a vertical transistor and a second-type STI region being defined by a spacer technique. The scalable vertical DRAM cell structure can offer a DARM cell size equal to or smaller than 4F2 and is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands over common-gate conductive connector islands and a plurality of common-drain conductive bit-lines.

Abstract: An image sensor capable of preventing the degradation of pinned photodiodes and the generation of leakage current between neighboring pinned photodiodes is provided. The disclosed image sensor contains a plurality of pixel units, each pixel unit having a photodiode region. The image sensor includes a semiconductor substrate of a first conductivity type; a device isolation layer formed in the semiconductor substrate; a field stop layer formed beneath the device isolation layer; a trench formed in the semiconductor substrate, wherein the trench surrounds the photodiode region; a first doping region of the first conductivity type formed beneath the surface of the semiconductor substrate and beneath the surfaces of the trench; an insulating member filling the trench; and a second doping region of a second conductivity type formed in the semiconductor substrate under the first doping region.

Abstract: The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.

Abstract: In a semiconductor device and method of manufacturing thereof, a semiconductor device having an SOI structure is provided with a capacitor including a first electrode in an SOI layer, a second electrode opposing the first electrode, and a dielectric film therebetween. An isolation region is provided as contained in the SOI layer to electrically isolate the first electrode from remaining areas of the SOI layer, such as active areas or the like. The method includes forming the isolation regions in the SOI layer, forming the first electrode in the SOI layer as electrically isolated from the remaining areas of the SOI layer by the isolation regions, forming the dielectric film on the first electrode, and forming the second electrode on the dielectric film opposite the first electrode.

Abstract: An asymmetric multilevel memory cell provides an inhibited source read current. The inhibited source read current dramatically reduces the likelihood of a cell type misread error for a memory array comprising multilevel cells. The method for fabricating the asymmetric multilevel memory cell comprises a source only implant, formation of a spacer on the drain side of the gate prior to source/drain implant, and the resultant formation of an offset region disposed between the channel and the drain. The offset region is not controlled by the gate voltage. The drain current at 1.5 volts is more than 3.5 times larger than the source current at 1.5 volts for spacer width of 0.12 micrometers. Asymmetric multilevel memory cells in a memory array, where the cells have a common source configuration, are accurately read in one direction because neighboring cells on the word line have substantially lower source current than the read cell drain current.

Abstract: MOS transistors are formed on island-shaped divided element regions of a silicon substrate, and provided with gate electrodes having the same widths as the element regions. Thereafter, capacitor grooves are formed at end portions of the element regions, and capacitor insulating films formed of BSTO are provided on inner walls of the capacitor grooves. Then, the capacitor grooves are filled with storage electrodes, thereby forming capacitors. Furthermore, connection conductors are formed to connect the storage electrodes and source diffusion layers of the MOS transistors. Then, word lines are formed to connect the gate electrodes of the MOS transistors, and further bit lines are formed to connect drain diffusion layers of the MOS transistors.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.

Abstract: A field oxide film is provided in the surface of a semiconductor substrate. An interlayer insulating film is provided on the semiconductor substrate so as to cover an active layer. A contact hole exposing the surface of the active layer is provided in the interlayer insulating film. A conductor fills the contact hole so as to be electrically connected to the surface of the active layer. The end portion of the field oxide film has a surface perpendicular with respect to the surface of the semiconductor substrate. As a result, a dynamic random access memory can be obtained which is improved so that leakage current is reduced, which in turn increases a hold time of information.

Abstract: A method and structure for a dynamic random access device which includes a substrate having a trench, a conductor in the trench, a transistor adjacent the trench and a conductive strap electrically connecting the conductor and the transistor, wherein the strap comprises a plurality of strap conductors and the strap has a lower resistance than the conductor. The conductor comprises a first material having a first resistance and the strap comprises a second material different than the first material having a second resistance, wherein the second resistance is lower than the first resistance. The plurality of strap conductors comprises at least two electrically connected strap conductors, and a first strap conductor is adjacent the conductor and a second strap conductor is adjacent the transistor and the first strap conductor has an improved interface with the conductor. The strap comprises a lip strap, wherein the strap forms an L-shape.

Abstract: A method and structure for a DRAM device which includes a trench within an insulator, a conductor within the trench, a transistor adjacent a first side of the trench, and a shallow trench isolation region formed within a top portion of the conductor on a second side of the trench, opposite the first side, wherein the top portion of the conductor has a curved shape at an edge of the shallow trench isolation region. The curved shape comprises a conductive strap and electrically connects the conductor and the single crystal where the transistor is formed, further comprising a collar oxide surrounding the top portion of the conductor, the collar oxide controlling a shape and location of the curved shape. The curved shape is formed by hydrogen annealing, and may be convex, or concave. The DRAM further comprising a collar oxide extending into the shallow trench isolation region on the second side.

Abstract: A dynamic random access memory includes memory cells arranged in rows and columns on the substrate and a plurality of connecting pillars, each associated with a memory cell. A bit line extends above the main area of the substrate and connects to each memory cell of a column. A first word line connects a first set of alternate memory cells of a row by a first subset of the plurality of connecting pillars. The first word line includes first parts arranged offset relative to the first subset of connecting pillars. A strip-shaped second part extends above the main area and adjoins the first parts of the first word line. A second word line connects to a second set of alternate memory cells of the row by a second subset of the connecting pillars. The second word line includes first parts arranged between mutually adjacent first word lines and offset from the second subset of the connecting pillars. Both the first and second word lines thus overlap but do not cover the connecting pillars.

Abstract: A conductive plug is formed in an interlayer insulation film and on an isolating layer which isolates semiconductor elements on a semiconductor substrate. The conductive plug electrically connects a pair of active regions of the semiconductor elements formed on the different sides of the isolating layer. Alternatively, a conductive plug is formed in an interlayer insulation film and on a conducive line formed on an isolating layer which isolates semiconductor elements on a semiconductor substrate. The conductive plug electrically connects the conductive line and an active region of the semiconductor element.

Abstract: An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width.

Abstract: A method of forming a fill layer over a layer in a semiconductor stack having gaps of high aspect ratio topography, and products produced thereby.

Abstract: Systems, devices, structures, and methods are described that inhibit dielectric degradation in the presence of contaminants. An enhanced capacitor in a dynamic random access memory cell is discussed. The enhanced capacitor includes a first electrode, a dielectric coupled to the first electrode, a second electrode coupled to the dielectric, and at least one inhibiting layer that couples to the first electrode, the dielectric, and the second electrode. The inhibiting layer defines a chamber that encloses the capacitor and renders the capacitor impervious to disturbance in its physical or chemical forces in the presence of contaminants. The inhibiting layer includes a nitride compound, an oxynitride compound, and an oxide compound. In one embodiment, the nitride compound includes SixNy. In another embodiment, the oxynitride compound includes SiOxNy. In another embodiment, the oxide compound includes Al2O3 and (SrRu)O3. The variables x and y are indicative of a desired number of atoms.

Abstract: An improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the adjacent isolation structure. An exemplary semiconductor device incorporating the new junction includes a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to LOCOS steps to create active areas bounded by a region of field oxide. An insulated gate electrode is formed over an anive area on the substrate, which has been doped to a first conductivity type. A contact region comprising a portion of the active area extends laterally between one side of the gate electrode and the field oxide region.

Abstract: A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrically insulative layer over the cell plate; c) providing a layer of semiconductive material on the insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; d) patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; e) filling the isolation trenches with insulative material; f) providing capacitor openings through the SOI layer and insulative layer into the cell plate substrate; g) providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; h) providing respective capacitor storage nodes over the dielectric layer within the capacitor openings, the respective storage nodes being in ohmic connection with the SOI layer; i) after providing the storage nodes, filling any remaining portions of the capacitor cont

Abstract: A process for forming an oxide layer on a sidewall of a trench in a substrate. The process comprises the steps of forming the trench in the substrate, forming a nitride interface layer over a portion of the trench sidewall, forming an amorphous layer over the nitride interface layer, and oxidizing the amorphous layer to form the oxide layer. The process may be used, for example, to form a gate oxide for a vertical transistor, or an isolation collar. The invention also comprises a semiconductor memory device comprising a substrate, a trench in the substrate having a sidewall, an isolation collar comprising an isolation collar oxide layer on the trench sidewall in an upper region of the trench, and a vertical gate oxide comprising a gate oxide layer located on the trench sidewall above the isolation collar.

Abstract: An improved gate structure for a MOSFET device exhibits a reduced level of 1/f noise or “flicker noise”, while maintaining the control of boron penetration into the substrate of the MOSFET device. The gate structure for the MOSFET device includes a gate electrode and a gate oxide layer wherein nitrogen is selectively implanted into the gate oxide/device substrate interface prior to oxidation of the gate oxide layer. The nitrogen is selectively implanted so that the nitrogen is implanted into thin gate oxide regions and masked from thick gate oxide regions so that the benefits of controlling the boron penetration are realized while the 1/f noise is reduced due to the selective implantation of the nitrogen.

Abstract: A power semiconductor device includes a die having a drain contact, a source contact, a primary gate contact, a partitioning region that partitions the source contact, and a secondary gate contact disposed in the partitioning region. A conductive strip is connected to the primary and secondary gate contacts. An insulation layer encloses a segment of the conductive strip. A conductive connecting member includes a metal sheet and a conductive paste. The metal sheet is attached to the source contact via the conductive paste and is formed with a groove to expose the insulation layer from the metal sheet.

Abstract: A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.

Abstract: The memory configuration has memory cells each with a selection transistor and a trench capacitor. The storage electrode is formed by a substrate region along the trench wall. A cell plate that forms a common opposing electrode for a number of memory cells lies inside the trench. The cell plate is structured in strips on the surface of the substrate. The strips can run parallel to the direction of cell rows or enclose a defined angle (other than zero) with this direction. The arrangement in the form of strips halves the minimum structure width in the region of the cell plate.

Abstract: Provided are a method of manufacturing a stacked capacitor with which it is easy to fabricate even when a noble metal such as platinum is used for a lower electrode, and a stacked capacitor which can suppress a chemical reaction between a dielectric film or a sidewall lower electrode and a conductive plug. The method comprises the steps of: forming an insulating film (4); forming a film to be etched on the insulating film (4); forming a pattern for a lower electrode core (5A) which extends through the film to be etched and the insulating film (4) and extends to part of a conductive plug (3); burying a material for the lower electrode core (5A) into the pattern; burying a top insulating film (6A) and removing the film to be etched; depositing a material for a sidewall lower electrode (7A) and performing an etch back; and forming a dielectric film (8) and upper electrode (9).

Abstract: A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness.

Abstract: A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench.

Abstract: A barrier metal film of a metal whose conductivity will not be lost when the metal is oxidized or of a conductive metal oxide and a conductive wiring film of copper or a copper alloy are sequentially formed on a semiconductor substrate with an insulating film interposed therebetween.

Abstract: A semiconductor memory comprises: a fist conductivity type semiconductor substrate and one or more memory cells constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate.

Abstract: A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.

Abstract: A pair of dynamic random access memory cells having each end of the active area surrounded on three sides by a gate conductor. The width of each end of the active area that is surrounded by a gate conductor preferably is less than fifty percent of the width of the deep trench intersected by that end of the active area.

Abstract: A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.

Abstract: The present invention provides a trench capacitor, particularly for use in a semiconductor memory cell (100), having an isolation collar (168) with a trench (108) formed in a substrate (101); said isolation collar (168) formed in the upper region of said trench (108); an optional buried plate (165) in said substrate region surrounding said lower region of said trench (180) as a first capacitor plate; a dielectric layer (164) for lining said lower region of said trench (108) and said isolation collar (168) as capacitor dielectric; and a conductive second fill material (161) filled in said trench (108) as a second capacitor plate; wherein said diameter of said lower region of said trench (108) is at least equal to said diameter of said upper region of said trench (108). Moreover, the invention provides a corresponding manufacturing method.