Abstract: A phase change memory device includes a lower electrode and a porous dielectric layer having fine pores on the lower electrode. A phase change layer is provided in the fine pores of the porous dielectric layer. An upper electrode is provided on the phase change layer. Related manufacturing methods are also described.

Abstract: A semiconductor device with having a MOS varactor and methods of fabricating the same are disclosed. The MOS varactor includes a metal gate electrode, an active semiconductor plate interposed between the metal gate electrode and the semiconductor substrate, and a capacitor dielectric layer interposed between the metal gate electrode and the active semiconductor plate. Further, a lower insulating layer insulates the MOS varactor from the semiconductor substrate. According to the present invention, a metal gate electrode is used to reduce poly depletion, thereby increasing a tuning range of the varactor, and to manufacture a reliable metal resistor without the need of an additional photomask.

Abstract: Nanotube on gate FET structures and applications of such, including n2 crossbars requiring only 2n control lines. A non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and a channel region of a second semiconductor type of material disposed between the source and drain region. A gate structure is made of at least one of semiconductive or conductive material and is disposed over an insulator over the channel region. A control gate is made of at least one of semiconductive or conductive material. An electromechanically-deflectable nanotube switching element is in fixed contact with one of the gate structure and the control gate structure and is not in fixed contact with the other of the gate structure and the control gate structure. The device has a network of inherent capacitances, including an inherent capacitance of an undeflected nanotube switching element in relation to the gate structure.

Abstract: A display device and a method of fabricating the same, the display device including a first substrate having a display region, a light emitting layer disposed within the display region, a first voltage pad disposed outside the display region, on the first substrate outside of the display region and supplying a predetermined voltage to the display region, a second substrate provided above the first substrate and corresponding to the display region, a second voltage pad disposed on a surface of the first or second substrate provided opposite to a direction of light emitted from the light emitting layer and a flexible film electrically connecting the first voltage pad and the second voltage pad.

Abstract: Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor is coupled to the bit line. The first pass transistor has a first diffusion structure configured to provide a breakdown voltage higher than that of a second diffusion structure. One or more second pass transistor(s) are coupled to the first pass transistor. The second pass transistor(s) have the second diffusion structure. The second diffusion structure may have a resistance smaller than a resistance of the first diffusion structure.

Abstract: A semiconductor device comprises varactor regions Va and transistor regions Tr. An active region for a varactor is formed with a substrate contact impurity diffusion region obtained by doping an N well region with N-type impurity at a relatively high concentration. However, any extension region (or LDD region) as in a varactor of a known semiconductor device is not formed in the active region for a varactor. On the other hand, parts of a P well region located to both sides of the polysilicon gate electrode in the transistor region Tr are formed with high-concentration source/drain regions and extension regions. Therefore, the extendable range of a depletion layer is kept wide to extend the capacitance variable range of the varactor.

Abstract: A tunable element in the microwave frequency range is described that may include one or more tunable elements that are directly digitally controlled by a digital bus connecting a digital control circuit to each controlled element. In particular, each digital signal is filtered by a digital isolation technique so that the signal reaches the tunable elements with very low noise. The low noise digital signals are then converted to analog control voltages. The direct D/A conversion is accomplished by a special D/A converter which is manufactured as an integral part of a substrate. This D/A converter in accordance with the invention may consist of a resistor ladder or a directly digitally controlled capacitor. The direct digitally controlled capacitor may be a cantilevered type capacitor having multiple separate electrodes or sub-plates representing binary bits that may be used to control the capacitor.

Abstract: A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator is comprised of amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate.

Abstract: A semiconductor device has a capacitive element including a first conductive film formed on the bottom and wall surfaces of an opening formed in an insulating film on a substrate, a dielectric film formed on the first conductive film, and a second conductive film formed on the dielectric film. The dielectric film of the capacitive element is crystallized. The first and second conductive films are made of a polycrystal of an oxide, a nitride or an oxynitride of a noble metal.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: A voltage-controlled oscillator (VCO) circuit includes first, second, third, and fourth transistors, each with a first terminal, a second terminal, and a control terminal. The first terminal of the first transistor communicates with the first terminal of the second transistor. The control terminals of the third and fourth transistors communicate with the second terminals of the first and second transistors, respectively. The first terminals of the third and fourth transistors communicate with the control terminals of the first and second transistors, respectively. First ends of first and second capacitances communicate with the second terminals of the first and second transistors, respectively. Second ends of the first and second capacitances communicate with the control terminals of the first and second transistors, respectively.

Abstract: A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least one common type of atoms for allowing the first and second hydrogen barrier films to adhere to each other.

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P? pocket regions 17 and N? pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P? pocket regions 17 and the N? pocket regions 27.

Abstract: A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P31 pocket regions 17 and N31 pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P31 pocket regions 17 and the N31 pocket regions 27.

Abstract: A micro-electro mechanical system (MEMS) variable capacitor (varactor) generally includes a substrate (102), a first capacitive plate (112) formed on the substrate, a flexible structure (150) coupled to the substrate, a second capacitive plate (116) and a first electrode (122) formed on the flexible structure; a package seal (104) coupled to the substrate and having a second electrode (106) formed thereon, wherein the distance between the first capacitive plate and the second capacitive plate (and hence, the capacitance of the structure) is responsive to a bias voltage applied to the electrodes.

Abstract: A semiconductor device is arranged so as to include (i) a wire L1, connected directly to an LSI chip, which serves as a VGL wire for supplying a voltage VGL to the LSI chip, and (ii) a wire LB1 connected not directly to but to one of a pair of electrodes of a capacitor provided between the wire LB1 and a voltage VGH wire, each of the wire L1 and the wire LB1 including a voltage input terminal. This arrangement provides (i) a semiconductor device, including a built-in capacitor, which makes it possible to shorten time required in an electrical screening test (final test) so as to reduce cost, and (ii) an electrical inspection method of the semiconductor device.

Abstract: In a manufacturing method for a piezoelectric actuator a first electrode layer is formed on substrate, a ferroelectric thin film is formed on the first electrode layer, and an inorganic protective layer 4 is formed on the ferroelectric thin film. Then, the inorganic protective layer 4 and the ferroelectric thin film are heat-treated under an oxygen containing atmosphere, and a second electrode layer is formed on an oxidation diffusion layer, wherein the oxidation diffusion layer is formed on a surface of the ferroelectric thin film as a result of component diffusion of the ferroelectric thin film and oxidation of the inorganic protective layer 4 due to the heat treatment. By using this method, it is possible to improve ferroelectricity without deterioration or cracking of a surface of the ferroelectric thin film.

Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P? well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P? well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

Abstract: The present invention provides a MOS-type variable capacitance element which can obtain a sufficient capacitance valuable width and, at the same time, can eliminate restrictions imposed on a control voltage range.

Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Abstract: A semiconductor varactor with reduced parasitic resistance. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer (50) over the well regions (20) is a further embodiment to reduce the parasitic resistance.

Abstract: A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.

Abstract: A semiconductor integrated circuit device is provided, in which a node from which an output signal of a level shifter is sent can be initialized such that the potential thereof be set at a desired logic level at the time of power supply. The semiconductor integrated circuit device includes a level shifter 6 and two capacitors N10 and C0. The level shifter 6 receives an input signal and converts the received signal to a signal having a voltage amplitude greater than that of the received signal, then to provide the signal to a node D3. The capacitor N10 is connected to the node D3, and the capacitor C0 is connected in series with the capacitor N10. The capacitor N10 is formed of a MOS transistor having a gate connected to the node D3 and a source and a drain both connected to the capacitor C0.

Abstract: A device (2) with a switchable capacitance comprises a first and a second electrode (12, 20) facing each other, a dielectric layer (14) between a first and a second capacitor electrode (12, 20), and a switching member (18) between the second electrode (20) and the dielectric layer (14), the switching member (18) comprising a switching material reversibly switchable between a lower conductivity state and a higher conductivity state, each of the lower conductivity state and the higher conductivity state being persistent, wherein the capacitance of the device (2) depends on the conductivity state of the switching material.

Abstract: A varactor is provided. The varactor includes a second type substrate, two gate structures, a first type doped region and a second type doped region. The two gate structures are disposed over the substrate, and each of the gate structures includes an inter-gate dielectric layer and a gate conductive layer. The first type doped region is disposed in the substrate between the two gate structures. The second type doped region is disposed in the substrate at a side of the two gate structures apart from the first type doped region. The first type doped region is electrically connected to a first electrode, and second type doped region is electrically connected to a second electrode, and the two gate structures are electrically connected to the first electrode or the second electrode.

Abstract: A tunable element in the microwave frequency range is described that may include one or more tunable elements that are directly digitally controlled by a digital bus connecting a digital control circuit to each controlled element. In particular, each digital signal is filtered by a digital isolation technique so that the signal reaches the tunable elements with very low noise. The low noise digital signals are then converted to analog control voltages. The direct D/A conversion is accomplished by a special D/A converter which is manufactured as an integral part of a substrate. This D/A converter in accordance with the invention may consist of a resistor ladder or a directly digitally controlled capacitor. The direct digitally controlled capacitor may be a cantilevered type capacitor having multiple separate electrodes or sub-plates representing binary bits that may be used to control the capacitor.

Abstract: An object of this invention is to provide a pn-varactor having a small resistance and capable of coinciding with incorporation of a circuit employing LC resonance into an integrated circuit. A dummy gate pattern 4 is formed over a n-well 1 in a semiconductor wafer and then p+ diffusion regions 2, 3 are formed on both sides with the dummy gate pattern 4 as inhibition mask. For the purpose, a control voltage VT higher than potentials of the p+ diffusion regions 2, 3 is applied to the n-well 1. Consequently, both the pn-junction between the n-well 1 and the p+ diffusion region 2 and the pn-junction between the n-well 1 and the p+ diffusion region 3 act as a pn-varactor whose capacity is changed by the control voltage VT. If an end dummy pattern is provided on both sides or around the p+ diffusion regions 2, 3, imbalance in capacity due to deflection in position is prevented.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: A non-volatile memory, which comprises an insulating substrate (11) that has a first electrode (18) that extends through the substrate from the front surface to the rear surface thereof; a second electrode (13) that is formed on one side of the insulating substrate (11); and a recording layer (12) that is clamped between the first electrode (18) and the second electrode (13) and whose resistance value varies when an electric pulse is applied across the first electrode (18) and the second electrode (13); wherein the insulating substrate (11) has a layered structure composed of an organic dielectric thin film (112) and an inorganic dielectric layer (111) that is thinner than the organic dielectric thin film (112); with the recording layer (12) being formed on the side on which the inorganic dielectric layer is formed. Use of this non-volatile memory increases the possible number of data writing cycles while saving power.

Abstract: Micro-Electro-Mechanical System (MEMS) Variable Capacitor Apparatus and Related Methods. According to one embodiment, a MEMS variable capacitor is provided. The variable capacitor can include first and second electrodes being spaced apart, and at least one of the electrodes being movable when a voltage is applied across the first and second electrodes. The variable capacitor can also include a first conductive plate attached to and electrically isolated from the first electrode. Furthermore, the variable capacitor can include a second conductive plate attached to the second electrode and spaced from the first conductive plate for movement of at least one of the plates with respect to the other plate upon application of voltage across the first and second electrodes to change the capacitance between the first and second plates.

Abstract: A method of forming a capacitor includes forming first and second capacitor electrodes over a substrate. A capacitor dielectric region is formed intermediate the first and second capacitor electrodes, and includes forming a silicon nitride comprising layer over the first capacitor electrode. A silicon oxide comprising layer is formed over the silicon nitride comprising layer. The silicon oxide comprising layer is exposed to an activated nitrogen species generated from a nitrogen-containing plasma effective to introduce nitrogen into at least an outermost portion of the silicon oxide comprising layer. Silicon nitride is formed therefrom effective to increase a dielectric constant of the dielectric region from what it was prior to said exposing. Capacitors and methods of forming capacitor dielectric layers are also disclosed.

Abstract: A semiconductor capacitor device has two pairs of first and second MIM capacitors on a semiconductor substrate. The paired first and second MIM capacitors include respective capacitor dielectric films having different compositions. Also, the paired first and second MIM capacitors are connected in inverse parallel fashion, with an upper electrode of the first MIM capacitor being connected with a lower electrode of the second MIM capacitor and with a lower electrode of the first MIM capacitor being connected with an upper electrode of the second MIM capacitor. Furthermore, the two first MIM capacitors are electrically connected in inverse parallel with each other, and the two second MIM capacitors are also electrically connected in inverse parallel with each other. This arrangement facilitates mutual counteraction of the voltage dependences of the two pairs of first and second MIM capacitors so as to make the voltage dependence of the capacitance of the capacitor device small.

Abstract: A PN-junction varactor includes a first ion well of first conductivity type formed on a semiconductor substrate of second conductivity type. A first dummy gate is formed over the first ion well. A first gate dielectric layer is formed between the first dummy gate and the first ion well. A second dummy gate is formed over the first ion well at one side of the first dummy gate. A second gate dielectric layer is formed between the second dummy gate and the first ion well. A first heavily doped region of the second conductivity type is located in the first ion well between the first dummy gate and the second dummy gate. The first heavily doped region of the second conductivity type serving as an anode of the PN-junction varactor.

Abstract: A semiconductor device having an analog capacitor and a method of fabricating the same are disclosed. The semiconductor device includes a bottom plate electrode disposed at a predetermined region of a semiconductor substrate, and an upper plate electrode having a region overlapped with the bottom plate electrode thereon. The upper plate electrode and the bottom plate electrode are formed of a metal compound. A capacitor dielectric layer is interposed between the bottom plate electrode and the upper plate electrode. A bottom electrode plug and an upper electrode plug are connected to the bottom plate electrode and the upper plate electrode through the interlayer dielectric layer.

Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

Abstract: An integrated, tunable capacitor has terminal regions that extend significantly deeper into the semiconductor body than the customary source/drain terminal regions in the conventional CMOS varactors. For this purpose, by way of example, well-type regions or collector deep implantation regions may be provided, with which the depleted regions occurring in the event of large tuning voltages extend significantly further into the semiconductor body. The varactor with a large tuning range can be produced without additional outlay in mass production methods and can be used, for example, in phase-locked loops.

Abstract: In a structure of a radio frequency (RF) variable capacitor having a variable range of capacitance between a first minimum value and a first maximum value, and a method of manufacturing the structure, the structure includes a first capacitor, which has a variable range of capacitance between a second minimum value greater than the first minimum value and a second maximum value greater than the first maximum value, and a second capacitor, which is connected in series to the first capacitor and has a capacitance of a fixed value. By the structure and method, a quality factor of a radio frequency (RF) variable capacitor may be increased without adding complex processing steps.

Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P? well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P? well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

Abstract: A charge control circuit for controlling a micro-electromechanical device having a variable capacitance is disclosed. In one embodiment, a charge storage device is configured to store a charge amount. A switch circuit is configured to control the variable capacitance of the micro-electromechanical device by sharing the charge amount between the charge storage device and the micro-electromechanical device to equalize the charge storage device and the micro-electromechanical device to a same voltage.

Abstract: In one embodiment, a varactor includes a first node and a second node. The varactor includes: at least one first varactor element including a source, a drain, and a p-type doped gate; at least one second varactor element including a source, a drain, and an n-type doped gate; and at least one third varactor element including a source, a drain, and an intermediately doped gate, the intermediately doped gate having doping characteristics intermediate to doping characteristics of the p-type and n-type gates. The varactor includes one or more wells in a substrate region underlying the first, second, and third varactor elements. The first, second, and third varactor elements are coupled in parallel between the first and second nodes.

Abstract: A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.

Abstract: The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.

Abstract: A parallel-plate, voltage-variable capacitor is designed to have an increased current conducting perimeter relative to its area. In one approach, the perimeter is increased by changing the shape of the plates. In another approach, the varactor is implemented by a number of disjoint plates, which are coupled in parallel.

Abstract: A single-poly EEPROM cell is disclosed with a vertically formed metal-insulator-metal (MIM) coupling capacitor, which serves as a control gate in place of a laterally buried control gate thereby eliminating the problem of junction breakdown, and at the same time reducing the size of the cell substantially. A method of forming the single-poly cell is also disclosed. This is accomplished by forming a floating gate over a substrate with an intervening tunnel oxide and then the MIM capacitor over the floating gate with another intervening dielectric layer between the top metal and the lower metal of the capacitor where the latter metal is connected to the polysilicon floating gate.

Abstract: A simple metal dielectric semiconductor (MDS) variable capacitor which may be a MOS capacitor uses the drain and source of a floating gate metal dielectric semiconductor field effect transistor connected to the bulk of the semiconductor substrate as one plate of the capacitor and the gate of the transistor as the other plate. The capacitance is voltage dependent and is strongly nonlinear in the depletion region. The accumulation and strong inversion regions are also nonlinear, but to a much smaller degree. The nonlinearity can be significantly reduced by connecting two of the capacitors in series. This series connection also makes possible a capacitor structure with an isolated floating gate connecting the two series capacitors. The charge on the floating gate can be controlled by tunneling and injection to vary the capacitor bias voltage and thus, its capacitance. Alternatively, the capacitors may operate in the accumulation region.

Abstract: In a multi-terminal MOS varactor, a floating electrode 8 of a MOS capacitor (Cf) 5 is connected to one of two terminals of each of a plurality of capacitors (C1-Cn) 6-1 through 6-n. To the other terminals (Vg1-Vgn) 9-1 through 9-n of the respective capacitors (C1-Cn) 6-1 through 6-n, control voltages Vg1-Vgn are applied, and a terminal (Vn) 11 of the MOS capacitor (Cf) 5, the terminal being on the side of a well, receives a control voltage. In the multi-terminal MOS varactor with the arrangement above, it is possible to progressively change the valid electrostatic capacity C of the other terminal (Vgj) 9-j of an arbitrary capacitor (Cj) 6-j, by changing the control voltage. Since electrostatic capacity can be progressively changed in this MOS varactor, adopting this MOS varactor to an oscillator enables to control a frequency and sensitivity of the oscillator.

Abstract: A voltage-variable capacitor uses the channel-to-substrate junction from a gated diode formed from a metal-oxide-semiconductor transistor. The transistor gate has at least two contacts that are biased to different voltages. The gate acts as a resistor with current flowing from an upper gate contact to a lower gate contact. The gate-to-source voltage varies as a function of the position. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the gate that has gate voltages above the critical voltage has an inversion layer or conducting channel under the gate. Another portion of the gate has gate voltages below the critical voltage, and thus no channel forms. By varying either the gate voltages or the source voltage, the area of the gate that has a channel under it is varied, varying the channel-to-substrate capacitance. Separate gate arms reduce bias current.

Abstract: A capacitor structure (10) is implemented in an integrated circuit chip (11) along with other devices at the device level in the chip structure. The method of manufacturing the capacitor includes forming an elongated device body (17) on a semiconductor substrate from a first semiconductor material. Fabrication also includes forming lateral regions (20, 22) on both lateral sides of this device body (17). These lateral regions (20, 22) are formed from a second semiconductor material. A dielectric layer (28) is formed over both lateral regions (20, 22) and the device body (17), while an anode layer (30) is formed over the dielectric layer in an area defined by the device body. Each lateral region (20, 22) is coupled to ground at a first end (25) of the elongated device body (17). The anode (30) is coupled to the chip supply voltage at a second end (33) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.

Abstract: In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.