Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Abstract: A basic form of a variable capacitive apparatus and its actuating method are disclosed. The apparatus is a simple two-terminal structure and may be set by short duration, low voltage electrical pulses. Materials with perovskite structure or perovskite-related structures, especially colossal magnetoresistive materials, are the active constituents of the apparatus. The apparatus overcomes the shortcomings of its predecessors and offers the advantages of non-volatility, two or multi-level storage, non-destructive reading, free-of-power maintenance and potential high radiation hardness.

Abstract: A thin-film capacitor device for performing temperature compensation is manufactured by layering a first dielectric thin-film and a second dielectric thin-film, wherein the second dielectric thin-film has a thickness tN, wherein tN={&egr;0&tgr;t0t/(C/S)}·{1/(&tgr;/&kgr;)}, wherein C/S represents a sheet capacitance, &egr;0 represents the dielectric constant of vacuum, &tgr;t0t represents a desired temperature coefficient of capacitance, &tgr; represents the temperature coefficient of capacitance of the second dielectric thin-film, and &kgr; represents the relative dielectric constant of the second dielectric thin-film, a target value of a grain size of the second dielectric thin-film is determined by selecting the grain size satisfying the formula (&tgr;/&kgr;)/(&tgr;g/&kgr;g)>1, wherein &tgr;g represents the temperature coefficient of capacitance of the principal crystal grain, and &kgr;g represents relative dielectric constant of the principal crystal grain, and the seco

Abstract: A variable capacitance device comprising, in a semiconductor layer formed on a substrate via an buried oxide film: an n− region 132 formed in the shape of a ring and containing an n-type dopant; an anode 133 adjoined to the outer periphery of the n− region 132, the anode 133 being formed in the shape of a ring and containing a p-type dopant; and a cathode 131 adjoined to the inner periphery of the n− region 132, the third region containing an n-type dopant, wherein the dopant concentration in the n− region 132 is lower than that in each of the anode 133 and the cathode 131.

Abstract: A circuit configuration for providing a capacitance includes short-channel MOS transistors that are reverse-connected in series or in parallel, and that have the same channel type. When the short-channel MOS transistors are operated exclusively in the depletion mode in the required voltage range, the useful capacitance is increased, because of intrinsic capacitances, as compared with circuit configurations having conventional long-channel MOS transistors. These circuits greatly reduce the area taken up and reduce the costs.

Abstract: A charge pump circuit includes a multiplicity of first electrodes, insulating layers, and a multiplicity of second electrodes. The multiplicity of first electrodes are formed at multiple locations within one region of the substrate, wherein the multiplicity of first electrodes are interconnected. The insulating layers are formed on/above respective substrate regions between neighboring first electrodes, each layer covering at least the respective substrate region. The multiplicity of second electrodes are formed on/above the respective insulating layers, wherein the multiplicity of second electrodes are interconnected.

Abstract: A parallel-plate, voltage-variable capacitor is designed to have an increased current conducting perimeter relative to its area. In one approach, the perimeter is increased by changing the shape of the plates. In another approach, the varactor is implemented by a number of disjoint plates, which are coupled in parallel.

Abstract: A voltage-variable capacitor uses the channel-to-substrate junction from a gated diode formed from a metal-oxide-semiconductor transistor. The transistor gate has at least two contacts that are biased to different voltages. The gate acts as a resistor with current flowing from an upper gate contact to a lower gate contact. The gate-to-source voltage varies as a function of the position. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the gate that has gate voltages above the critical voltage has an inversion layer or conducting channel under the gate. Another portion of the gate has gate voltages below the critical voltage, and thus no channel forms. By varying either the gate voltages or the source voltage, the area of the gate that has a channel under it is varied, varying the channel-to-substrate capacitance. Separate gate arms reduce bias current.

Abstract: A varactor circuit having an increased tuning range comprises a first varactor in series with a second varactor between first and second terminals. A resistor is connected between the first and second terminals. A tap of the resistor is connected to a junction of the first and second varactors. This circuit effectively doubles tuning range compared to a single varactor.

Abstract: A receiver for radio or television signals provided with a high-frequency circuit having a discrete semiconductor component which includes a planar variable capacitance diode and an integrated series resistor formed on a common semiconductor or substrate. The receiver has lower parasitic capacitance and improved data reception, resulting in an increase of the Q factor of the variable capacitance diode and an increase in the circuit performance. The overall circuit loss is also reduced.

Abstract: An object of this invention is to provide a pn-varactor having a small resistance and capable of coinciding with incorporation of a circuit employing LC resonance into an integrated circuit. A dummy gate pattern 4 is formed over a n-well 1 in a semiconductor wafer and then p+ diffusion regions 2, 3 are formed on both sides with the dummy gate pattern 4 as inhibition mask. For the purpose, a control voltage VT higher than potentials of the p+ diffusion regions 2, 3 is applied to the n-well 1. Consequently, both the pn-junction between the n-well 1 and the p+ diffusion region 2 and the pn-junction between the n-well 1 and the p+ diffusion region 3 act as a pn-varactor whose capacity is changed by the control voltage VT. If an end dummy pattern is provided on both sides or around the p+ diffusion regions 2, 3, imbalance in capacity due to deflection in position is prevented.

Abstract: A Micro Electro-Mechanical System (MEMS) varactor (100, 200) having a bottom electrode (116) formed over a substrate (112) and a dielectric material (130) disposed over the bottom electrode (116). A pull-down electrode (122) is formed over spacer (120) and the dielectric material (130). The MEMS varactor (100, 200) is adapted to operate in a stiction mode, with at least a portion of pull-down electrode (122) in contact with dielectric material (130). The MEMS varactor (100, 200) has a high Q, large tuning range, and high sensitivity.

Abstract: The invention concerns a variable capacitance capacitor comprising a periodic structure of raised zones (5) separated by recesses (6) formed in a type N semiconductor substrate (1). The walls of the raised zones and the base of the recesses are coated with a conductive layer (9, 10). The substrate is connected to a first terminal (A) of the capacitor and the conductive layer to a second terminal (B) of the capacitor. At least the base of the recesses or the side of the raised zones comprises type P regions (8), the pitch of the raised parts being selected so that the space charging zones linked to the type P regions are joined when the voltage difference between said terminals exceeds a predetermined threshold. The zones not comprising type P regions are coated with an insulant (7) and a highly doped N region (10) is formed beneath the insulant.

Abstract: A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.

Abstract: A variable capacitor and a memory device employing the same. The variable capacitor includes a first electrode formed above a substrate; a second electrode suspended with respect to the first electrode to be moved back and forth with respect to the first electrode; and an actuator for varying a capacitance. One end of the actuator is connected to the second electrode and mounted with respect to the substrate to move the second electrode with respect to the first electrode in accordance with a voltage signal input through a driving electrode exposed externally. The memory device includes a transistor having a source, a gate, and a drain formed above a substrate, which are spaced apart from each other, a capacitor connected to the source, and an actuator varying a capacitance of the capacitor.

Abstract: A gate or capacitor insulator structure using a first grown oxide layer, a high-k dielectric material on the grown oxide layer, and a deposited oxide layer on the high-k dielectric material. The deposited oxide layer is preferably a densified deposited oxide layer. A conducting layer, such as a gate or capacitor plate, may overlay the densified oxide layer.

Abstract: A voltage-variable capacitor is constructed from a metal-oxide-semiconductor transistor. The transistor source has at least two contacts that are biased to different voltages. The source acts as a resistor with current flowing from an upper source contact to a lower source contact. The gate-to-source voltage varies as a function of the position along the source-gate edge. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the source has source voltages above the critical voltage and no conducting channel forms under the gate. Another portion of the source has source voltages below the critical voltage, and thus a conducting channel forms under the gate for this portion of the capacitor. By varying either the gate voltage or the source voltages, the area of the gate that has a channel under it is varied, varying the capacitance. Separate source islands eliminate source current.

Abstract: An integrated adjustable capacitor device and method for making such a device are provided. The adjustable capacitor includes an underlying electrode, a dielectric cavity, an upper electrode, and an etch cavity for removing sacrificial material from the dielectric cavity. The surface of the device is relatively flat due to epitaxal deposition of epi polysilicon and single crystal silicon. The adjustable capacitor system is capable of undergoing CMOS processes without requiring additional steps of covering the capacitor device to protect it and then removing the covering following the CMOS processes.

Abstract: A new MOS varactor device is described. A bottom electrode comprises a plurality of diffusion junctions in a semiconductor substrate. The semiconductor substrate may be n-type or p-type. The diffusion junctions are arranged in a two-dimensional array. The diffusion junction may be either n-type or p-type. The diffusion junctions may be contained in a p-well or an n-well. A dielectric layer overlies the semiconductor substrate. A top electrode overlies the dielectric layer. The top electrode comprises a single polygon containing a two-dimensional array of openings therein that exposes the diffusion junctions. The top electrode preferably comprises polysilicon. An interlevel dielectric layer overlies the top electrode and the diffusion junction. The interlevel dielectric layer has a two-dimensional array of contact openings that expose the underlying diffusion junctions. A patterned metal layer overlies the interlevel dielectric layer and contacts the diffusion junctions through the contact openings.

Abstract: In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer includes a layer of conductive metallic oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. A diode is formed on the overlying monocrystalline material layer, which is a gallium arsenide layer. Optionally, the accommodating buffer layer may include a non-conductive oxide layer on the conductive metallic oxide layer.

Abstract: A small-sized low-power-loss capacitor having low parasitic resistance is obtained by adopting metal wires as wires in a line and space structure to utilize capacitances between adjacent metal wires. A plurality of wires (3) each extending in a direction (x) and composed of metals such as Al and Cu are aligned in a direction (y) at predetermined intervals, forming a line and space structure (4). The line and space structure (4) is formed on a silicon substrate (1). On the silicon substrate (1), an insulation film (2) composed for example of a silicon oxide film is formed to provide electrical isolation between adjacent wires (3).

Abstract: A voltage controlled capacitor sandwiched between a buried oxide and a shallow trench insulator to form a near ideal P+ to n-well diode with minimal parasitic capacitance and resistance.

Abstract: An integrated adjustable capacitor device and method for making such a device are provided. The adjustable capacitor includes an underlying electrode, a dielectric cavity, an upper electrode, and an etch cavity for removing sacrificial material from the dielectric cavity. The surface of the device is relatively flat due to epitaxal deposition of epi polysilicon and single crystal silicon. The adjustable capacitor system is capable of undergoing CMOS processes without requiring additional steps of covering the capacitor device to protect it and then removing the covering following the CMOS processes.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to VCC power bus and the other node directly VSS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 &mgr;F.

Abstract: A receiver for radio or television signals provided with a high-frequency circuit comprising a discrete semiconductor component which includes a planar variable capacitance diode formed on a semiconductor substrate of a first doping type with a first doping density n1, on which semiconductor substrate an epitaxial layer of the same doping type with a second doping density n2>n1 is provided, on which epitaxial layer an insulation layer having a first window is provided by means of a first laterally bounded semiconductor region of a second doping type with a doping density n3>n2 in the epitaxial layer below the first window, and a first contact pad which contacts the first laterally bounded semiconductor region via the first window,

Abstract: A micro electro-mechanical systems device having variable capacitance is controllable over the full dynamic range and not subject to the “snap effect” common in the prior art. The device features an electrostatic driver (120) having a driver capacitor of fixed capacitance (121) in series with a second driver capacitor of variable capacitance (126). A MEMS variable capacitor (130) is controlled by applying an actuation voltage potential to the electrostatic driver (120). The electrostatic driver (120) and MEMS variable capacitor (130) are integrated in a single, monolithic device.

Abstract: A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrically insulative layer over the cell plate; c) providing a layer of semiconductive material on the insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; d) patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; e) filling the isolation trenches with insulative material; f) providing capacitor openings through the SOI layer and insulative layer into the cell plate substrate; g) providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; h) providing respective capacitor storage nodes over the dielectric layer within the capacitor openings, the respective storage nodes being in ohmic connection with the SOI layer; i) after providing the storage nodes, filling any remaining portions of the capacitor cont

Abstract: A semiconductor varactor with reduced parasitic resistance. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer (50) over the well regions (20) is a further embodiment to reduce the parasitic resistance.

Abstract: The present invention relates to a metal oxide semiconductor (MOS) varactor that takes advantage of the beneficial characteristics of MOS varactors to provide a high maximum to minimum capacitance ratio. By coupling in parallel at least one pair of MOS varactors with similar but shifted capacitance voltage (C-V) curves, the resulting capacitance is generally linear while preserving the desirable large capacitance ratio. A pair of MOS varactors, one with a p+ type gate and one with a n+ doped gate connected in parallel approximates the desired result. However, by adding further varactor elements, with their threshold voltages shifted by either implanting specific properties in their bodies or by providing offset voltages, a more linear C-V curve is attained while preserving the desired capacitance ratio.

Abstract: A switched variable capacitor (20), and binary-weighted array (40) of such capacitors (20), are disclosed. The switched variable capacitor (20) includes a switching transistor (14) connected in series with first and second capacitors (12), between the two terminals (A,B). Bias transistors (18) are provided, and of opposite conductivity type as the switching transistor (14) but with their gates connected to the gate of the switching transistor (14). The bias transistors (18), when on, apply a reverse bias voltage to the source/drain regions of the switching transistor (14), to minimize the parasitic junction capacitance, and thus improve the temperature stability of the capacitor (20). A binary-weighted array (40) of switched variable capacitors (20) is also disclosed, as is a voltage-controlled oscillator (50) incorporating such an array (40).

Abstract: A flat panel display device comprising a thin film semiconductor switching element formed on a surface of a substrate, a display electrode connected with the switching element, a semiconductor layer for auxiliary capacity which is electrically connected with the display electrode, a dielectric layer formed on a surface of the semiconductor layer for auxiliary capacity, and a metal layer formed on a surface of the dielectric layer, wherein the auxiliary capacity is constituted by the semiconductor layer for auxiliary capacity, the dielectric layer, and the metal layer, and the semiconductor layer for auxiliary capacity is implanted all over the surface thereof with a high concentration of impurity ion.

Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material preferably has a hardness which is at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.

Abstract: A MOS-type capacitor includes a semiconductor substrate of a first conductive type serving as a first electrode, a conductor layer formed on the semiconductor substrate via a capacitive insulation film and serving as a second electrode, and an impurity region of a second conductive type formed in the vicinity of the surface of the semiconductor substrate at a location in proximity to a region facing the conductor layer. The MOS-type capacitor is used as a variable capacitor in a VCO (voltage-controlled oscillator) having a widened frequency range.

Abstract: A high-speed voltage shifter/amplifier, a sigma delta modulator having a high-speed voltage shifter/amplifier and method for performing an amplification/a voltage shift to an analog signal. The voltage shifter/amplifier comprising a capacitor and an isolator; the isolator is coupled to the capacitor. The capacitor is adapted to receive a control signal, to be charged by an input signal, and to provide an output signal. The capacitor has a capacitance that is responsive to a level of the control signal, and a change in the capacitance of the capacitor forces a change in a level of the output signal; and the isolator is adapted to electrically isolate the capacitor when the capacitance is changed.

Abstract: A contact in a semiconductor memory device is formed on an active region of a cell array region, rather than on a sloped area between the cell array region and a core region. Preferably, an insulating layer on the active region is etched to form a hole therein and the contact formed through the hole. Preferably, the etching is performed using an etch solution having a high etch selectivity between the insulating layer and a top layer of the active region. Thus, the contact is evenly formed and the area of the cell array region is reduced, thereby enabling cells to be packed on a chip with high density.

Abstract: A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or “binary” varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region having little or no voltage dependency and having a capacitance equal to a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. The capacitance of the binary capacitor can be changed from C1 to C2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value.

Abstract: Semiconductor capacitor constructions, DRAM cell constructions, methods of forming semiconductor capacitor constructions, methods of forming DRAM cell constructions, and integrated circuits incorporating capacitor structures and DRAM cell structures are encompassed by the invention. The invention includes a method comprising: a) forming an opening within an insulative layer and over a node location; b) forming a spacer within the opening to narrow the opening, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed opening; c) removing a portion of the insulative layer from proximate the outer surface to expose at least a portion of the outer surface; d) forming a storage node layer in electrical connection with the node location, extending along the spacer inner surface, and extending along the exposed spacer outer surface; and e) forming a dielectric layer and a cell plate layer operatively proximate the storage node layer.

Abstract: A voltage generator for electrically programmable non-volatile memory cells, constructed of a number of charge pump circuits having inputs controlled by a number of phase generators. The charge pump circuits are laid as pairs of first and second charge pump circuits. The first charge pump circuits are active when the second charge pump circuits are inactive, and vice versa.

Abstract: A capacitor structure which exhibits a constant capacitance at non-negative voltages is provided by erasing a P-well floating gate NMOS transistor prior to its use as a capacitor. By erasing the transistor, a negative threshold voltage is obtained, thereby turning on the transistor and placing the transistor in an inversion state where the MOS capacitance is voltage-independent. Such transistors can be utilized as capacitors, whereby one plate of the capacitor corresponds to the control gate of the transistor and the other plate corresponds to the commonly connected source, drain, P-well, and deep N-well regions of the transistor, in voltage regulator circuits or other circuits in which node stabilization is desired. As a result, the capacitance is constant even at initialization when zero volts is applied.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.CC power bus and the other node directly V.sub.SS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.

Abstract: An electrical device having a voltage dependent capacitance is provided comprising a first region of a semiconductor material, and a second region and a third region of a semiconductor material formed in the first region, the second and third regions being separated by a separation region, and an electrically insulating layer formed on the first region at least at a region corresponding to the separation region, and a substantially conductive element formed on the insulating layer at least at a region corresponding to the separation region such that the insulating layer electrically insulates the substantially conductive element from the first, second and third regions, and a first electrode connected to the substantially conductive element, and a second electrode and third electrode are connected to the second and third regions. A method of manufacturing the device is also disclosed.

Abstract: The invention discloses a variable capacitor including a first storage electrode, a second storage electrode, and a variable length means coupled therebetween. The capacitance can be adjusted by varying a dielectric space therebetween according with an electrical input. The method for manufacturing a variable capacitor in an integrated circuit includes the steps of forming a first storage electrode, a first dielectric layer, a second dielectric layer, a pair of contact channels, and a second sacrificial layer. The method further includes forming a third sacrificial layer, a second storage electrode, a resistor pattern, a passivation layer, and etching the third, the second, and the first sacrificial layer for having a dielectric space between the first storage electrode and the second storage electrode.

Abstract: A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions.

Abstract: A single-poly EEPROM cell comprising an inverter and a capacitive coupling area. The inverter is formed by: a p-well formed in a substrate; a gate structure formed atop the p-well and being formed from a thin gate oxide layer underneath a conductive layer; an n-base formed adjacent to a first edge of the gate structure and within the p-well; a p+ structure formed within the n-base; and a n+ structure adjacent a second edge of the gate structure and within the p-well. The capacitive coupling area is formed from a second p-well formed in the substrate and a floating gate, the floating gate formed from the conductive layer and capacitively coupled to the second p-well.

Abstract: In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

Abstract: A voltage variable capacitor (10) fabricated on a semiconductor substrate (11) includes a gate structure (62) and a well (22) under the gate structure (62). A heavily doped buried layer (15) and a heavily doped contact region (31) in the semiconductor substrate (11) form a low resistance conduction path from the well (22) to a surface (17) of the semiconductor substrate (11). A multi-finger layout is used to construct the voltage variable capacitor (10). In operation, when a voltage applied across the voltage variable capacitor (10) changes, the width of depletion region in the well (22) changes, and the capacitance of the voltage variable capacitor (10) varies accordingly.

Abstract: A structure is provided to create a voltage-independent capacitive structure using a typical MOS fabrication process. The capacitive structure includes two FET devices connected in series by having their source, drain, and body terminals all coupled together into a common node. A biasing circuit that includes a current generator and a current mirror biases the common node so that a constant capacitance is maintained across the gate terminals of the two serially connected FET devices, independent of the applied voltage.

Abstract: A tunable capacitor includes a first capacitor formed from semiconductor material and having a first terminal defining an anode, and a second capacitor integrally formed with the first capacitor from semiconductor material, the second capacitor being operatively coupled in series with the first capacitor, and having a second terminal defining a cathode. The second capacitor is formed as a field effect device or MOSFET configured to provide a depletion region controlled by applying a control voltage to a control terminal of the field effect device. The first capacitor is reverse biased by application of a reverse bias voltage between the anode and the cathode to provide a predetermined capacitance while the control voltage applied to the control terminal of the second capacitor varies the depletion region such that the capacitance of second capacitor is varied independently of the reverse bias voltage.

Abstract: A voltage variable capacitor (VVC) is made by placing an intercalation compound between two electrodes of a capacitor. The VVC has a reservoir of an intercalant in proximity with the intercalation compound. The two materials are chosen from those known to exhibit the intercalation reaction. The extent of the intercalation reaction is controlled by applying a voltage to the intercalant reservoir and the intercalation compound. A variable capacitor is created by applying a signal to the device and appropriately controlling the .di-elect cons. of the device by using the input control voltages.