Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a substrate, a source region and a drain region in the substrate, a buffer dielectric layer positioned on the substrate adjacent to the drain region, and a gate electrode laterally positioned between the source region and the drain region. The gate electrode includes a portion that overlaps with the buffer dielectric layer, and the portion of the gate electrode includes notches.

Abstract: A multi-level inverter having at least two banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.

Abstract: A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

Abstract: Provided are a semiconductor device having small characteristic variations with time and high reliability and an in-vehicle control device using the same, the semiconductor device including a plurality of transistor elements constituting a current mirror circuit or a differential amplifier circuit that requires high relative accuracy.

Abstract: A multi-level inverter having at least two banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.

Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.

Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents is less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

Abstract: A semiconductor device includes a semiconductor body comprising a first surface, a second surface opposite to the first surface, an active region, and an edge region surrounding the active region in a horizontal plane. The semiconductor device further includes a plurality of transistor cells at least partly integrated in the active region. Each transistor cell includes a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region. The semiconductor device also includes a sensor device having a first sensor region of a first doping type integrated in the edge region. The first sensor region is electrically coupled to a first contact pad and to a second contact pad. Each contact pad is arranged either on the first surface or on the second surface. The sensor device at least partially extends around the active region.

Abstract: An integrated circuit includes a first and a second set of conductive traces. The first set of conductive traces is in a first level and extends in a first direction. The second set of conductive traces is in a second level and extends in a second direction. The second set of conductive traces includes a first conductive trace corresponding to a gate terminal of a first p-type transistor and a gate terminal of a first n-type transistor, and a second conductive trace corresponding to a gate terminal of a second n-type transistor and a gate terminal of a second p-type transistor. The first and second conductive trace are separated from each other in the first direction. The first n-type transistor and the second p-type transistor are part of a first transmission gate. The second n-type transistor and the first p-type transistor are part of a second transmission gate.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate and a drain region disposed within the substrate. The drain region is separated from the source region along a first direction. A drift region is disposed within the substrate between the source region and the drain region, and a plurality of isolation structures are disposed within the drift region. A gate electrode is disposed within the substrate. The gate electrode has a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures.

Abstract: A high voltage device for use as a lower switch in a power stage of a switching regulator includes at least one lateral diffused metal oxide semiconductor (LDMOS) device and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well, a body region, a gate, a source, and a drain. The SBD includes a Schottky metal layer and a Schottky semiconductor layer. The Schottky metal layer is electrically connected to the source, and the Schottky semiconductor layer is in contact with the well.

Abstract: A gate pad is includes a first portion disposed in a gate pad region and a second portion disposed in a gate resistance region and connected to the first portion, the gate pad has a planar shape in which the second portion protrudes from the first portion. A gate polysilicon layer disposed on a front surface of a semiconductor substrate via a gate insulating film, between the semiconductor substrate and an interlayer insulating film, has a surface area at least equal to that of the gate pad and opposes an entire surface of the gate pad in a depth direction. ESD capability of a first region where the gate pad is provided is greater than ESD capability of a second region where a gate resistance is provided and is greater than ESD capability of a third region where a MOS structure of an active region is provided.

Abstract: An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated in the first direction, and a second gate electrode structure having a third portion and a fourth portion separated in the first direction. The integrated circuit further includes a conductive feature including a first section electrically connected to the second portion, wherein the first section extends in the second direction, a second section electrically connected to the third portion, wherein the second section extends in the second direction, and a third section electrically connecting the first section and the second section, the third section extends in a third direction angled with respect to the first and second directions.

Abstract: An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.

Abstract: The present invention relates, for example, to a semiconductor structure containing multiple parallel channels in which several parallel conductive channels are formed within the semiconductor structure. Electric contact or electrostatic control over all these channels is done by three-dimensional electrode structures. The multiple channel structure with three-dimensional electrodes can be applied to semiconductors devices such as field effect transistors, diodes, and other similar electronic or quantum-effect devices. This structure is practical for materials where multiple parallel conduction channels can be formed, such as in III-V semiconductors. Ill-Nitride semiconductors with such structures are described which can lead to increased power density, reduced on-resistance and improved device performance, in addition to reducing dynamic on-resistance, and improving the stability of their threshold voltage and reliability.

Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.

Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.

Abstract: The semiconductor device including a substrate comprising a chip region and a guard-ring region which surrounds a side surface of the chip region, an isolation layer configured to define an active region within the guard-ring region, a first doping layer in the active region and doped with first impurities having a first doping concentration, a second doping layer on the first doping layer and in the active region, the second doping layer doped with second impurities having a same conductivity type as the first impurities of the first doping layer, the second impurities having a second doping concentration, the second doping concentration being greater than the first doping concentration, a first gate electrode on the second doping layer, and a first wire layer on the first gate electrode may be provided.

Abstract: A method of manufacturing an integrated circuit includes manufacturing a first set of conductive features by a first mask, positioning a set of gates in a second direction, manufacturing a second set of conductive features by a second mask, and electrically coupling a first portion of the set of gates to a second portion of the set of gates. The first and second set of conductive features is in a first direction and a first layer. The set of gates is in a second layer. The first portion of the set of gates corresponds to a gate terminal of a first n-type transistor, the second portion of the set of gates corresponds to a gate terminal of a first p-type transistor, the first n-type transistor being part of a first transmission gate, and the first p-type transistor being part of a second transmission gate.

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate disposed over a drift region. A first gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an outer sidewall of the first gate electrode to the drain region. The etch stop layer overlies the drift region disposed between the source region and the drain region. A field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate overlies the drift region. A top surface of the field plate is aligned with a top surface of the first gate electrode and a bottom surface of the field plate is vertically above a bottom surface of the first gate electrode. The field plate and first gate electrode respectively include metal materials.

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.

Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.

Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

Abstract: A semiconductor switch device and a method of making the same. The device includes a semiconductor substrate having a major surface. The device also includes a first semiconductor region located in the substrate beneath the major surface. The device includes an elongate gate located on the major surface. The device also includes a source region and a drain region located in the first semiconductor region adjacent respective first and second elongate edges of the gate. The device also includes electrical contacts for the source and drain regions. The contacts include at least two contacts located on either the source region or the drain region, which are spaced apart along a direction substantially parallel the elongate edges of the gate. The device further includes an isolation region located between the at least two contacts. The isolation region extends through the source/drain region from the major surface to the first semiconductor region.

Abstract: Embodiments of packaged semiconductor devices and methods of making thereof are provided herein, which include a semiconductor die having a plurality of pads on an active side; a dummy die having a plurality of openings that extend from a first major surface to a second major surface opposite the first major surface, wherein the plurality of openings are aligned with the plurality of pads; and a silicone-based glue attaching the dummy die to the active side of the semiconductor die, wherein a plurality of bondable surfaces of the semiconductor die are exposed through the plurality of openings of the dummy die.

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a semiconductor substrate, and includes: a gate, a source, a drain, and at least one plug plate electrode. The plug plate electrode is in direct contact with the gate, and is electrically connected to the gate. The plug plate electrode extends downwards from the bottom of the gate to the semiconductor substrate, through a current vertical height of a conductive current when the high voltage is ON. The plug plate electrode is between the source and the drain in a lateral direction. The plug plate electrode includes a dielectric layer and a conductive layer.

Abstract: A semiconductor substrate has a main surface, a rear surface, an active device region, and an inactive region adjacent the active device region. Doped source, body, drift and drain regions, and electrically conductive gate and field electrodes are disposed in the active device region. The gate electrode is configured to control an electrical connection between the source and drain regions. The field electrode is adjacent to the drift region. An intermetal dielectric layer is disposed on the main surface, an electrically conductive source pad is formed in a first metallization layer that is formed on the intermetal dielectric layer. A resistor is connected between the source pad and the field electrode. The resistor includes an electrically conductive resistance section that is disposed in a resistor trench. The resistor trench is formed within the inactive region and is electrically isolated from every active device within the active device region.

Abstract: An electronic device includes an isolated region surrounded by an isolation ring over a semiconductor substrate. A well of a first conductivity type is located within the isolated region. A source region and a drain region of a second conductivity type are located over the well. A local-oxidation-of-silicon (LOCOS) layer is located on the well between the source and the drain, between the source and the isolation ring, and between the drain and the isolation ring. A gate electrode located between the source and the drain on said LOCOS layer.

Abstract: Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

Abstract: A recessed portion is formed in a top surface of an isolation insulation film filling an isolation trench between a p+ source region and a p+ drain region. A p? drift region is located below the isolation trench and connected to the p+ drain region. A gate electrode fills the recessed portion. An n-type impurity region is located below the p? drift region and directly below the recessed portion.

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.

Abstract: A transistor includes a first gate-controlled region having a first threshold voltage and a second gate-controlled region in parallel with the first gate-controlled region. The second gate-controlled region has a second threshold voltage different form the first threshold voltage.

Abstract: Techniques are disclosed for forming a monolithic integrated circuit semiconductor structure that includes a radio frequency (RF) frontend portion and may further include a CMOS portion. The RF frontend portion includes componentry implemented with column III-N semiconductor materials such as gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and compounds thereof, and the CMOS portion includes CMOS logic componentry implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). Either of the CMOS or RF frontend portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of III-N transistors and/or RF filters, along with column IV CMOS devices on a single substrate.

Abstract: Semiconductor device and methods for making the devices includes a buried layer of a first conductivity in a substrate in which a distance between two adjacent ends can be selected to achieve a desired breakdown voltage. A deep well having a first doping concentration of a second conductivity type is implanted in an epitaxial layer above the two adjacent ends of the buried layer. A patterned doped region is formed in the deep well and extending into the epitaxial layer above and separated a distance from the two adjacent ends of the buried lay. The patterned doped region has a second doping concentration of the second conductivity type that is greater than the first doping concentration.

Abstract: The present disclosure provides a method for forming a semiconductor device, including: forming a mask layer over a substrate, the mask layer containing an opening, exposing a surface portion of the substrate to form an exposed surface portion of the substrate; forming an insulation structure between the mask layer and the substrate, and in the opening; performing a thinning process on the insulation structure exposed by the opening to form a recess region on a top of the insulation structure; and forming a gate electrode over the insulation structure and covering a portion of the recess region.

Abstract: A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode.

Abstract: Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (22), a first P well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second N well (32) in the first N well and form a second P well (34) in the first P well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode (72) and a source electrode (74).

Abstract: A high voltage (HV) transistor is integrated on a silicon-on-insulator (SOI) substrate. The HV transistor is disposed in a HV device region disposed on a bulk substrate of the SOI substrate. The HV device region includes a top field oxide which includes at least a part of a buried oxide (BOX) of the SOI substrate. A HV gate is disposed in HV region overlapping the HV top field oxide and includes first and second HV gate sidewalls. A drain is disposed on the bulk substrate and displaced from the first HV gate sidewall by the HV top field oxide. A source is disposed on the bulk substrate adjacent to the side of the second HV gate sidewall.

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance.

Abstract: A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

Abstract: Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

Abstract: A high-voltage semiconductor device is provided. The device includes a semiconductor substrate having a first conductivity type, and a first doping region having a second conductivity type therein. An epitaxial layer is on the semiconductor substrate. A body region having the first conductivity type is in the epitaxial layer on the first doping region. A second doping region and a third doping region that have the second conductivity type are respectively in the epitaxial layer on both opposite sides of the body region, so as to adjoin the body region. Source and drain regions are respectively in the body region and the second doping region. A field insulating layer is in the second doping region between the source and drain regions. A gate structure is on the epitaxial layer to cover a portion of the field insulating layer.

Abstract: The present disclosure provides a laterally diffused metal-oxide-semiconductor (LDMOS) device. The LDMOS device includes a plurality of fin structures formed on a substrate including a first device region, a second device region, and an isolation region sandwiched between the two regions. An opening is formed in the fin structures in the isolation region. The LDMOS device further includes an isolation layer formed in the opening and covering the sidewall of the opening formed by a portion of each fin structure in the first device region. The isolation layer exposes top surfaces of the plurality of fin structures. Moreover, the LDMOS device also includes a gate structure formed across each fin structure in the first device region. The gate structure covers a portion of the sidewall and the top surfaces of the fin structure formed in the first device region and also covers the top surface of the isolation layer.

Abstract: A semiconductor device includes a bulk substrate of a first conductivity type, a first semiconductor on insulator (SOI) block in the bulk substrate, a first well of the first conductivity type in the first SOI block, a second well of a second conductivity type in the first SOI block, a first guard ring of the first conductivity type in the first SOI block around at least a portion of a periphery of the first SOI block, and a second guard ring of the second conductivity type in the first SOI block around at least a portion of the periphery of the first SOI block. The first conductivity type is different than the second conductivity type.