Abstract: A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.

Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.

Abstract: A semiconductor device comprises a bulk semiconductor substrate that includes a first conductivity type floating buried doped region bounded above by a second conductivity type doped region and bounded below by another second conductivity semiconductor region. Trench isolation regions extend through the second conductivity doped region and the first conductivity floating buried doped region into the semiconductor region. Functional devices are disposed within the second conductivity type doped region. The first conductivity type floating buried doped region is configured as a self-biased region that laterally extends between adjacent trench isolation regions.

Abstract: Formation methods of a semiconductor device structure are provided. The method includes forming a bottom layer, a middle layer and an upper layer over a substrate, developing the upper layer to form an upper pattern with a first opening exposing the middle layer and a sidewall of the upper pattern. The upper pattern has a top surface. The method further includes conformally forming a protective layer over the upper pattern and the exposed middle layer, anisotropically etching the protective layer to leave a portion of the protective layer over the sidewall of the upper pattern and expose the middle layer, etching the middle layer not covered by the upper pattern and the portion of the protective layer to form a middle pattern with a second opening exposing the bottom layer, and etching the bottom layer though the second opening of the middle pattern.

Abstract: A semiconductor device includes a substrate having a high-voltage (HV) region; HV gate structures formed in the HV region of the substrate; a HV dummy pattern disposed in the HV region, and the HV dummy pattern comprising at least a semiconductor portion and a dummy HM stack disposed on the semiconductor portion, wherein a height (hS) of the semiconductor portion of the HV dummy pattern is smaller than a height (hHV-g) of a HV gate electrode of one of the HV gate structures.

Abstract: A switching device may be provided with: a semiconductor substrate; a trench provided in an upper surface of the semiconductor substrate; a gate insulating layer covering an inner surface of the trench; and a gate electrode located in the trench. The semiconductor substrate includes: a first semiconductor region being in contact with the gate insulating layer; a body region being in contact with the gate insulating layer under the first semiconductor region; a second semiconductor region being in contact with the gate insulating layer under the body region; a bottom region being in contact with the gate insulating layer at a bottom surface of the trench; and a connection region being in contact with the gate insulating layer at a lateral surface of the trench and connecting the body region and the bottom region. The connection region is thicker than the bottom region.

Abstract: Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.

Abstract: Semiconductor device with a semiconductor body that includes a clamping structure including a pn junction diode and a Schottky junction diode serially connected back to back between a first contact and a second contact. A breakdown voltage of the pn junction diode is greater than 100 V and a breakdown voltage of the Schottky junction diode is greater than 10 V.

Abstract: According to an example, a device is suggested, said device comprising a switching element, an integrated sensor providing a signal and an electronic fuse that is arranged to determine a fuse condition based on the signal and based on at least one fuse characteristic and to trigger a fuse event in case the fuse condition is met.

Abstract: A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.

Abstract: To suppress the reverse breakdown voltage decrease while separating a main body region from a current detecting region. To provide a semiconductor device comprising a semiconductor substrate, a main body region having one or more operation cells formed inside the semiconductor substrate, a current detecting region having one or more current detecting cells formed inside the semiconductor substrate, an intermediate region formed between the main body region and the current detecting region and inside the semiconductor substrate, an upper surface side electrode formed above at least part of the main body region, a current detecting electrode that is formed above at least part of the current detecting region and is separate from the upper surface side electrode, and an additional electrode that is formed above at least part of the intermediate region and is connected to either the upper surface side electrode or the current detecting electrode.

Abstract: An embodiment of a semiconductor device comprises a trench transistor cell array in a semiconductor body. The semiconductor device further comprises an edge termination region of the trench transistor cell array. At least two first auxiliary trench structures extend into the semiconductor body from a first side and are consecutively arranged along a lateral direction. The edge termination region is arranged, along the lateral direction, between the trench transistor cell array and the at least two first auxiliary trench structures. First auxiliary electrodes in the at least two first auxiliary trench structures are electrically connected together and electrically decoupled from electrodes in trenches of the trench transistor cell array.

Abstract: A cascode switch circuit includes a normally-on device cascode coupled to a normally-of device between first and second terminals of the cascode switch circuit. A leakage clamp circuit is coupled between first and second terminals of the normally-off device. The leakage clamp circuit is coupled to clamp a voltage at an intermediate terminal between the normally-on device and the normally-off device at a threshold voltage level. The leakage clamp circuit is further coupled to clamp a voltage between the second terminal of the normally-on device and the control terminal of the normally-on device at the threshold voltage level to keep the normally-on device off when the normally-on device and the normally-off device are off.

Abstract: Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

Abstract: A semiconductor power chip has a semiconductor power device formed on a semiconductor die; wherein the semiconductor power device comprises an array of conductive contact elements; a passivation layer formed over the plurality of conductive contact elements, the passivation layer comprising passivation openings over a plurality of the conductive contact elements; and an array of conductive bumps including one or more interconnection bumps, wherein each interconnection bump is formed over the passivation layer and extends into at least two of the passivation openings and into contact with at least two underlying conductive contact elements to thereby provide a conductive coupling between the at least two underlying conductive contact elements.

Abstract: A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure.

Abstract: A slotted gate power transistor is a lateral power device including a substrate, a gate dielectric formed over the substrate, a channel region in the substrate below the gate dielectric and gate electrode layer formed over the gate dielectric. The gate electrode layer overlaps the gate dielectric above the channel region, an accumulation region, and a drift region below an oxide filled shallow trench isolation (or STI) or locally oxidized silicon (LOCOS) region. The slotted gate power transistor includes one or more slots or openings on the gate electrode layer over the accumulation region. Electrical connectivity is maintained over the entire gate electrode layer without external wiring.

Abstract: A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body

Abstract: Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ??100 Ohm·cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

Abstract: A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate.

Abstract: A tri-gate laterally-diffused metal oxide semiconductor (LDMOS), including a substrate, a P-type semiconductor region, a P-type contact region, an N-type source region, a gate dielectric layer, an N-type drift region, a first isolation dielectric layer, an N-type drain region, and a second isolation dielectric layer. The P-type semiconductor region is disposed on one end of an upper surface of the substrate, and the N-type drift region is disposed on another end of the upper surface. The P-type semiconductor region contacts with the N-type drift region. The P-type contact region and the N-type source region are disposed on one side of the P-type semiconductor region which is away from the N-type drift region, and compared with the P-type contact region, the N-type source region is in the vicinity of the N-type drift region.

Abstract: A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a body region disposed in the semiconductor substrate and to which a voltage is applied during operation and in which a channel is formed during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the body region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. The depletion region establishes an electrical link between the buried doped isolation layer and the body region such that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the body region.

Abstract: A semiconductor device is formed, the semiconductor device including: an SOI substrate; field insulating films that are formed on the SOI substrate and that separate a plurality of element formation regions; first and second HV pMOSs, and first and second LV pMOSs that are formed in the plurality of element formation regions; a first interlayer insulating film and a second interlayer insulating film formed on the SOI substrate; a mold resin formed on the second interlayer insulating film; and conductive films that are formed on the first interlayer insulating film and that are interposed between the plurality of element formation regions, and the field insulating films and mold resin.

Abstract: The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array. The deep trench isolation structures limit the lateral diffusion of dopants and the lateral movement of charge carriers.

Abstract: A temperature detection circuit for detecting a temperature of a switching element, a current source for causing a forward current to flow to the temperature detection circuit, an amplifier circuit for amplifying a forward voltage of the temperature detection circuit, a current adjustment circuit for adjusting a magnitude of a gate current to the switching element on the basis of an output voltage of the amplifier circuit, and a drive circuit for receiving an external signal and turning ON/OFF the switching element, are included. The magnitude of the gate current caused to flow from the current adjustment circuit to the gate electrode of the switching element is adjusted on the basis of a change in a magnitude of the forward voltage corresponding to a change in the temperature of the temperature detection circuit.

Abstract: A device that increases a value of current flowing through a whole chip until a p-n diode in a unit cell close to a termination operates and reduces a size of the chip and a cost of the chip resulting from the reduced size. The device includes a second well region located to sandwich the entirety of a plurality of first well regions therein in plan view, a third separation region located to penetrate the second well region from a surface layer of the second well region in a depth direction, and a second Schottky electrode provided on the third separation region.

Abstract: A pressure sensor includes a body made of semiconductor material having a first type of conductivity and a pressure-sensitive structure having the first type of conductivity defining a suspended membrane. One or more piezoresistive elements having a second type of conductivity (P) are formed in the suspended membrane. The piezoresistive elements form, with the pressure-sensitive structure, respective junction diodes. A temperature sensing method includes: generating a first current between conduction terminals common to the junction diodes; detecting a first voltage value between the common conduction terminals when the first current is supplied; and correlating the detected first voltage value to a value of temperature of the diodes. The temperature value thus calculated can be used for correcting the voltage signal generated at output by the pressure sensor when the latter is operated for sensing an applied outside pressure which deforms the suspended membrane.

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a stack overlying a substrate. The stack includes a silicon germanium layer and a silicon layer, where the silicon germanium layer has a first germanium concentration. The stack is condensed to produce a second germanium concentration in the germanium layer, where the second germanium concentration is greater than the first germanium concentration. A fin is formed that includes the stack, and a gate is formed overlying the fin.

Abstract: Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a P-well and an N-well disposed in the semiconductor substrate, a source disposed in the N-well and a drain disposed in the P-well, a shallow trench isolation (STI) structure disposed in the P-well, a gate structure disposed on the semiconductor substrate, wherein a portion of the gate structure extends into the semiconductor substrate and is disposed in a location corresponding to the STI structure.

Abstract: To improve the reliability of a semiconductor device. In particular, the reading of incorrect information from a memory cell is suppressed. A first low-concentration region is formed in a well, and is located under a side wall insulating film in a planar view. The first low-concentration region has a second conductivity type, and the second conductivity-type impurity concentration is lower than the impurity concentration in a drain. A second low-concentration region is formed in the well, and is located under a spacer insulating film in a planar view. In addition, a second conductivity type impurity concentration in the second low-concentration region is lower than the second conductivity-type impurity concentration in the first low-concentration region, and is higher than the second conductivity-type impurity concentration in a portion located under the insulating film of the well.

Abstract: Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells.

Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.

Abstract: In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET.

Abstract: A method for manufacturing a semiconductor device may include the following steps: preparing a semiconductor substrate that includes a first substrate region, a second substrate region, and a third substrate region; providing a first mask that overlaps the semiconductor substrate; etching, using the first mask, the first semiconductor substrate to form a trench in each of the substrate regions; providing a second mask that overlaps the semiconductor substrate and includes three openings corresponding to the substrate regions; performing first ion implantation through the three openings to form a P-doped region in each of the substrate regions; performing second ion implantation through the three openings to form an N-doped region in each of the substrate regions; and performing third ion implantation through the three openings to form another N-doped region in each of the substrate regions; and forming an isolation member in each of the trenches.

Abstract: A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film.

Abstract: An LDMOS is formed with a field plate over the n? drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.

Abstract: A device includes a substrate, a body region in the substrate and having a first conductivity type, source and drain regions in the substrate, having a second conductivity type, and spaced from one another to define a conduction path that passes through the body region, a doped isolating region in the substrate, having the second conductivity type, and configured to surround a device area in which the conduction path is disposed, an isolation contact region in the substrate, having the second conductivity type, and electrically coupled to the doped isolating region to define a collector region of a bipolar transistor, and first and second contact regions within the body region, having the first and second conductivity types, respectively, and configured to define a base contact region and an emitter region of the bipolar transistor, respectively.

Abstract: A semiconductor memory device includes a sense amplifier section. The sense amplifier section includes first n-type diffusion layers, second n-type diffusion layers, first to fifth gates, and first to eighth contacts. The first to fourth contacts are formed over the first n-type diffusion layers. The fifth to eighth contacts are formed over the second n-type diffusion layers. The first and fourth gates are formed in a region between the first n-type diffusion layers. The third gate is formed in a region between the first n-type diffusion layers and in a region between the second n-type diffusion layers. The second and fifth gates are formed in a region between the second n-type diffusion layers.

Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Abstract: The present invention provides a semiconductor device structure which integrates a lateral diffused metal oxide semiconductor (LDMOS) with a Schottky diode, including: a substrate, having a first conductivity type, a gate positioned on the substrate, a drain region formed in the substrate, the drain region having a second conductivity type complementary to the first conductivity type, a source region formed in the substrate, the source region having the second conductivity type, a high-voltage well region formed in the substrate, the high-voltage well region having a first conductivity type; a Schottky diode disposed on the substrate and disposed beside the LDMOS, wherein the semiconductor device structure is an asymmetric structure, and a deep well region disposed in the substrate and having the second conductivity type, wherein the LDMOS and the Schottky diode are all formed within the deep well region.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract: A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.

Abstract: A light emitting element has a property in which a current value is varied due to a change in temperature. A display device has a temperature compensation function in order to suppress the variation in current value dues to the change in temperature. The temperature compensation function, which is essential for the present invention has a sensor, a storage means, and a correction means. The sensor has a function of detecting an environmental temperature. The detected temperature is compared with data of voltage-current characteristic versus temperature in the light emitting element which is stored in advance in the storage means. In the correction means, a signal inputted to a pixel or a power source potential supplied to a pixel portion is corrected using an output of the sensor and the data stored in the storage means.

Abstract: An LDMOS device includes a second conduction type buried layer, a first conduction type drain extension region configured to be formed on and/or over a region of the second conduction type buried layer, a second conduction type drain extension region configured to be formed in a partial region of the first conduction type drain extension region, a first conduction type body, a first guard ring configured to be formed around the second conduction type drain extension region and configured to include a second conduction type impurity layer, and a second guard ring configured to be formed around the first guard ring and configured to include a high-voltage second conduction type well and a second conduction type impurity layer. Further, the second conduction type impurity layer of the first guard ring and the second conduction type impurity layer of the second guard ring operate as an isolation.

Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T2 that is larger than the thickness T1 of an upper portion of the gate oxide. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.

Abstract: In the interior of a semiconductor substrate having a main surface, a first p? epitaxial region is formed, a second p? epitaxial region is formed on the main surface side, and an n-type drift region and a p-type body region are formed on the main surface side. An n+ buried region is formed between the first p? epitaxial region and the second p? epitaxial region in order to electrically isolate the regions. A p+ buried region having a p-type impurity concentration higher than that of the second p? epitaxial region is formed between the n+ buried region and the second p? epitaxial region. The p+ buried region is located at least immediately under the junction between the n-type drift region and the p-type body region so as to avoid a site immediately under a drain region which is in contact with the n-type drift region.