High Temperature (i.e., >30o Kelvin) Patents (Class 257/33)
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Patent number: 6784451Abstract: In one embodiment, a two-junction phase qubit includes a superconducting loop and two Josephson junctions separated by a mesoscopic island on one side and a bulk loop on another side. The material forming the superconducting loop is a superconducting material with an order parameter that violates time reversal symmetry. In one embodiment, a two-junction phase qubit includes a loop of superconducting material, the loop having a bulk portion and a mesoscopic island portion. The loop further includes a relatively small gap located in the bulk portion. The loop further includes a first Josephson junction and a second Josephson junction separating the bulk portion from the mesoscopic island portion. The superconducting material on at least one side of the first and second Josephson junctions has an order parameter having a non-zero angular momentum in its pairing symmetry. In one embodiment, a qubit includes a superconducting loop having a bulk loop portion and a mesoscopic island portion.Type: GrantFiled: December 17, 2002Date of Patent: August 31, 2004Assignee: D-Wave Systems Inc.Inventors: Mohammad H. S. Amin, Alexandre Zagoskin, Geordie Rose, Jeremy P. Hilton
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Patent number: 6682621Abstract: A method of forming a novel high temperature superconducting Josephson junction which is capable of achieving a formation of a Josephson junction having high characteristic conveniently and quickly without necessitating costly micromachining facilities. Two high temperature superconducting whisker crystals are crossed with each other on a substrate and subjected to thermal treatment to form a Josephson junction between the two high temperature superconducting whisker crystals.Type: GrantFiled: August 21, 2001Date of Patent: January 27, 2004Assignee: National Institute for Materials ScienceInventors: Yoshihiko Takano, Takeshi Hatano, Akira Ishii, Syunichi Arisawa, Kazumasa Togano
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Patent number: 6670630Abstract: A superconducting structure that includes a mesoscopic phase device and a mesoscopic charge device. The superconducting structure further includes a mechanism for coupling the mesoscopic phase device and the mesoscopic charge device so that the quantum state of the mesoscopic phase device and the quantum state of the mesoscopic charge device interact. In another aspect, the superconducting structure includes a mechanism for reading out the quantum state of the mesoscopic charge device.Type: GrantFiled: April 12, 2002Date of Patent: December 30, 2003Assignee: D-Wave Systems, Inc.Inventors: Alexandre Blais, Jeremy P. Hilton
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Publication number: 20030209706Abstract: A mesa-shaped superconducting-superlattice structure is formed and adhered with epoxy onto a dielectric substrate where plural superconducting layers and plural insulating layers are naturally and alternately stacked. A &lgr;/4 micro strip line (which means the length of the strip line is one-fourth of the wavelength of a microwave to be introduced) is electrically connected via a metallic film onto the mesa structural portion of the superconducting-superlattice structure, and a metallic electrode is electrically connected to the additional mesa structural portion of the superconducting-superlattice structure via a metallic film.Type: ApplicationFiled: March 21, 2003Publication date: November 13, 2003Applicant: UTSUNOMIYA UNIVERSITYInventors: Akinobu Irie, Ginichiro Oya
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Patent number: 6627915Abstract: A superconducting qubit is presented. The qubit is a shaped long Josephson junction with a magnetic fluxon such that, in the presence of an externally applied magnetic field, a fluxon potential energy function indicating a plurality of pinning sites in the qubit is produced. In one embodiment, a heart-shaped Josephson junction is formed where a trapped fluxon has a double-welled potential energy function, indicating two pinning sites, when the junction is placed in an externally applied magnetic field. The qubit is manipulated by preparing an initial state, creating a superposition of the two states by decreasing the magnetic field, evolving of the quantum state with time, freezing in a final state by increasing the magnetic field, and reading out the final state. In other embodiments, qubit exhibiting potential energy functions having any number of pinning sites can be realized.Type: GrantFiled: August 11, 2000Date of Patent: September 30, 2003Assignee: D-Wave Systems, Inc.Inventors: Alexey V. Ustinov, Andreas Walraff, Yu Koval
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Patent number: 6605822Abstract: A method for performing a quantum computing entanglement operation between a phase qubit and a charge qubit. A coherent connection between the phase qubit and the charge qubit is provided. The coherent connection allows the quantum state of the phase qubit and the quantum state of the charge qubit to interact with each other. The coherent connection is modulated for a duration te. The phase qubit is connected to the charge qubit during at least a portion of the duration te in order to controllably entangle the quantum state of the phase qubit and the quantum state of the charge qubit.Type: GrantFiled: April 12, 2002Date of Patent: August 12, 2003Assignee: D-Wave Systems, Inc.Inventors: Alexandre Blais, Jeremy P. Hilton
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Publication number: 20030127644Abstract: The present invention, a III-nitride light emitting diode (LED) and a manufacture method thereof, forms a magnetic metal layer in a conventional III-nitride LED by the method of thermal evaporation, e-beam evaporation, ion sputtering, or electroplate. Due to the eddy current effect, heat is generated by using electromagnetic oven inducing with electromagnetic wave to activate the p-type semiconductor material in III-nitride LED. The present invention has advantages of providing the equipments of simple structure and low cost. The contact resistance between the semiconductors and electrodes is reduced while the III-nitride compound semiconductor material is activated.Type: ApplicationFiled: February 4, 2002Publication date: July 10, 2003Applicant: EPITECH CORPORATION, LTD.Inventor: Shi-Ming Chen
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Patent number: 6580102Abstract: Quantum computing systems and methods that use opposite magnetic moment states read the state of a qubit by applying current through the qubit and measuring a Hall effect voltage across the width of the current. For reading, the qubit is grounded to freeze the magnetic moment state, and the applied current is limited to pulses incapable of flipping the magnetic moment. Measurement of the Hall effect voltage can be achieved with an electrode system that is capacitively coupled to the qubit. An insulator or tunnel barrier isolates the electrode system from the qubit during quantum computing. The electrode system can include a pair of electrodes for each qubit. A readout control system uses a voltmeter or other measurement device that connects to the electrode system, a current source, and grounding circuits. For a multi-qubit system, selection logic can select which qubit or qubits are read.Type: GrantFiled: June 5, 2001Date of Patent: June 17, 2003Assignee: D-Wave Systems, Inc.Inventors: Zdravko Ivanov, Alexander Tzalentchuk, Jeremy P. Hilton, Alexander Maassen van den Brink
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Patent number: 6573202Abstract: Quantum computing systems and methods that use opposite magnetic moment states read the state of a qubit by applying current through the qubit and measuring a Hall effect voltage across the width of the current. For reading, the qubit is grounded to freeze the magnetic moment state, and the applied current is limited to pulses incapable of flipping the magnetic moment. Measurement of the Hall effect voltage can be achieved with an electrode system that is capacitively coupled to the qubit. An insulator or tunnel barrier isolates the electrode system from the qubit during quantum computing. The electrode system can include a pair of electrodes for each qubit. A readout control system uses a voltmeter or other measurement device that connects to the electrode system, a current source, and grounding circuits. For a multi-qubit system, selection logic can select which qubit or qubits are read.Type: GrantFiled: May 24, 2002Date of Patent: June 3, 2003Assignee: D-Wave Systems, Inc.Inventors: Zdravko Ivanov, Alexander Tzalentchuk, Jeremy P. Hilton, Alexander Maassen van den Brink
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Publication number: 20030094606Abstract: A method and structure for a d-wave qubit structure includes a qubit disk formed at a multi-crystal junction (or qubit ring) and a superconducting screening structure surrounding the qubit. The structure may also include a superconducting sensing loop, where the superconducting sensing loop comprises an s-wave superconducting ring. The structure may also include a superconducting field effect transistor.Type: ApplicationFiled: May 16, 2002Publication date: May 22, 2003Inventors: Dennis M. Newns, Chang C. Tsuei
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Patent number: 6563311Abstract: A solid-state quantum computing structure includes a d-wave superconductor in sets of islands that clean Josephson junctions separate from a first superconducting bank. The d-wave superconductor causes the ground state for the supercurrent at each junction to be doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents at the junctions create qubits for quantum computing. The quantum states can be uniformly initialized from the bank, and the crystal orientations of the islands relative to the bank influence the initial quantum state and tunneling probabilities between the ground states. A second bank, which a Josephson junction separates from the first bank, can be coupled to the islands through single electron transistors for selectably initializing one or more of the supercurrents in a different quantum state. Single electron transistors can also be used between the islands to control entanglements while the quantum states evolve.Type: GrantFiled: May 14, 2001Date of Patent: May 13, 2003Assignee: D-Wave Systems, Inc.Inventor: Alexandre M. Zagoskin
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Patent number: 6563310Abstract: A solid-state quantum computing structure includes a set of islands that Josephson junctions separate from a first superconducting bank. A d-wave superconductor is on one side of the Josephson junctions (either the islands' side or the bank's side), and an s-wave superconductor forms the other side of the Josephson junctions. The d-wave superconductor causes the ground state for the supercurrent at each junction to be doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents at the junctions create qubits for quantum computing. The quantum states can be uniformly initialized from the bank, and the crystal orientations of the islands relative to the bank influence the initial quantum state and tunneling probabilities between the ground states.Type: GrantFiled: May 14, 2001Date of Patent: May 13, 2003Assignee: D-Wave Systems, Inc.Inventor: Alexandre M. Zagoskin
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Patent number: 6559467Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of AlxByInzGa1-x-y-zN, InGaN1-a-bPaAsb, or AlxByInzGa1-x-y-zN1-a-bPaAsb.Type: GrantFiled: May 17, 2001Date of Patent: May 6, 2003Assignee: Technologies and Devices International, Inc.Inventors: Audrey E. Nikolaev, Yuri V. Melnik, Konstantin V. Vassilevski, Vladimir A. Dmitriev
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Patent number: 6559472Abstract: A method of depositing a thin film on a substrate in a semiconductor device using Atomic Layer Deposition (ALD) process parameters exposes the substrate to at least one adherent material in a quantity sufficient for the material to adsorb onto the substrate and thereby form an initiation layer. The initiation layer presents at least one first reactive moiety which is then chemically reacted with at least one first reaction material using atomic layer deposition conditions to form a second reactive moiety. The second reactive moiety is then chemically reacted with at least one second reaction material under process conditions sufficient to form a reaction layer over the initiation layer. The process may be repeated to form successive reaction layers over the initiation layer. The adherent material constituting the initiation layer is preferably one which is not substantially degraded by the atomic layer deposition parameters.Type: GrantFiled: January 14, 2002Date of Patent: May 6, 2003Assignee: Micron Technology, Inc.Inventors: Gurtej Sandhu, Garo J. Derderian
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Patent number: 6541789Abstract: In a method of manufacturing a Josephson junction, a first superconductive layer is formed on a substrate. An insulating film is formed on the first superconductive layer. The insulating film is etched to have an inclination portion. The first superconductive layer is etched using the etched insulating film as a mask, to have an inclination portion. A barrier layer is formed on a surface of the inclination portion of the first superconductive layer. A second superconductive layer is formed on the barrier layer and the inclination portion of the insulating layer.Type: GrantFiled: August 30, 1999Date of Patent: April 1, 2003Assignee: NEC CorporationInventors: Tetsuro Sato, Jian-Guo Wen, Naoki Koshizuka, Shoji Tanaka
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Patent number: 6476413Abstract: A high temperature superconducting Josephson junction device with ramp-edge geometry in which silver is combined in a composite with YBa2Cu3O7, yttrium-barium-copper-oxide, to form the electrodes, or PrBa2Cu3O7, praseodymium-barium-copper-oxide, to form the weak link.Type: GrantFiled: April 24, 1998Date of Patent: November 5, 2002Assignee: The Regents of the University of CaliforniaInventors: Quanxi Jia, Xin Di Wu, Steven R. Foltyn, David W. Reagor
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Publication number: 20020096429Abstract: A Josephson junction includes first and second electrodes, each of which is formed of superconductive material. The first electrode has a first electrode face. A barrier of the junction extends from the first electrode to the second electrode. The barrier has a first barrier face opposing and adjoining the first electrode face. The barrier is formed of non-superconductive barrier material and superconductive barrier material. A concentration of the superconductive barrier material is greater than zero at the first barrier face, whereby the first barrier face is formed at least partially of the superconductive barrier material.Type: ApplicationFiled: November 5, 2001Publication date: July 25, 2002Inventors: Ju Gao, Jinglan Sun
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Publication number: 20020084453Abstract: A hybrid oxide heterostructure device is disclosed. The device includes a substrate, and formed monolithically on the substrate, by atomic layer-by-layer molecular-beam epitaxy, successive metal oxide layers forming a high-temperature superconducting (HTS) structure and a multi-layer magnetic memory/storage structure. The HTS structure includes one or more HTS metal oxide layers formed on the substrate, and electrical contacts formed on the one or more HTS layers. The magnetic-memory structure includes one or more metal oxide magnetic layers formed monolithically on, below, or between the layer(s) of the HTS device, and having electrical contacts formed on one or more of the magnetic layers. Application of current or voltage to an HTS structure, under conditions effective to establish a superconducting current in the HTS structure, is effective to alter read or write characteristics of the memory-storage structure.Type: ApplicationFiled: September 27, 2001Publication date: July 4, 2002Inventor: Ivan Bozovic
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Publication number: 20020074626Abstract: There is provided a superconducting device including a substrate, a first superconductor layer supported by the substrate and containing Ln, AE, M and O, and a second superconductor layer containing a material represented by a formula of (Yb1−yLn′y)AE′2M′3Oz, the first and second superconductor layers forming a junction, and atomic planes each including M and O in the first superconductor layer and atomic planes each including M′ and O in the second superconductor layer being discontinuous to each other in a position of the junction, wherein each of Ln and Ln′ represents at least one metal of Y and lanthanoids, each of AE and AE′ represents at least one of alkaline earth metals, each of M and M′ represents a metal which contains 80 atomic % or more of Cu, y represents a value between 0 and 0.9, and z represents a value between 6.0 and 8.0.Type: ApplicationFiled: October 30, 2001Publication date: June 20, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshihiko Nagano, Jiro Yoshida
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Patent number: 6388268Abstract: A semiconducting yttrium-barium-copper-oxygen(YBCO) device which locally converts a semiconducting YBCO film to a nonconducting YBCO film by a conductive atomic force microscope (AFM), a superconducting YBCO device which locally converts a superconducting YBCO film to nonsuperconducting YBCO by an AFM, and manufacturing methods thereof are provided. According to a method of manufacturing a semiconducting YBCO device or a superconducting YBCO device locally converted by an AFM tip, a voltage is applied to the local region of a semiconducting YBCO channel or a superconducting YBCO channel by an AFM tip. This can produce a nonconducting YBCO region or nonsuperconducting YBCO region to thereby manufacture a tunnel junction easily without any patterning process by microfabrication including photolithography and dry/wet etching.Type: GrantFiled: September 26, 2000Date of Patent: May 14, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Byong-man Kim, Insang Song
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Patent number: 6384424Abstract: A superconducting thin film pattern (20) formed from an oxide superconducting thin film is formed on a sapphire substrate (10) having a step (11) via a CeO2 buffer layer, and the step (11) and superconducting thin film pattern (20) are formed such that the step (11) crosses a predetermined portion of a square thin film pattern (22) having an opening portion (23) at the central portion. Step-edge Josephson junctions (26, 27) are formed at the portion crossed by the step (11), and a SQUID is obtained. The sapphire substrate is relatively inexpensive, and a large substrate can be used.Type: GrantFiled: October 11, 2000Date of Patent: May 7, 2002Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hirokazu Kugai, Yasuyuki Matsui, Tatsuoki Nagaishi, Hideo Itozaki
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Patent number: 6353234Abstract: The invention concerns a layered arrangement comprising at least one layer based on a high-temperature superconductive material with at least one unit cell having a CuO2 plane, the layer being connected to a non-supeconductive layer. A modified interface layer is provided between the two layers. Alternatively, at least one of the contacting layers can be modified in the interface region. Modification can be brought about by doping with metallic ions or implantation.Type: GrantFiled: February 11, 1999Date of Patent: March 5, 2002Assignee: Forschungszentrum Julich GmbHInventors: Mikhail Faley, Ulrich Poppe, Chunlin Jia
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Publication number: 20020025586Abstract: A method of forming a novel high temperature superconducting Josephson junction which is capable of achieving a formation of a Josephson junction having high characteristic conveniently and quickly without necessitating costly micromachining facilities. Two high temperature superconducting whisker crystals are crossed with each other on a substrate and subjected to thermal treatment to form a Josephson junction between the two high temperature superconducting whisker crystals.Type: ApplicationFiled: August 21, 2001Publication date: February 28, 2002Inventors: Yoshihiko Takano, Takeshi Hatano, Akira Ishii, Syunichi Arisawa, Kazumasa Togano
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Patent number: 6348699Abstract: A superconductive device is disclosed, which has specific characteristics of a generator and/or detector of sub-millimeter wave length radiation, comprising a two-dimensional lateral array of mesas (column-shaped elements) each containing vertically stacked Josephson junctions on top of one another. This device is capable of covering the entire frequency range between the microwave and far infrared spectral regions, in plurality of applications, where radiation emission and detection is involved. According to its various embodiments, thin columns (stacks) of Josephson junctions are monolithically built between superconducting electrical top and bottom contact layers. Mutually isolated segments cut out of the contact layers allow for optimization of circuit parameters such as impedance matching to load and maximizing the output power. External electronic control allows modulation of the radiation field and other operation modes of the device.Type: GrantFiled: May 19, 1999Date of Patent: February 19, 2002Assignee: Oxxel Oxide Electronics Technology GmbHInventor: Alfred Zehe
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Patent number: 6328942Abstract: Compounds of the general formula A4MeSb3O12 wherein A is either barium (Ba) or strontium (Sr) and Me is an alkali metal ion selected from the group consisting of lithium (Li), sodium (Na) and potassium (K) have been prepared and included in high critical temperature thin film superconductors, ferroelectrics, pyroelectrics, piezoelectrics, and hybrid device structures.Type: GrantFiled: May 8, 2000Date of Patent: December 11, 2001Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Arthur Tauber, Steven C. Tidrow, William D. Wilber, Robert D. Finnegan
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Publication number: 20010035524Abstract: A superconductive device is disclosed, which has specific characteristics of a generator and/or detector of sub-millimeter wavelength radiation, comprising a two-dimensional lateral array of mesas (column-shaped elements) each containing vertically stacked Josephson junctions on top of one another. This device is capable of covering the entire frequency range between the microwave and far infrared spectral regions, in a plurality of applications, where radiation emission and detection is involved. According to its various embodiments, thin columns (stacks) of Josephson junctions are monolithically built between superconducting electrical top and bottom contact layers. Mutually isolated segments cut out of the contact layers allow for optimization of circuit parameters such as impedance matching to load and maximizing the output power. External electronic control allows modulation of the radiation field and other operation modes of the device.Type: ApplicationFiled: June 20, 2001Publication date: November 1, 2001Applicant: OXXEL OXIDE ELECTRONICS TECHNOLOGY GMBHInventor: Alfred Zehe
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Patent number: 6287969Abstract: Disclosed herein is a method of forming a superconductor, comprising the steps of: providing a substrate and exposing the substrate to a first atmosphere, including precursors to form a first epitaxial layer segment. The first layer segment is then exposed to a second atmosphere, including precursors to form a second epitaxial layer segment, and the second layer segment is exposed to a third atmosphere including precursors to form a third epitaxial layer segment. Each of the first and third layer segments are each formed from a superconductor material and the second layer segment is formed from a material different from the first and third layer segments and the first, second and third layer segments have a collective thickness, the third layer segment having an outer surface with a roughness which is less than that of a single layer of the superconductor material with a thickness equal to the collective thickness.Type: GrantFiled: May 6, 1999Date of Patent: September 11, 2001Assignee: McMaster UniversityInventors: Robert A. Hughes, Patrick J. Turner, John S Preston
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Patent number: 6263219Abstract: A SQUID made of an oxide superconducting thin film is formed on a sapphire substrate. CeO2 film, RBa2Cu3O7−x film (“R” indicates a rare earth element chosen among a group formed of Yb, Er, Ho, Y, Dy, Gd, Eu, Sm and Nd) and SrTiO3 film are deposited on the substrate top of the sapphire substrate successively. Furthermore, an oxide superconducting thin film to form a SQUID is deposited on the SrTiO3 film.Type: GrantFiled: March 23, 1999Date of Patent: July 17, 2001Assignee: Sumitomo Electric Industries, Inc.Inventor: Tatsuoki Nagaishi
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Patent number: 6188919Abstract: A SNS Josephson junction (10) is provided for use in a superconducting integrated circuit. The SNS junction (10) includes a first high temperature superconducting (HTS) layer (14) deposited and patterned on a substrate (18), such that the first HTS layer (14) is selectively removed to expose a top surface of the substrate (18) as well as to form an angular side surface (22) on the first HTS layer (14) adjacent to the exposed top surface of the substrate (18). Ion implantation is used to form a junction region (12) having non-superconducting properties along the angular side surface (22) of the first HTS layer (14). A second HTS layer (16) is then deposited and patterned over at least a portion of the first HTS layer (14) and the exposed top surface of the substrate (18), thereby forming a SNS Josephson junction.Type: GrantFiled: May 19, 1999Date of Patent: February 13, 2001Assignee: TRW Inc.Inventors: John R. LaGraff, James M. Murduck, Hugo W-K. Chan
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Patent number: 6157044Abstract: A tunnel junction type Josephson device includes a pair of superconductor layers formed of a compound oxide superconductor material and an insulator layer formed between the pair of superconductor layers. The insulator layer is formed of a compound oxide which is composed of the same constituent elements as those of the compound oxide superconductor material of the superconductor layers but with an atomic ratio which does not present a superconductivity characteristics. In addition, the superconductor layers and the insulator layer are continuously formed while supplying oxygen.Type: GrantFiled: March 10, 1993Date of Patent: December 5, 2000Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hidenori Nakanishi, Saburo Tanaka, Hideo Itozaki, Shuji Yazu
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Patent number: 6147360Abstract: This invention provides a superconducting device with good characteristics that can be reproduced at an arbitrary place on a substrate and a method of manufacturing the same. A convex region (a processed, linearly-shaped platinum thin film) of oriented metal is provided on a substrate as a gate electrode. Then, an oxide insulating film (SrTiO.sub.3 thin film) is deposited on the convex region, and further a YBa.sub.2 Cu.sub.3 O.sub.7 oxide superconducting thin film is deposited on the oxide insulating film. Accordingly, a grain boundary part is formed on the convex region. A drain electrode and a source electrode are formed facing each other with the grain boundary part in between.Type: GrantFiled: May 21, 1998Date of Patent: November 14, 2000Assignee: Matsushita Electric Industrial Co. Ltd.Inventors: Akihiro Odagawa, Hideaki Adachi, Kentaro Setsune
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Patent number: 6121630Abstract: A high-temperature superconducting thin film of compound oxide selected from the group consisting of:Y.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Ho.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Lu.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x,Sm.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Nd.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Gd.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x,Eu.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Er.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Dy,Ba.sub.2 Cu.sub.3 O.sub.7-x,Tm.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Yb.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x La.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x,(La, Sr).sub.2 CuO.sub.4-x,which is deposited on a substrate of sapphire, with the outer surface of the high-temperature superconducting thin film being covered with a protective crystalline film of SrTiO.sub.3.Type: GrantFiled: May 20, 1998Date of Patent: September 19, 2000Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hideo Itozaki, Saburo Tanaka, Nobuhiko Fujita, Shuji Yazu, Tetsuji Jodai
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Patent number: 6087711Abstract: The present invention discloses an integrated circuit that is wired with a high-temperature superconductive material that is superconductive at temperatures of about 70.degree. K and above, and methods of making the integrated circuit. The front-end manufactured semiconductor structure is patterned with a preferred precursor metal or metal oxide and a complementary compound is superposed and reacted to form wiring lines of superconductor ceramics that complete integrated circuits within the front-end manufactured semiconductor structure. The front-end manufactured semiconductor structure is alternatively patterned first with the complementary compound and the precursor metal is thinly patterned by ion implantation. The front-end manufactured semiconductor structure is then treated to form wiring lines of superconductor ceramics that complete integrated circuits within structure.Type: GrantFiled: February 17, 1998Date of Patent: July 11, 2000Assignee: Micron Technology Inc.Inventor: John H. Givens
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Patent number: 6087687Abstract: A semiconductor device is provided, which is readily and correctly designed even when the semiconductor device is further miniaturized. This device includes a semiconductor substrate, a source region and a drain region formed to be apart from each other in the substrate, a gate insulator formed on a main surface of the substrate, and a gate electrode formed on the gate insulator. The gate insulator includes a ferroelectric region and a dielectric region located in a same level as that of the ferroelectric region. The ferroelectric region is contacted with the main surface of the substrate and the gate electrode. The dielectric region is contacted with the main surface of the substrate and the ferroelectric region. The whole bottom of the ferroelectric region is contacted with the main surface of the substrate in such a way that no overlap exists between the ferroelectric region and the dielectric region.Type: GrantFiled: May 15, 1997Date of Patent: July 11, 2000Assignee: NEC CorporationInventor: Yuukoh Katoh
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Patent number: 6084246Abstract: Compounds of the general formula A.sub.4 MeSb.sub.3 O.sub.12 wherein A is either barium (Ba) or strontium (Sr) and Me is an alkali metal ion selected from the group consisting of lithium (Li), sodium (Na) and potassium (K) have been prepared and included in high critical temperature thin film superconductors, ferroelectrics, pyroelectrics, piezoelectrics, and hybrid device structures.Type: GrantFiled: August 10, 1999Date of Patent: July 4, 2000Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Arthur Tauber, Steven C. Tidrow, William D. Wilber, Robert D. Finnegan
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Patent number: 6023072Abstract: A Josephson junction having a laminar structure which includes a substrate, a first superconductive layer deposited on the substrate, a non-superconductive layer deposited on the first superconductive layer, and a second superconductive layer deposited on the non-superconductive layer. The laminar structure has three segments, including: a first planar segment, a second planar segment, and a ramp segment connecting the two planar segments at an ascent angle thereto. The layers are of substantially uniform thickness in the three segments, with the substrate being thinner in the second planar segment than in the first planar segment and having a constantly-decreasing thickness in the ramp segment. The superconductive layers and the non-superconductive layer are deposited in-situ and are epitaxial with a c-axis in a direction substantially normal to the first and second planar segments.Type: GrantFiled: March 27, 1997Date of Patent: February 8, 2000Assignee: TRW Inc.Inventor: Arnold H. Silver
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Patent number: 6011981Abstract: An oxide superconducting multilayered thin film structure having a laminated layer structure of oxide superconductor thin film layers and non-superconductor thin film layers constituted by a combination of material groups for making strain free interfaces among both thin film layers. For example, an oxide superconductor multilayered film constituted by a laminated layer structure where thin films of an oxide superconductor represented by the chemical formula of M'Ba.sub.2 Cu.sub.3 O.sub.7-.delta. (M'; a rare earth element of Nd, Sm, Eu or the like or an alloy of these, .delta.; oxygen depletion amount) and thin films of an oxide represented by the chemical formula of M*Ba.sub.2 Cu.sub.3 O.sub.7-.delta. (M*; an element of Pr, Sc or the like or an alloy of these, .delta.; oxygen depletion amount) are alternately stacked. The oxide thin films are thin films fabricated by a pulsed laser deposition process or a sputtering process. A Josephson device can be provided by using the multilayered film.Type: GrantFiled: March 10, 1997Date of Patent: January 4, 2000Assignee: International Superconductivity Technology CenterInventors: Gustavo Alvarez, Furen Wang, Jian-Guo Wen, Naoki Koshizuka, Youichi Enomoto, Tadashi Utagawa, Shoji Tanaka
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Patent number: 5986280Abstract: A magnetic sensor comprises a SQUID made of a superconducting thin film. The superconducting thin film has a washer pattern and a terminal portion. The washer pattern has a non-square one hole pattern and a pair of slit patterns. The hole pattern has rectangle shape and includes the center of the washer pattern. The slit patterns having a straight shape growing parallel to the long side of the hole pattern, from the outside edge of the washer pattern toward the inside of the washer pattern. This outside edge of the washer pattern is the nearest to the hole pattern. There is an artificial grain boundary in the domain that spacing between the hole pattern and the slit pattern is narrowest. There is no artificial grain boundary in the other domain at all.Type: GrantFiled: September 3, 1997Date of Patent: November 16, 1999Assignee: Sumitomo Electric Industries, Ltd.Inventor: Hirokazu Kugai
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Patent number: 5962866Abstract: A superconductor device has a substrate with an inclined surface that divides the substrate surface into a lower planar substrate surface and an upper planar substrate surface. A lower layer of an anisotropic superconductor material is epitaxially deposited on the lower planar substrate surface so that an a-axis of the anisotropic superconductor material of the lower layer is exposed at a top edge of the lower layer. An upper layer of an anisotropic superconductor material is epitaxially deposited on the upper planar substrate surface so that an a-axis of the anisotropic superconductor material of the upper layer is exposed at a top edge of the upper layer. A layer of a non-superconductor material overlies the inclined surface and the layers of anisotropic superconductor material.Type: GrantFiled: June 27, 1996Date of Patent: October 5, 1999Assignee: Biomagnetic Technologies, Inc.Inventors: Mark S. DiIorio, Shozo Yoshizumi, Kai-Yueh Yang
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Patent number: 5955400Abstract: Pickup coils constructed by superconductors and a SQUID part are formed on a single substrate. The pickup coils are parallelly connected to two other superconductors (inductance of the SQUID ring) in a SQUID ring, which consists of two Josephson junctions and two superconductive lines. Each of the superconductors can be a superconductive line of one loop or a washer type coil. Each pickup coil occupies about one half of the area of the substrate and the SQUID and the pickup coils are symmetrical with respect to the center line of the substrate.Type: GrantFiled: August 4, 1997Date of Patent: September 21, 1999Assignee: Hitachi, Ltd.Inventors: Koichi Yokosawa, Shinya Kuriki
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Patent number: 5942765Abstract: In the random access memory utilizing an oxide high-temperature superconductor, a first high-temperature superconductor layer 1, a non-superconductor layer 2, a second high-temperature superconductor layer 3 and a non-superconductor layer 4 are formed on an insulated substrate. The first high-temperature superconductor layer 1 is formed in a first loop, forming a memory storage superconductor quantum interference device by two Josephson junctions and a control current line I.sub.WX (6) and a bias current line I.sub.WY (8) in order to store the flux quantum. The second high-temperature superconductor layer 3 is formed in a second loop, forming a reading superconducting quantum interference device by two Josephson junctions and a control current line I.sub.RX (5) and a bias current line I.sub.RY (7).Type: GrantFiled: November 20, 1997Date of Patent: August 24, 1999Assignee: International Superconductivity Technology CenterInventors: Kazunori Miyahara, Yoichi Enomoto, Shoji Tanaka
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Patent number: 5925892Abstract: A Josephson junction element having a substrate of a single crystal having a V-shaped notch formed in a surface of the substrate and a wiring pattern of an oxide superconductor formed on the surface of the substrate and crossing the notch to form a weak link region in the pattern at a position above the notch. The notch is defined by first and second walls joining with each other at the bottom of the notch and has first and second corners at which the first and second walls meet the surface of the substrate. The first and second corners have radii of curvature of 5-50 nm and 50-500 nm, respectively, provided that the difference in radius of curvature between the first and second corners is not smaller than 10 nm. The notch is formed by obliquely irradiating a predetermined portion of the substrate with a focused ion beam.Type: GrantFiled: June 12, 1997Date of Patent: July 20, 1999Assignees: International Superconductivity Technology Center, Sharp Kabushiki Kaisha, NEC CorporationInventors: Yuji Mizuno, Katsumi Suzuki, Youichi Enomoto
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Patent number: 5910662Abstract: A semiconductor substrate comprising a single crystal substrate base such a silicon and a superconducting thin film layer deposited on said substrate base and composed of compound oxide such as Ln.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-.delta.. (Ln is lanthanide).Type: GrantFiled: December 14, 1993Date of Patent: June 8, 1999Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hideo Itozaki, Keizo Harada, Naoji Fujimori, Shuji Yazu, Tetsuji Jodai
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Patent number: 5892243Abstract: A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T.sub.c, superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T.sub.c, superconductive layer. The dielectric layer and the first high-T.sub.c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T.sub.c, superconductive layer (second base electrode layer) 54 directly on the first high-T.sub.c superconductive layer, a normal barrier layer 56 on the second high-T.sub.c superconductive layer, and a third high-T.sub.c superconductive layer 58 (counterelectrode) on the barrier layer. The ramp edge is typically formed by photoresist masking and ionmilling. A plasma etch step can be performed in-situ to remove the photoresist layer 62 following formation of the ramp edge.Type: GrantFiled: December 6, 1996Date of Patent: April 6, 1999Assignee: TRW Inc.Inventor: Hugo W. Chan
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Patent number: 5889289Abstract: High temperature superconductor composite thin film devices with easily moved Josephson vortices are described having high T.sub.c and good magnetic vortex properties. A preferred composite material was YBCO/CeO.sub.2 thin film on a MgO substrate. The superconductor composites were preferably formed by off-axis co-sputtering. A surprising recovery in properties was seen after plasma etching with oxygen.Type: GrantFiled: August 28, 1997Date of Patent: March 30, 1999Assignee: The United States of America as represented by the Secretary of the NavyInventors: Edward J. Cukauskas, Laura H. Allen
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Patent number: 5885937Abstract: This invention provides a superconducting tunnel junction element showing satisfactory Josephson effect. The element includes a Bi-based layered compound such as Bi.sub.2 Sr.sub.2 (Ca.sub.0.6 Y.sub.0.4)Cu.sub.2 O.sub.8, Bi.sub.2 Sr.sub.2 Cu.sub.2 O.sub.6 and Bi.sub.2 Sr.sub.2 CaCu.sub.2 O.sub.8 as the barrier layer between the superconducting oxide electrodes. The structural matching of the superconducting oxide with the Bi-based compound is supposed to be good. Some kinds of Cu-based superconducting oxides such as YSr.sub.2 Cu.sub.2.7 Re.sub.0.3 O.sub.7, Sr.sub.2 CaCu.sub.2 O.sub.6 and (La.sub.0.9 Sr.sub.0.1).sub.2 CuO.sub.4 are used for the electrodes to obtain a Josephson element which can work at a high temperature. When using the superconducting oxides including Ba such as YBa.sub.2 Cu.sub.3 O.sub.7 for the electrode, forming a thin film between the electrode and the barrier is better to prevent Ba from reacting with Bi in the barrier layer.Type: GrantFiled: July 7, 1997Date of Patent: March 23, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideaki Adachi, Masahiro Sakai, Akihiro Odagawa, Kentaro Setsune
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Patent number: 5877122Abstract: An oxide superconductor element, produced by forming a damaged region on a substrate surface by the Ga.sup.+ focusing ion beam method and then depositing an oxide superconductor thin-film over it, is characterized in that a NdBa.sub.2 Cu.sub.3 O.sub.7-y (0.ltoreq.y.ltoreq.0.5) oxide superconductor is used in a tunnel junction having a tunneling barrier region with weak superconductivity.Type: GrantFiled: May 17, 1996Date of Patent: March 2, 1999Assignees: Fujitsu Ltd., Sharp Kabushiki Kaisha, NEC Corp., International Superconductivity Technology CenterInventors: Yoshihiro Ishimaru, Yuuji Mizuno, Katsumi Suzuki, Youichi Enomoto, Shoji Tanaka
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Patent number: 5863868Abstract: A SQUID 10 was multiple junctions, each junction allowing a critical current to flow therethrough. The SQUID 10 comprises a laminar structure including: (a) a substantially planar substrate 12; (b) a first high temperature superconductive layer 14 of substantially uniform thickness deposited on the substrates; (c) a dielectric layer 16 deposited on the first superconductive layer 14, the dielectric layer 16 comprising a planar level segment 18 having two ramp segments defining SQUID junctions at opposing ends 20 and defining SQUID hole; and (d) a second high temperature superconductive layer 24 of substantially uniform thickness deposited on the dielectric layer 16, the second high temperature superconductive layer 24 covering all three segments of the dielectric layer 16.Type: GrantFiled: September 25, 1997Date of Patent: January 26, 1999Assignee: TRW Inc.Inventors: Hugo Wai-Kung Chan, Kenneth P. Daly, James M. Murduck
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Patent number: 5828078Abstract: The present invention presents an electrostatic discharge and power surge protected circuit board (10) and method for providing an electrostatic discharge and power surge protected circuit board. The protected circuit board (10) includes temperature sensitive conducting material (14) and semiconductor circuit components (12). The temperature sensitive conducting material (14) has a critical current density, provides a high impedance when the critical current density is exceeded, and preferably comprises a high temperature superconductor. Preferably, the temperature sensitive conducting material (14) and the semiconductor circuit components (12) are coupled in series. In a method aspect of the present invention, an electrostatic discharge protected circuit board (10) is provided by providing a current carrying mechanism (16) on the circuit board (10), and coupling the current carrying mechanism (16) to temperature sensitive conducting material (14).Type: GrantFiled: October 25, 1996Date of Patent: October 27, 1998Assignee: Hughes ElectronicsInventor: Nicholas A. Doudoumopoulos
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Patent number: RE37587Abstract: A SQUID includes a substrate and a superconducting current path of a patterned oxide superconductor material thin film formed on a surface of the substrate. A c-axis of an oxide crystal of the oxide superconductor material thin film is oriented in parallel to the surface of the substrate.Type: GrantFiled: March 6, 1998Date of Patent: March 19, 2002Assignee: Sumitomo Electric Industries Ltd.Inventors: Takashi Matsuura, Saburo Tanaka, Hideo Itozaki