Abstract: The present invention relates to a device for electrostatic discharge protection (ESD).

Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.

Abstract: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

Abstract: An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive type region, a first high concentration first conductive type region, and a second high concentration second conductive type region are formed in a surface of the second conductive type well. A third high concentration second conductive type region is formed in a surface of the first conductive type well. The first high concentration second conductive type region and the first high concentration first conductive type region are connected with a first power supply of a potential. The third high concentration second conductive type region is connected with a second power supply having a potential different from the potential of the first power supply.

Abstract: To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is connected to the output of the NMOS, to shift the output of the NMOS for boosting. Then, a back gate of the NMOS is connected, via a PMOS in an on state, to the power source. With this structure, the PMOS provides a resistor component when the output terminal short-circuits.

Abstract: A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.

Abstract: Ferroelectric thin film devices including a passivation structure to reduce or control a leakage path between two electrodes and along an interface between a ferroelectric thin film layer and a passivation layer are described. Methods for fabricating such devices are also disclosed. The passivation structure includes a first passivation layer that includes an opening exposing a portion of the ferroelectric thin film layer allowing a second passivation layer to contact the thin film layer through the opening. In an exemplary embodiment, the opening is a rectangular ring surrounding an active region of a capacitor. In another exemplary embodiment, the second passivation layer also contacts the second electrode, a portion of which is also exposed through the opening. In another exemplary embodiment, current flows along the interface between the thin film layer and the passivation layer in an integrated resistor.

Abstract: A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

Abstract: In an integrated circuit, a diode is interposed between the semiconductor substrate and the contact pad to an external bias voltage, and the substrate is biased at an internal voltage reference. Between each contact pad of the integrated circuit and semiconductor substrate, there is positioned a protection device against permanent overloads and a protection device against electrostatic discharges. By isolating the semiconductor substrate from the external voltages source and by placing a protection device between each contact pad and the substrate, a broad, general protection of the integrated circuit is obtained against all the destructive phenomena such as overloads, positive and negative overvoltages, polarity reversal and electrostatic discharges.

Abstract: Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.

Abstract: A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad is a large, plate, and ideal conductor, the connected pad and the ESD device are capable of distributing current in the ESD device averagely.

Abstract: The present invention realizes the miniaturization of a semiconductor device. On a first insulation film, an island-like semiconductor layer and a second insulation film which surrounds the semiconductor layer are formed, and resistance elements (for example, poly-silicon resistance elements) which are formed of a conductive film are arranged to be overlapped to an upper surface of the semiconductor layer in plane.

Abstract: In accordance with the objectives of the invention a new arrangement is provided for ESD protection of mounted flip chips. In a first embodiment of the invention, the Input/Output cells and power cells are provided with ESD protection that is connected to a dedicated bump pad. The substrate of the flip chip package interconnects all of the dedicated bump pads, completing the ESD network. Under the second embodiment of the invention, the Input/Output cells and power cells are provided with ESD protection that is connected to a dedicated bump pad, a last metal layer interconnects all of the dedicated bump pads, completing the ESD network.

Abstract: An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection circuit includes a silicon controlled rectifier (SCR) having at least one first type high dopant region coupled to a first reference potential of the protected circuitry, and at least one second type high dopant region coupled to a second reference potential of the IC. The SCR is triggered by an external on-chip trigger device, which is adapted for injecting a trigger current into at least one gate of the SCR.

Abstract: A protection circuit for protecting an integrated circuit pad 201 against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor 202 (preferably pMOS) in a substrate 205 (preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground 203. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a component 221 determining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor 222 (for example about 40 to 60?) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion.

Abstract: Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.

Abstract: The present invention provides an ESD protection device or structure that exploits the high conductivity of a heavily doped heterojunction base of a standard SiGe bipolar junction transistor (BJT) cell. This improved ESD protection scheme further uses the combination of trench isolation and buried subcollector layer of the SiGe BJT to confine ESD current, minimizing parasitic substrate leakage and achieving large forward voltages while imposing minimal parasitic capacitive loads on a protected active device. Since the ESD protection structure is formed from conventional SiGe BJT transistor cells through modification of the contact metallization, it can be fabricated in an available SiGe BiCMOS fabrication process without additional processing steps, and characterization data already available for the SiGe BJTs can be used to model the performance of the ESD protection devices.

Abstract: The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor device. The resistor includes first and second crystalline layers which may or may not differ from one another. One of the first and second crystalline layers comprises doped silicon/germanium, and the other comprises doped silicon. The transistor device and resistor can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The invention also includes processes of forming semiconductor constructions, and in particular aspects, includes processes of forming resistor constructions.

Abstract: A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.

Abstract: A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current path through the first region is determined by a portion of a doping boundary between the first region and the second region.

Abstract: A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.

Abstract: An integrated circuit includes at least two circuit components formed on a common semiconductor substrate. Each circuit component has a self-contained supply voltage system. Coupling circuits couple the supply voltage systems for the at least two circuit components. Each coupling circuit includes at least one transistor having a base formed by or within the substrate itself; more specifically, by or within a region of the substrate contiguous with collector doping zones and emitter doping zones of the transistor. The resistance between the transistor base and the potentials of the two supply voltage systems coupled by each of the coupling circuits is the intrinsic resistance of the substrate between the region forming the base and one of each contact doping zone conductively connected to the collector or emitter through a metallization applied to the substrate.

Abstract: An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor, and a second thin film resistor disposed on the second dielectric layer. A first layer of interconnect conductors is disposed on the second dielectric layer and includes a first interconnect conductor contacting a first contact area of the first thin film resistor, a second interconnect conductor contacting a second contact area of the first thin film resistor, and a third interconnect conductor electrically contacting a first contact area of the second thin film resistor. A third dielectric layer is disposed on the second dielectric layer. A second layer of interconnect conductors is disposed on the third dielectric layer including a fourth interconnect conductor for contacting the second interconnect conductor.

Abstract: A semiconductor device, a method for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes a substrate section, a resistor formed on the substrate section, a metal pattern formed on the resistor, an oxide pattern formed on the metal pattern, and a protective film covering the resistor, the metal pattern and the oxide pattern. With this structure, the metal pattern sufficiently prevents formation of an oxide film on a surface of the resistor even when dry ashing or dry etching is performed in the manufacturing process.

Abstract: In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.

Abstract: Methods of fabricating semiconductor devices are provided. Transistors are provided on a semiconductor substrate. A first interlayer insulating layer is provided on the transistors. A second interlayer insulating layer is provided on the first interlayer insulating layer. The second interlayer insulating layer defines a trench such that at least a portion of an upper surface of the first interlayer insulating layer is exposed. A resistor pattern is provided in the trench such that the at least a portion of the resistor pattern contacts the exposed portion of the first interlayer insulating layer. Related methods are also provided.

Abstract: A process of forming a high resistance CMOS resistor with a relatively small die size is provided. According to an aspect of the present invention, the process of fabricating a high resistance resistor is a standard CMOS process that does not require any additional masking. An n-well is firstly formed in a p-type silicon substrate. A nitride film is then deposited and patterned to form a patterned mask layer. The patterned mask layer serves as a mask. A p-field region is formed in the n-well to form a CMOS resistor. The CMOS resistor according to the present invention has a resistance of 10 k?–20 k? per square.

Abstract: A vertical SCR-type switch including a control area having a first control region forming a first diode with a first neighboring region or layer, and a second control region forming a second diode with a second neighboring region or layer. A contact is formed on each of the first and second control regions and on each of the first and second neighboring regions or layers. The contacts are connected to terminals of application of an A.C. control voltage so that, when an A.C. voltage is applied, each of the two diodes is alternately conductive.

Abstract: As for the resistor on the semiconductor substrate, it is required to achieve obtaining a metal resistor, which can be formed in the latter half of a preliminary process for manufacturing a semiconductor, in addition to forming a polysilicon resistor, which is formed in the first half of the preliminary process. A capacitor having MIM structure comprises a lower electrode, a capacitive insulating film and an upper electrode, all of which are sequentially formed in this sequence. A resistor structure having MIM structure also comprises a lower electrode, a capacitive insulating film and a resistor, all of which are sequentially formed in this sequence. In this case, the biasing conditions thereof should be selected so that the resistor structure lower electrode of the MIM structure resistor is not coupled to any electric potential, and is in a floating condition.

Abstract: A semiconductor device has a p-type substrate, a low-concentration n-type region formed in the p-type substrate, a first high-concentration p-type region formed in the low-concentration n-type region and connected to a first electrode, a first high-concentration n-type region formed in the low-concentration n-type region and connected via a resistive element to the first electrode, a low-concentration p-type region formed contiguously with the first high-concentration n-type region, a second high-concentration n-type region and a second high-concentration p-type region formed in the p-type substrate and connected to a second electrode, and an element separator portion formed between the low-concentration p-type region and the second high-concentration n-type region. This makes it possible to control the switching characteristic of the electrostatic protection circuit with high accuracy and thus to cope with the thinning of the gate oxide film protected by the protection circuit.

Abstract: An ESD protection circuit includes: a first metal oxide semiconductor (MOS) transistor discharging an excessive electrostatic current generated between an input pad and an internal circuit, and having a first terminal connected to a ground voltage supply terminal; and a second MOS transistor discharging an electrostatic current generated between the input pad and the internal circuit, and having a gate and a first terminal connected to a bulk terminal of the first MOS transistor. The first terminal is connected to the ground voltage supply terminal through an interconnection line having a parasitic resistance with a predetermined value.

Abstract: The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor device. The resistor includes first and second crystalline layers which may or may not differ from one another. One of the first and second crystalline layers comprises doped silicon/germanium, and the other comprises doped silicon. The transistor device and resistor can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The invention also includes processes of forming semiconductor constructions, and in particular aspects, includes processes of forming resistor constructions.

Abstract: A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well. Further a finger-shaped diode (520) with its cathode (521) located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to ground and approximately perpendicular to the first n-well contact, acting as a guard wall (550).

Abstract: The electrostatic protection device provided between an input/output terminal and an internal circuit of a semiconductor device according to the present invention has a first insulated gate field effect transistor (MOS transistor) and a second MOS transistor that are connected mutually in parallel between an input/output wiring connected to the input/output terminal and an electrode wiring of a prescribed potential, where the first MOS transistor and the second MOS transistor are MOS transistors of the same channel type, the second MOS transistor has s higher drive capability than the first MOS transistor, and the electrostatic protection device is formed such that it is started by the first MOS transistor.

Abstract: A high voltage device. A high voltage MOS transistor is applied in the ESD protection device to the structure of which a doped region is added, generating a parasitic semiconductor controlled rectifier (SCR) having a shorter discharge path such that the SCR has faster response enhancing ESD protection.

Abstract: A multifinger ESD protection element has between an input wiring to which a surge current is input and a reference-potential wiring, 2n-number (where n is a natural number of 2 or greater) of fingers F1 to F2n. A drain resistor Rdi (i=1 to 2n), NMOS transistor Ti and source resistor Rsi are connected serially in each finger Fi in the order mentioned. A single unit Uj is constructed by two mutually adjacent fingers F2j?1 and F2j (where j is a natural number of 1 to n). In each unit the source of one transistor is connected to the gate of the other transistor and the source of this other transistor is connected to the gate of the first-mentioned transistor. The source S2j of finger F2j is connected to the source S2j+1 of the next unit Un+1. The 2n-number of fingers are connected in the form of a ring.

Abstract: In one embodiment, a concentric ring ESD structure includes a first p-type region and a second p-type region are formed in a layer of semiconductor material. The two p-type regions are coupled together with a floating n-type buried layer. The first and second p-type regions form a back-to-back diode structure with the floating n-type buried layer. A pair of shorted n-type and p-type contact regions is formed in each of the first and second regions. An isolation region is formed between the first and second p-type regions.

Abstract: A high-voltage device structure disposed in a substrate of a first conductivity type includes a first well and a second well each of a second conductivity type, a source diffusion region and a drain diffusion region each of a first length located in the first well and the second well respectively, and a gate of a second length on the substrate surface. Since the gate of the second length is longer than the source diffusion region and the drain diffusion region of the first length, the two sides of the gate have two spare regions. Two windows are located in the spare regions.

Abstract: An input protection circuit capable of precisely bypassing a surge current to a power source terminal and protecting the gate of a protective transistor from an electrostatic surge. The input protection circuit has an input terminal which receives an input signal, a first power source terminal which receives a first power source electric potential, and a first protective power source potential line connected to the first power source terminal for supplying the first power source electric potential to an input protection circuit. The input protection circuit has a first input protection transistor of a first conductive type having a drain connected to the input terminal, a gate and a source connected to the first protective power source potential line.

Abstract: Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range ?40 C to +85 C. Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.

Abstract: An electrically programmable fuse includes a metal-oxide-semiconductor (MOS) programmable transistor that is gate-source coupled by a resistive element. The resistive element can comprise a gate-source coupled MOS transistor. If the MOS transistor is unprogrammed, then the resistive element ensures that the programmable transistor is turned off during read operations. However, when a programming voltage is applied across the source and drain terminals of the programmable transistor, the resistive element allows the programming voltage to be capacitively coupled to the gate of the programmable transistor from its drain. This turns the programmable transistor on, thereby reducing the snapback voltage of the programmable transistor, and hence, the required programming voltage. Once the snapback mode is entered, current flow through the programmable transistor increases until thermal breakdown occurs and the programmable transistor shorts out.

Abstract: The present invention relates to structures and methods that reduce ESD damage to electronic devices. In an embodiment, the structure is a parallel plate dissipative capacitor formed by sandwiching a dissipative dielectric layer between two conductive layers in series to the electronic device. The dissipative dielectric layer includes a nonconductive dielectric doped with a voltage dependent resistive material that defines a conductive threshold voltage. The structure functions as a voltage dependent resistor in response to an applied voltage such as an ESD surge voltage exceeding the defined conductive threshold voltage and dissipates the applied voltage into thermal energy before it can reach the electronic device and cause damage. The dissipative dielectric layer restores to a dielectric and the structure functions as a capacitor when the excess voltage is depleted that is drops below the defined conductive threshold voltage.

Abstract: An electrostatic discharge (ESD) protection circuit is provided for protecting transistors of an integrated circuit (IC) from ESD. The ESD protection circuit includes n transistors with n gates and less than n drains where n is an integer greater than 1. At least m resistors have first ends that communicate with at least one of the transistors of the IC, a blocking capacitor of the IC, an input pad of the IC, and an output pad of the IC, and second ends that connect to corresponding drain terminals of said drains where m is an integer greater than or equal to n/2.

Abstract: A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent thereto from above so that the laser beams or the equivalent strong light are radiated onto the impurity regions and on an boundary between the impurity region and an active region adjoining the impurity region.

Abstract: An SOI single crystalline chip structure includes an active device layer for having at least one SOI device placed thereon, a buried oxide layer under the active device layer, a metal layer under the buried oxide layer, and a silicon substrate under the metal layer. At least one through hole passing through the buried oxide layer is disposed at a first predetermined position of the buried oxide layer, and at least one concave hole not passing through the buried oxide layer is disposed at a second predetermined position of the bottom surface of the buried oxide layer.

Abstract: A pMOS transistor (601) is located in an n-well (602) and has at least one gate (603). Transistor (601) is connected between power pad Vdd or I/O pad (604) and ground potential Vss (605). Gate (603) is connected to power pad (604). The n-well (602) is capacitively (620) coupled to ground (605), decoupled from the transistor source (606) and floating under normal operating conditions. Under an ESD event, the diode formed by the source (606) and the n-well (602) is forward biased (n-well negatively biased) to turn on the lateral pnp transistor to discharge the ESD current. The well voltage keeps increasing up to the value that triggers the lateral bipolar pnp transistor. The ESD protection is scalable with the width of gate (603), improving with shrinking gate width.

Abstract: A semiconductor device includes a substrate, a well region formed in the substrate, a field effect transistor formed in the well region, and a diffused region, formed across the well region and the substrate for applying back gate potential to the well region, and forming a PN junction together with its periphery. The field effect transistor and the PN junction are connected between terminals for absorbing excess current so that an internal circuit connected to the terminals is protected.

Abstract: A doped region is provided on a substrate. A plane with conductive useful structures and a conductive filler structure is arranged at the surface of the substrate. The conductive filler structure is conductively connected to the doped region. In this way, charging of the conductive filler structure, which is provided for improving the planarity of the circuit arrangement and has no circuit-oriented function, is avoided.

Abstract: A multi-level metal interconnect structure and method for forming the same for improving a resistance of CMOS transistors to electrostatic discharge (ESD) transient events is disclosed. A semiconductor device including at least one NMOS transistor electrically connected along at least one circuit pathway to an input/output signal source and a reference voltage potential; and, electrically connecting at least the input/output signal source to the at least one NMOS transistor with a metal interconnect line extended in length by compacting at least a portion of the metal interconnect line length portion into a serpentine shape within a predetermined volume of the semiconductor device.