Abstract: A device includes standard cells in a layout of an integrated circuit. The standard cells include a first standard cell and a second standard cell disposed next to each other. The first standard cell is configured to operate as an electrostatic discharge (ESD) protection circuit and includes a first gate and a second gate. The first gate includes a first gate finger and a second gate finger that are arranged over a first active region, for forming a first transistor and a second transistor, respectively. The second gate is separate from the first gate. The second gate includes a third gate finger and a fourth gate finger that are arranged over a second active region, for forming a third transistor and a fourth transistor, respectively. The first transistor and the second transistor are connected in parallel, and the third transistor and the fourth transistor are connected in parallel.

Abstract: Provided is a semiconductor device including: a semiconductor substrate including a bulk donor; and a first buffer region of a first conductivity type, the first buffer region being provided on a lower surface side of the semiconductor substrate and having one or more doping concentration peaks and one or more hydrogen concentration peaks in a depth direction of the semiconductor substrate, in which a doping concentration at a shallowest concentration peak, out of the doping concentration peaks of the first buffer region, closest to the lower surface of the semiconductor substrate is 50 times as high as a concentration of the bulk donor of the semiconductor substrate or lower. The doping concentration at the shallowest concentration peak may be lower than a reference carrier concentration obtained when current that is 1/10 of rated current flows between an upper surface and the lower surface of the semiconductor substrate.

Abstract: An integrated circuit is provided with a protected circuit wherein a first FinFET operably coupled to a signal node is protected against electrostatic discharge voltage damage by a standard cell electrostatic discharge protection circuit which is connected between first and second voltage supplies and which includes a first FinFET diode connected between the signal node and the first voltage supply, and a second FinFET diode connected between the signal node and the second voltage supply, where the first and second FinFET diodes are each formed with a FinFET device comprising (1) a body well region forming a first diode terminal connected to one of the first or second voltage supplies, and (2) a shorted gate, source, and drain regions forming a second diode terminal connected to the signal node.

Abstract: An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.

Abstract: A semiconductor device includes a P-doped well having a first concentration of P-type dopants in the substrate; a P-doped region having a second concentration of P-type dopants in the substrate and extending around a perimeter of the P-doped well; a shallow trench isolation structure (STI) between the P-doped well and the P-doped region; an active area on the substrate, the active area including an emitter region and a collector region; a deep trench isolation structure (DTI) extending through the active area and between the emitter region and the collector region; and an electrical connection between the emitter region and the P-doped region.

Abstract: Devices and methods for switch body connections to achieve soft breakdown. In some embodiments, a field-effect transistor (FET) can include an assembly of source, gate, and drain implemented on an active region, a first body contact implemented at a first end of the assembly, and a second body contact implemented at a second end of the assembly. The second end can be distal from the first end along a width of the field-effect transistor.

Abstract: A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.

Abstract: Protection against electrostatic discharges is to be improved for electronic devices, or is to be provided in the first place. The device for protection against electrostatic discharges having an integrated semiconductor protection device comprises an inner region (1) configured at least as a thyristor (SCR) and at least one outer region (2a, 2b) configured as a corner region, which is formed and configured at least as a PNP transistor. The inner region (1) and the at least one outer region (2a, 2b) are arranged adjacent to one another.

Abstract: An electronic device includes: a control terminal, which extends on a first face of a substrate; a first conduction terminal, which extends in the substrate at the first face of the substrate; a first insulating layer interposed between the control terminal and the first conduction terminal; a conductive path, which can be biased at a biasing voltage; and a protection element, coupled to the control terminal and to the conductive path, which forms an electrical connection between the control terminal and the conductive path and is designed to melt, and thus interrupt electrical connection, in the presence of a leakage current higher than a critical threshold between the control terminal and the first conduction terminal through the first insulating layer.

Abstract: An electrostatic discharge (ESD) circuit including a booster cell is disclosed. The ESD circuit may include first and second rails configured to provide power to the ESD circuit. The first rail may include two spaced apart conductors. The ESD circuit may further include an input/output (I/O) pad and a power/ground (P/G) pad. The P/G pad may include a power clamp electrically coupled between the first and second rails. The booster cell may be physically located between the I/O pad and the P/G pad. The booster cell may provide an electrical connection between the two spaced apart conductors.

Abstract: Disclosed are a radio frequency transistor for improving radio frequency switch performance, a chip and a mobile terminal. The radio frequency transistor comprises a first metal layer, a second metal layer, a polysilicon layer and an active area, the first metal layer being connected to the active area via contact holes, the first metal layer being connected to the second metal layer via through holes. The wiring direction of the second metal layer is perpendicular to the wiring direction of the polysilicon layer, thereby reducing parallel areas between the polysilicon layer and the first metal layer and decreasing the numbers of contact holes and through holes, so as to reduce the off capacitance. In addition, space saved by the first metal layer wiring and the contact holes is utilized, thereby increasing the channel width of the radio frequency transistor accommodated in a same chip area, and reducing the on-resistance.

Abstract: According to an exemplary embodiment of the present invention, a display device includes a static electricity blocking circuit having a first conductive layer, a first semiconductor portion, a second semiconductor portion, a channel portion disposed therebetween, a first electrode connected to the first semiconductor portion through first signal line contact holes, and a second electrode connected to the second semiconductor portion through first power line contact holes. The first signal line contact holes are disposed closer to an outermost edge of the first semiconductor portion than an innermost edge thereof. The first power line contact holes are disposed closer to an outermost edge of the second semiconductor portion than an innermost edge thereof. The second conductive layer is closer to the innermost edge of the first semiconductor portion than the outermost edge thereof and is closer to the innermost edge of the second semiconductor portion than the outermost edge thereof.

Abstract: A semiconductor structure includes a semiconductor wafer having a topside and a backside. The wafer includes a first semiconductor well of a first conductive type, a second semiconductor well of a second conductive type different from the first conductive type, a plurality of first semiconductor doped regions of the first conductive type and a plurality of first through silicon vias (TSVs) filled with conductive material. The first semiconductor well is formed within the second semiconductor well and exposed to the topside. The semiconductor device and the first semiconductor doped regions are formed within the first semiconductor well, and the first semiconductor doped regions surround the semiconductor device. Each first TSV extends into a corresponding one of the first semiconductor doped regions from the backside through the first and second semiconductor wells and is connected to a DC voltage or a ground potential from the backside.

Abstract: A silicon controlled rectifier includes a substrate, an N-type well, a P-type well, a gate structure, a first N-type doped region, a second N-type doped region, a first P-type doped region, a second P-type doped region, a first STI, and a second STI. The N-type well and the P-type well are disposed in the substrate. The gate structure is disposed on the P-type well. The first N-type doped region is disposed in the N-type well at one side of the gate structure. The second N-type doped region is disposed in the P-type well at another side of the gate structure. The first P-type doped region is disposed in the N-type well. The second P-type doped region is disposed in the P-type well. The first STI is between the first N-type and first P-type doped regions. The second STI is between the second N-type and second P-type doped regions.

Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.

Abstract: Provided is a semiconductor structure including a first guard ring and a second guard ring. The first guard ring is located in a substrate. The first guard ring includes first doped regions and second doped regions arranged alternately. The first doped regions and the second doped regions have different conductivity types. The second guard ring is located adjacent to the first guard ring. The second guard ring includes third doped regions and fourth doped regions arranged alternately, and mask layers. Each of the third doped regions corresponds to each of the second doped regions. Each of the fourth doped regions corresponds to each of the first doped regions. The third doped regions and the first doped regions have the same conductivity type and are disposed in a staggered manner. The mask layers are respectively disposed on the substrate between the third doped regions and the fourth doped regions.

Abstract: A semiconductor device configures a protection element that protects a protection target element connected between a cathode electrode and an anode electrode when a parasitic transistor configured by a cathode region, a first conductivity type well layer, and a second conductivity type well is turned on and electrical continuity is established between the cathode electrode and the anode electrode. The semiconductor device includes a plurality of body regions in one cell of the protection element, and the plurality of body regions is brought in contact with the cathode electrode.

Abstract: Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.

Abstract: An output circuit with electrostatic discharge (ESD) protection in a semiconductor chip includes a first metal oxide semiconductor (MOS) transistor and a first resistor. The first MOS transistor includes a first terminal coupled to an output pad of the semiconductor chip, a bulk terminal and a gate terminal. The first resistor is coupled between the bulk terminal of the first MOS transistor and a first power supply terminal.

Abstract: A semiconductor device includes field-effect transistor having a gate, a drain, and a source. A first clamping circuit is connected between the drain and the gate. The first clamping circuit has a first clamp voltage that is lower than a source-to-drain breakdown voltage of the field-effect transistor. A first resistor in the device has a first end connected to a first node between the first clamping circuit and the gate. A second clamping circuit is connected between the drain and a second end of the first resistor. The second clamping circuit has a second clamp voltage is higher than the first clamp voltage and lower than the source-to-drain breakdown voltage.

Abstract: A transient voltage suppressor includes a substrate, a first well, a second well, a third well, a first electrode, a second electrode and a doped region. The first well is formed in the substrate and near a surface of the substrate. The second well is formed in the first well and near the surface. The third well is formed in the first well and near the surface. There is a gap between the second well and the third well. The first electrode and second electrode are formed in the second well and near the surface respectively. The first well and first electrode have a first electrical property. The second well, third well and second electrode have a second electrical property. The doped region is formed between the first electrode and second electrode and near the surface and electrically connected with the first well and third well.

Abstract: The present invention relates to a method for manufacturing an at least partly hollow MEMS structure. In a first step one or more through-going openings is/are provided in core material. The one or more through-going openings is/are then covered by an etch-stop layer. After this step, a bottom electrically conducting layer, one or more electrically conducting vias and a top electrically conducting layer are created. The bottom layer is connected to the vias and vias are connected to the top layer. The vias are formed by filling at least one of the one or more through-going openings. The method further comprises the step of creating bottom and top conductors in the respective bottom and top layers. Finally, excess core material is removed in order to create the at least partly hollow MEMS structure which may include a MEMS inductor.

Abstract: In accordance with an embodiment, a method of manufacturing an electrical component that may include a high voltage capacitor that includes providing a semiconductor material of a second conductivity type in which first doped region of a first conductivity type is formed. A plurality of doped regions of the first conductivity type and a plurality of doped regions of the second conductivity type are formed in the first doped region. A first p-n junction is formed between first doped regions of the first and second conductivity types and a second p-n junction is formed between second doped regions of the first and second conductivity types. A metallization system is formed above the doped regions so that capacitors are formed by a parallel connection of a first metal layer to a polysilicon layer and the first metal layer to a second metal layer.

Abstract: A circuit for implementing a discharge path in an input/output circuit of an integrated circuit is described. The circuit comprises an input/output pad; a first node coupled to a power reference voltage; a first impedance element implemented between the first node and the input/output pad; a second node coupled to a ground reference voltage; and a second impedance element implemented between the second node and the input/output pad. A method of implementing a discharge path in an input/output circuit of an integrated circuit is also disclosed.

Abstract: An integrated gate protection device P for a GaN power transistor D1 provides negative ESD spike protection. Protection device P comprises a smaller gate width wg enhancement mode GaN transistor Pm. The source of Pm is connected to its gate, the drain of Pm is connected to the gate input of D1, and the source of Pm is connected to the intrinsic source of D1. When the gate input voltage is taken negative below the threshold voltage for reverse conduction, Pm conducts and quenches negative voltage spikes. When device P comprises a plurality of GaN protection transistors P1 to Pn, connected in series, it turns on when the gate input voltage applied to the drain of P1 goes negative by more than the sum of the threshold voltages of P1 to Pn. The combined gate width of P1 to Pn is selected to limit the gate voltage excursion of D1.

Abstract: Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.

Abstract: A radio-frequency module includes a multilayer substrate, an input switch, an output switch, and filters. A switch IC is disposed on a main surface of the multilayer substrate. The input switch is disposed in the switch IC and includes a first input terminal and first output terminals. The output switch is disposed in the switch IC and includes second input terminals and a second output terminal. The filters are disposed outside the switch IC and are connected to the first output terminals and the second input terminals. In a plan view of the multilayer substrate, the first input terminal and the first output terminals are disposed close to a first side of an exterior of the switch IC, and the second input terminals and the second output terminal are disposed close to a second side different from the first side of the exterior of the switch IC.

Abstract: A semiconductor apparatus includes an input/output pad configured to exchange signals with an external device; a control pad configured to be inputted with a discharge signal from the external device; and a first electrostatic protection unit configured to form an electrostatic discharge path from the input/output pad to a first voltage supply line according to the discharge signal.

Abstract: A semiconductor device includes a substrate, a first semiconductor layer formed over the substrate, a second semiconductor layer formed over the first semiconductor layer, a third semiconductor layer formed over the second semiconductor layer, and a gate electrode, a source electrode, and a drain electrode that are formed over the third semiconductor layer. The first semiconductor layer includes a first nitride semiconductor. The second semiconductor includes a second nitride semiconductor. The third semiconductor layer includes a third nitride semiconductor. The concentration of oxygen included in the second semiconductor layer is less than 5.0×1018 cm?3. The concentration of oxygen included in the third semiconductor layer is greater than or equal to 5.0×1018 cm?3.

Abstract: A semiconductor device including drivers is disclosed, which can maximize driving ability of a plurality of drivers installed in a given region when the plurality of drivers is arranged in an array shape. The semiconductor device includes: a first active region; a second active region spaced apart from the first active region a predetermined distance in a first direction; a first gate finger group located in the first active region, and configured to include an odd number of gate fingers; and a second gate finger group located in the second active region, and configured to include an even number of gate fingers electrically coupled to the gate fingers of the first gate finger group.

Abstract: Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.

Abstract: Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage resistance and high speed in the semiconductor device using a polarization super junction, realize both the high voltage resistance and elimination of the occurrence of current collapse, operate at a high speed, and further the loss is low. The semiconductor device comprises a polarization super junction region and a p-electrode contact region. The polarization super junction region comprises an undoped GaN layer 11, an undoped AlxGa1-xN layer 12 with a thickness not smaller than 25 nm and not larger than 47 nm and 0.17?x?0.35, an undoped GaN layer 13 and a p-type GaN layer 14. When the reduced thickness tR is defined as tR=u+v(1+w×10?18) for the thickness u [nm] of the undoped GaN layer 13, the thickness v [nm] and the Mg concentration w [cm?3] of the p-type GaN layer 14, tR?0.864/(x?0.134)+46.0 [nm] is satisfied.

Abstract: A branch current monitor that includes reconfiguration.

Abstract: A device includes a first power node, a second power node, a first input node, a second input node, a protected circuit, and a switch circuit. The protected circuit is coupled between the first power node and the second power node, and the protected circuit is further coupled with the second input node. The switch circuit is coupled with the first power node, the second power node, the first input node, and the second input node. The switch circuit is configured to electrically decouple the first input node and the second input node after (a) the first power node is floating or electrically coupled to the second power node and (b) a voltage level at the first input node is greater than a voltage level at the second power node by a predetermined voltage value.

Abstract: Aspects of the invention provide a compact semiconductor device having a surge protection element, which can reliably protect against surge and is unlikely to be affected by manufacturing variation. By forming a parasitic n-p-n transistor on a guard ring, and adopting the parasitic n-p-n transistor as a surge protection element, it is possible to provide a compact semiconductor device having a surge protection element. Also, by adopting the parasitic n-p-n transistor as a surge protection element, it is possible to reduce the operating resistance in comparison with when using a parasitic n-p-n transistor as a surge protection element, and thus possible to improve the surge protection function. Further, by providing one surge protection element on the guard ring, rather than providing a surge protection element in each cell, it is possible minimize the effect of manufacturing variation (i.e., in-plane variation) on the surge protection function.

Abstract: A transient voltage suppressor device includes a transient voltage suppression circuit, a first voltage monitor lead connected to the transient voltage suppression circuit, and a second voltage monitor lead connected to the transient voltage suppression circuit. A voltage injection circuit having a plurality of output voltage levels is also connected to the transient voltage suppression circuit to provide indication via the first and second voltage monitors if the transient voltage suppression circuit is shorted or open.

Abstract: A semiconductor structure comprises a well, a first lightly doped region, a second lightly doped region, a first heavily doped region, a second heavily doped region and a gate. The first lightly doped region is disposed in the well. The second lightly doped region is disposed in the well and separated from the first lightly doped region. The first heavily doped region is disposed in the first lightly doped region. The second heavily doped region is partially disposed in the second lightly doped region. The second heavily doped region has a surface contacting the well. The gate is disposed on the well between the first heavily doped region and the second heavily doped region. The well has a first doping type. The first lightly doped region, the second lightly doped region, the first heavily doped region and the second heavily doped region have a second doping type.

Abstract: A power switch device includes a transistor and an ESD protection circuit. The transistor includes a source, a drain, and a gate, wherein a well region is disposed between the source and the drain. One end of the ESD protection circuit is coupled to the gate and another end thereof is coupled to the well region so as to form a protection circuit between the gate and the source and between the gate and the drain simultaneously.

Abstract: An integrated radiation sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second lateral bipolar junction transistors (BJTs) having opposite polarities. The first lateral BJT has a base that is electrically coupled to the sensing structure and is configured to generate an output signal indicative of a change in stored charge in the sensing structure. The second lateral BJT is configured to amplify the output signal of the first bipolar junction transistor. The first and second lateral BJTs, the sensing structure, and the substrate on which they are formed comprise a monolithic structure.

Abstract: A signal transceiving circuit comprising an IC including a signal transmitting part. The signal transmitting part comprises: a first I/O pad; a second I/O pad; a first output stage circuit, coupled to the first I/O pad; a second output stage circuit, coupled to the second I/O pad; and a first surge protecting device, comprising a first terminal coupled to the first output stage circuit and the first I/O pad, and comprising a second terminal coupled to the second output stage circuit and the second I/O pad.

Abstract: According to one embodiment, a thin-film transistor comprises an oxide semiconductor layer formed on a part of a substrate, a first gate insulator film of a silicon dioxide film formed on the oxide semiconductor layer and by the CVD method with a silane-based source gas, a second gate insulator film of a silicon dioxide film formed on the first gate insulator film by the CVD method with a TEOS source gas, and a gate electrode formed on the second gate insulator film.

Abstract: A circuit may include a first sample node configured to provide a low precision sample of an input signal, a second sample node configured to store a high precision sample of an input signal, and a first switch circuit coupled between an input and the first sample node. The circuit may further include a second switch circuit coupled between the first sample node and the second sample node and configured to limit leakage current that could discharge the second sample node.

Abstract: In accordance with an embodiment, an integrated circuit has a first transistor made of a plurality of first transistor segments disposed in a well area, and a second transistor made of at least one second transistor segment. Drain regions of the plurality of first transistor segments and the at least one second transistor segment are coupled to a common output node. The at least one second transistor segment is disposed in the well area such that an electrostatic discharge pulse applied to a common output node homogenously triggers parasitic bipolar devices coupled to each drain region of the plurality of first transistor segments and the drain region of the at least one second transistor segment.

Abstract: A signal transmission method suitable for DDR for driving a connecting pad includes a level shifting circuit including up and down level shifters, a buffer circuit including up and down buffer units, and an output circuit. The level shifting circuit, disposed between a DDR operating voltage and a ground voltage, receives an input signal in a first operating voltage equal to the ground voltage and a second operating voltage smaller than the DDR operating voltage. The up buffer unit is disposed between the DDR operating voltage and a first reference voltage, and the down buffer unit is disposed between the ground voltage and a second reference voltage equal to the second operating voltage. The up and down level shifters adopt IO devices, and other components adopt core devices. The first reference voltage is a difference between the DDR operating voltage and the second reference voltage.

Abstract: An electrostatic discharge (ESD) protection integrated circuit (IC) includes a substrate having a semiconductor surface, a high power supply rail (VDD) and a low power supply rail (VSS) on the semiconductor surface. A trigger circuit including at least one trigger input and at least one trigger output is coupled between VDD and VSS. An active shunt including at least a large MOSFET is coupled between VDD and VSS. The trigger output is coupled to a gate electrode of the large MOSFET, and at least one diode or diode connected transistor (blocking diode) is coupled between VDD and the trigger circuit, within the trigger circuit or between the trigger output and gate electrode.

Abstract: A display substrate and a method of manufacturing the same. The display substrate includes a substrate including an active area and an inactive area, an organic light-emitting diode (OLED) unit disposed on the active area of the substrate, and a transmittance measurement pattern unit disposed on the inactive area of the substrate. The transmittance measurement pattern unit includes a deposition assistant layer pattern disposed on the substrate.

Abstract: An electrostatic discharge protection structure includes a first well, a second well disposed in the first well, a first and a second doped region disposed in the first well, a third and a fourth doped region disposed in the second well, a first electrode electrically connected to the first doped region and the second doped region, and a second electrode electrically connected to the fourth doped region.

Abstract: A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.

Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).