Abstract: A discharge unit is connected to a power pad, a ground pad, and an I/O pad, and can discharge an electrostatic charge when an electrostatic pulse appears on any of the power pad, the ground pad, and the I/O pad. The discharge unit includes a first discharge unit and a second discharge unit, the first discharge unit is connected to the second discharge unit, the power pad, and the I/O pad, and the second discharge unit is connected to the ground pad and the I/O pad. The first discharge unit and/or the second discharge unit can discharge electrostatic charges on different pads, respectively.

Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.

Abstract: The invention provides a chip structure of a micro light-emitting diode display, comprising a package substrate, at least one light-emitting diode (LED) element, at least one metal oxide semiconductor field effect transistor (MOSFET), and a connection line. The LED element and the MOSFET are positioned on the package substrate, and each MOSFET comprises a source connected with the input voltage in common, a gate connected with a main control circuit, and a drain. An end of the LED element is connected with the drain of the MOSFET through the connection line, and the other end of the LED element is independently connected with a source drive circuit. Therefore, the MOSFET is provided on the package substrate and integrated in a chip structure, so as to achieve a better heat dissipation effect and requirements of high density and brightness.

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

Abstract: A transient voltage suppression device includes a P-type semiconductor layer, a first N-type well, a first N-type heavily-doped area, a first P-type heavily-doped area, a second P-type heavily-doped area, and a second N-type heavily-doped area. The first N-type well and the second N-type heavily-doped area are formed in the layer. The first P-type heavily-doped area is formed in the first N-type well. The first P-type heavily-doped area is spaced from the bottom of the first N-type well. The second P-type heavily-doped area is formed within the first N-type well and spaced from the sidewall of the first N-type well. The second P-type heavily-doped area is formed between the first P-type heavily-doped area and the second N-type heavily-doped area.

Abstract: A circuit for a circuit interrupter is provided. The circuit may in include a first SCR configured to receive a first trigger signal at a gate of the first SCR, a second SCR configured to receive a second trigger signal at a gate of the second SCR, and a third SCR configured to receive a third trigger signal at a gate of the third SCR. A cathode of the first SCR may be connected to an anode of the third SCR. A cathode of the second SCR and a cathode of the third SCR may be connected to a ground. Methods of operating a circuit interrupter and a circuit are also provided.

Abstract: A semiconductor integrated circuit includes a high-potential-side circuit region, a high-voltage junction termination structure surrounding the high-potential-side circuit region, and a low-potential-side circuit region surrounding the high-potential-side circuit region via the high-voltage junction termination structure which are integrated into a single chip, and wherein a first distance between a looped well region and a buried layer in a region in which a first contact region is formed is smaller than a second distance between the looped well region and the buried layer in a region in which a carrier reception region is formed.

Abstract: The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

Abstract: An electrostatic discharge, ESD, protection structure (200) formed within a semiconductor substrate of an integrated circuit device (600). The integrated circuit device (600) comprising: a radio frequency domain (632); a digital domain (610). The ESD protection structure (200) further includes an intermediate domain located between the radio frequency domain (632) and the digital domain (610) that comprises at least one radio frequency, RF, passive or active device that exhibits an impedance characteristic that increases as a frequency of operation increases.

Abstract: A semiconductor chip having a pad, a protective element, and an internal circuit for providing a semiconductor chip having a protective circuit with high noise resistance, wherein the semiconductor chip is characterized in that the resistance value of metal wiring on a path reaching the pad and the protective element is higher than the resistance value of the protective element.

Abstract: Various embodiments of a photonic integrated circuit (PIC) are described herein. A PIC, functioning as a coherent receiver, may include optical components such as an optical coupler, a directional coupler, a beam splitter, a polarizing beam rotator-splitter, a variable optical attenuator, a monitor photodiode, 90-degree hybrid mixer, and a waveguide photodiode. The PIC may also include electrical components such as an electrode, a capacitor, a resistor and a Zener diode.

Abstract: Provided are a display panel, a driving method, and a display device. The display panel comprises: pixel circuits arranged in rows and columns in a display area which comprises first and second display areas along a row direction, and an outer edge of the second display area extending stepwise along a column direction; data lines one-to-one corresponding to columns of the pixel circuit; signal line groups one-to-one corresponding to rows of the pixel circuits, each signal line group comprising a scan line and a light-emitting control signal line; and first electrostatic protection circuits one-to-one corresponding to data lines in the second display area, each first electrostatic protection circuit being connected to a scan line and a light-emitting control signal line in the same signal line group, for discharging static electricity on the data line to the scan line or the light-emitting control signal line.

Abstract: A semiconductor device that can have both noise resistance and ESD resistance is provided. The semiconductor device includes a first and a second digital circuits, a first and a second ground potential lines respectively provided corresponding to the first and the second digital circuits, a first and a second analog circuits, a third and a fourth ground potential lines respectively provided corresponding to the first and the second analog circuits, a first bidirectional diode group provided between the first and the second ground potential lines, a second bidirectional diode group provided between the third and the fourth ground potential lines, and a third bidirectional diode group provided between the first and the third ground potential lines. The number of stages of bidirectional diodes of the third bidirectional diode group is greater than that included in each of the first and the second bidirectional diode groups.

Abstract: The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails.

Abstract: A p+ collector layer is provided in a rear surface of a semiconductor substrate which will be an n? drift layer and an n+ field stop layer is provided in a region which is deeper than the p+ collector layer formed on the rear surface side. A front surface element structure is formed on the front surface of the semiconductor substrate and then protons are radiated to the rear surface of the semiconductor substrate at an acceleration voltage corresponding to the depth at which the n+ field stop layer is formed. A first annealing process is performed at an annealing temperature corresponding to the proton irradiation to change the protons into donors, thereby forming a field stop layer. Then, annealing is performed using annealing conditions suitable for the conditions of a plurality of proton irradiation processes to recover each crystal defect formed by each proton irradiation process.

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes an active region defined by an isolation layer. A source region portion, a drain region portion and a channel region are located in the active region. The channel region includes a first portion located close to the source region portion and a second portion having a higher threshold voltage than the first portion.

Abstract: The present disclosure relates to a semiconductor device with an ESD protection structure. The semiconductor device includes a high-voltage power device 101, the ESD protection structure is a NMOS transistor 102, a drain of the NMOS transistor is shared by a source of the power device as a common-drain-source structure 107, substrate leading-out regions of the power device 101 and the NMOS transistor are coupled to the source 106 of the NMOS transistor as a ground leading-out. In the present disclosure, the drain of the NMOS transistor is shared by the source of the power device, so the increased area of the device with the ESD protection structure incorporated is small. In addition, the holding voltage at the source of the high-voltage power device is relatively low, which helps to protect the gate oxide and improve the source reliability.

Abstract: An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

Abstract: According to an embodiment, a transient voltage protection circuit includes a first integrated circuit including an input node, an output node, a first transient voltage protection component coupled between the input node and a reference voltage node, and an impedance element coupled between the input node and the output node. The first transient voltage protection component has a first dynamic resistance and the output node is configured to be coupled to an electrostatic discharge (ESD) protection component having a second dynamic resistance that is greater than the first dynamic resistance.

Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, a first conductive layer, a second conductive layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The first conductive layer is sandwiched between the source electrode and the semiconductor layer. The second conductive layer is sandwiched between the drain electrode and the semiconductor layer. The gate electrode is insulated from the source electrode, the drain electrode, the first conductive layer, the second conductive layer, and the semiconductor layer by the insulating layer. A first work-function of a first material of the first conductive layer and the second conductive layer is same as a second work-function of a second material of the semiconductor layer.

Abstract: A semiconductor device includes a drift zone in a semiconductor body. A charge-carrier transfer region forms a pn junction with the drift zone in the semiconductor body. A control structure electrically connects a recombination region to the drift zone during a desaturation cycle and disconnects the recombination region from the drift zone outside the desaturation cycle. During the desaturation cycle the recombination region reduces a charge carrier plasma in the drift zone and reduces reverse recovery losses without adversely affecting blocking characteristics.

Abstract: A bipolar ESD protection device includes a substrate having a p-type epi layer thereon including an epi region over an n-buried layer (NBL). An n-type isolation tank (iso tank) includes a deep n+ region and NBL for containing an isolated epi region of the epi region. An NPN transistor and an avalanche diode are formed in the isolated epi region. The NPN transistor includes an emitter within a base having a base contact and the collector is a top portion of NBL. The avalanche diode includes a p-type anode region including an anode contact and an n-type cathode region having a cathode contact. The anode region and base are resistively coupled through the epi region. A ground connection couples the emitter to the anode contact and a strike node connection couples the cathode contact to an n+ isolation contact.

Abstract: An ESD transistor and an ESD protection circuit thereof are provided. An ESD transistor includes a collector region disposed on a surface of a substrate, a sink region disposed vertically below the collector region, and a buried layer protruding horizontally further than the sink region under the sink region.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. A first III-V compound layer is disposed over the silicon substrate. A second III-V compound layer is disposed over the first III-V compound layer. The semiconductor device includes a transistor disposed over the first III-V compound layer and partially in the second III-V compound layer. The semiconductor device includes a diode disposed in the silicon substrate. The semiconductor device includes a via coupled to the diode and extending through at least the first III-V compound layer. The via is electrically coupled to the transistor or disposed adjacent to the transistor.

Abstract: In a semiconductor device having a vertical semiconductor element configured to pass an electric current between an upper electrode and a lower electrode, a field stop layer includes a phosphorus/arsenic layer doped with phosphorus or arsenic and a proton layer doped with proton. The phosphorus/arsenic layer is formed from a back side of a semiconductor substrate to a predetermined depth. The proton layer is deeper than the phosphorus/arsenic layer. An impurity concentration of the proton layer peaks inside the phosphorus/arsenic layer and gradually, continuously decreases at a depth greater than the phosphorus/arsenic layer.

Abstract: A semiconductor device includes a semiconductor region, a first active region in the semiconductor region, a second active region in the semiconductor region, and a conductive gate disposed above the first active region and the second active region. A first contact of the conductive gate is configured to couple to a first node of a circuit associated with the semiconductor device. Moreover, a second contact of the conductive gate is configured to couple to a second node of a circuit associated with the semiconductor device. A resistive device is defined between the first contact and the second contact.

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes a bigFET configured to conduct an ESD pulse during an ESD event. The bigFET includes a backgate terminal, a source terminal, and a current distributor connected to the backgate terminal and the source terminal and configured to homogeneously activate a parasitic bipolar junction transistor of the bigFET in response to a current that is generated in the bigFET during the ESD pulse. Other embodiments are also described.

Abstract: A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region.

Abstract: A semiconductor device is disclosed with a protection device formed of a parasitic bipolar transistor, a parasitic diode and a parasitic resistance and operated at a lowered operating voltage to be capable of improving a blocking capability against an over voltage. The impurity concentration in a semiconductor layer as the base of a parasitic bipolar transistor is lower compared with the impurity concentration of a semiconductor layer of the same conduction type arranged adjacently to the semiconductor layer as the base and to be the anode of a parasitic diode. The lowered impurity concentration is determined to be the concentration for making the parasitic bipolar transistor have a snapback phenomenon occur.

Abstract: A device includes a High-Voltage N-Well (HVNW) region have a first edge, and a High-Voltage P-Well (HVPW) region having a second edge adjoining the first edge. A first Shallow N-well (SHN) region is disposed over a lower portion of the HVNW region, wherein the first SHN region is spaced apart from the first edge by an upper part of the HVNW region. A second SHN region is disposed over a lower portion of the HVPW region, wherein the second SHN region is laterally spaced apart from the second edge. A Shallow P-well (SHP) region is disposed over the lower portion of the HVPW region, and is between the first SHN region and the second SHN region. The SHP region has a p-type impurity concentration higher than a p-type impurity concentration of the HVPW region. An isolation region is disposed over and contacting the SHP region.

Abstract: A semiconductor component includes a semiconductor substrate, and a doped well having a well terminal and a transistor structure having at least one potential terminal formed in the semiconductor substrate. The transistor structure has a parasitic thyristor, and is at least partly arranged in the doped well. The potential terminal and the well terminal are connected via a resistor.

Abstract: Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.

Abstract: In an aspect of the present invention, an ESD (Electrostatic Discharge) protection element includes a bipolar transistor comprising a collector diffusion layer connected with a first terminal and an emitter diffusion layer; and current control resistances provided for a plurality of current paths from a second terminal to the collector diffusion layer through the emitter diffusion layer, respectively. The bipolar transistor further includes a base diffusion region connected with the second terminal through a first resistance which is different from the current control resistances.

Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.

Abstract: A resistor-equipped transistor includes a package that provides an external collector connection node (114, 134), an external emitter connection node (120, 140) and an external base connection node (106, 126). The package contains a substrate upon which a transistor (102, 122), first and second resistors, and first and second diodes are formed. The transistor has an internal collector (118, 138), an internal emitter (120, 140) and an internal base (116, 136) with the first resistor (104, 124) being electrically connected between the internal base and the external base connection node and the second resistor (108, 128) being electrically connected between the internal base and the internal emitter.

Abstract: The present invention discloses a high-voltage ESD protection device including a silicon controlled rectifier and a first PNP transistor. The silicon controlled rectifier includes a high-voltage P-well and N-well; a first N+ and P+ diffusion region are formed in the high-voltage P-well; a second N+ and P+ diffusion region are formed in the high-voltage N-well. The first PNP transistor comprises an N-type buried layer; a low-voltage N-well formed in the N-type buried layer; and a base, emitter and collector formed in the low-voltage N-well. The base and emitter are shorted together; the collector is shorted to the second N+ diffusion region and the second P+ diffusion region; the first N+ diffusion region is shorted to the first P+ diffusion region to act as a ground terminal. The high-voltage ESD protection device can effectively adjust the ESD trigger voltage and improve the snapback sustaining voltage after the device is switched on.

Abstract: A semiconductor device includes an n-type drift layer formed on a main surface of a semiconductor substrate, a plurality of p-type well regions formed selectively in an upper layer portion of the drift layer, an n-type source region formed in a surface of the p-type well region, and a p-type contact region which is shallower than the source region formed in the surface of the p-type well region adjacent to the source region. Moreover, the semiconductor device includes an n-type additional region formed in contact with a bottom surface of the p-type well region in a position corresponding to below the contact region and deeper than the p-type well region.

Abstract: A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate.

Abstract: A structure comprises an N+ region formed over a substrate, a P+ region formed over the substrate, wherein the P+ region and the N+ region form a diode and a first epitaxial growth block region formed between the N+ region and the P+ region.

Abstract: In a method for producing an electronic component, a substrate is doped by introducing doping atoms. In the doped substrate, at least one connection region of the electronic component is formed by doping with doping atoms. Furthermore, at least one additional doped region is formed at least below the at least one connection region by doping with doping atoms. Furthermore, at least one well region is formed in the substrate by doping with doping atoms in such a way that the well region doping is blocked at least below the at least one additional doped region.

Abstract: The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.

Abstract: An integrated circuit comprising electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to an external terminal of the integrated circuit. The ESD protection circuitry comprises: a thyristor circuit comprising a first bipolar switching device operably coupled to the external terminal and a second bipolar switching device operably coupled to another external terminal, a collector of the first bipolar switching device being coupled to a base of the second bipolar switching device and a base of the first bipolar switching device being coupled to a collector of the second bipolar switching device. A third bipolar switching device is also provided and operably coupled to the thyristor circuit and has a threshold voltage for triggering the thyristor circuit, the threshold voltage being independently configurable of the thyristor circuit.

Abstract: Bi-directional blocking voltage protection devices and methods of forming the same are disclosed. In one embodiment, a protection device includes an n-well and first and second p-wells disposed on opposite sides of the n-well. The first p-well includes a first P+ region and a first N+ region and the second p-well includes a second P+ region and second N+ region. The device further includes a third P+ region disposed along a boundary of the n-well and the first p-well and a fourth P+ region disposed along a boundary of the n-well and the second p-well. A first gate is disposed between the first N+ region and the third P+ region and a second gate is disposed between the second N+ region and the fourth P+ region. The device provides bi-directional blocking voltage protection during high energy stress events, including in applications operating at very low to medium swing voltages.

Abstract: An apparatus is provided. In the apparatus, there is comprises a substrate with a first region of a first conductivity type, a second region of a second conductivity type that is substantially surrounded by the first region, and a third region of the second conductivity type that is substantially surrounded by the second region. A first dielectric layer is formed over the substrate, and a first conductive layer is formed over the first dielectric layer, which is configured to form a first electrode of a capacitor. A second dielectric layer is formed over the first conductive layer. A plate is formed over the second dielectric layer so as to form a second electrode of the capacitor. A cap is formed over the second dielectric layer, being spaced apart from the plate. A via is electrically coupled to the cap and the third region, extending through the first and second dielectric layers.

Abstract: An electrostatic discharge (ESD) device includes a substrate, an external well of a first conductivity type in the substrate, and an internal well of a second conductivity type in the external well, the first conductivity type opposite the second conductivity type. The ESD device further includes a first heavily doped region of the first conductivity type located at a surface of the internal well, a second heavily doped region of the second conductivity type located at a surface of the internal well, and a third heavily doped region of the first conductivity type located at a surface of the external well. The second heavily doped region is interposed between and spaced from each of the first and third heavily doped regions, and at least one of a space between the first and second heavily doped regions and a space between the second and third heavily doped regions is devoid of a device isolation structure of electrical isolation material.

Abstract: An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type.

Abstract: A semiconductor body includes a protective structure. The protective structure (10) includes a first and a second region (11, 12) which have a first conductivity type and a third region (13) that has a second conductivity type. The second conductivity type is opposite the first conductivity type. The first and the second region (11, 12) are arranged spaced apart in the third region (13), so that a current flow from the first region (11) to the second region (12) is made possible for the limiting of a voltage difference between the first and the second region (11, 12). The protective structure includes an insulator (14) that is arranged on the semiconductor body (9) and an electrode (16) that is constructed with floating potential and is arranged on the insulator (14).

Abstract: A semiconductor device includes an output port that has a first lateral double diffused metal oxide semiconductor (LDMOS) device and an electrostatic discharge protection device that has a second LDMOS device and a bipolar transistor and that protects the output port from electrostatic discharge. A breakdown voltage of the second LDMOS device is equal to or lower than a breakdown voltage of the first LDMOS device.

Abstract: A punch-through diode and method of fabricating the same are disclosed herein. The punch-through diode may be used as a steering element in a memory device having a reversible resistivity-switching element. For example, a memory cell may include a reversible resistivity-switching element in series with a punch-through diode. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. In other words, the ratio of Ion/Ioff is high. Therefore, the punch-through diode is compatible with bipolar switching in cross-point memory arrays having resistive switching elements.