Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximate the edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region. P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.

Abstract: A method and apparatus for preventing thermo-mechanical damage to an electrostatic discharge (ESD) protection device is disclosed. The method and apparatus of the invention focus on preventing ESD protection circuit failure due to elastic waves within the materials of an integrated circuit. The elastic waves are specifically caused by very fast ESD discharge events. Disclosed are ESD protection circuits incorporating materials with superior thermo-mechanical properties, in particular, material damping, melting temperature, material stiffness, elastic modulus, tensile strength and fracture toughness. Also disclosed is the use of thermo-mechanical energy absorber material that is designed to protect ESD devices from failure due to slower ESD events.

Abstract: A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of ?2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.

Abstract: The present invention relates to a packaging mold with electrostatic discharge protection, comprising at least one recess for receiving at least one packaging substrate, the packaging substrate comprising an outer wall with a first height, the recess comprising an inner wall with a second height and the inner wall electrically connecting the outer wall of the packaging substrate, wherein the second height is larger than the first height. When separating the packaging substrate and the packaging mold, the duration of the outer wall connecting to the inner wall is extended, so that static electric charges generated when separating are conducted via the packaging mold preventing the dice to be packaged from damage due to electrostatic discharge to raise the yield rate of semiconductor package products thereby.

Abstract: In a BSCR and method of making a BSCR, a npn BJT structure is created and a p+ region is provided that is connected to the collector of the BJT, and one or more of the NBL, sinker and n+ collector of the BJT are partially blocked. In this way the NBL is formed into a comb-like NBL with a plurality of tines in one embodiment. The sinker and n+ collector may also be formed into a plurality islands. Furthermore, the period of the tines and islands may be varied to provide the desired BSCR characteristics.

Abstract: An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a result, an input impedance higher than the input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.

Abstract: A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and both having a depletion region when reverse biased. The shallow regions are surrounded in part by an enhanced p-doping implant pocket. The transistor further has in these regions of enhanced p-doping another region of a p-resistivity higher than the remainder of the semiconductor. These regions extend laterally approximately from the inner border of the respective shallow region to the inner border of the respective recessed region, and vertically from a depth just below the depletion regions of source and drain to approximately the top of the channel stop regions.

Abstract: An electrostatic discharge device may provide better protection of an integrated circuit by more uniform breakdown of a plurality of finger regions. The plurality of finger regions may extend through a first region of a substrate having a first conductivity type and into a second region of the substrate more lightly doped with impurities of the first conductivity type. An electrostatic discharge device may include a collector region having a middle region that may be highly doped with impurities of the first conductivity type. The middle region may be proximate to a layer that is lightly doped with impurities of the first conductivity type and a layer that is doped with impurities of the second conductivity type. The collector region may decrease the breakdown voltage of the electrostatic discharge device.

Abstract: A multi-finger type electrostatic discharge protection circuit is disclosed. In an NMOS type ESD protection circuit, a pair of gates are formed in parallel with each other in one of multiple active regions so as to enable all the gate fingers in the active regions to perform npn bipolar operations uniformly. The present invention discharges an ESD pulse effectively by forming one or more additional n+ (or p+) type active regions, which are connected to Vcc (or Vss), between respective active regions.

Abstract: The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I/O cell libraries. The ESD device according to the present invention uses a novel I/O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and/or varying channel lengths in the layout structure.

Abstract: An ESD protection device (20) comprises an N-type epitaxial collector (21), a first, lightly doped, deep base region (221) and second, highly doped, shallow base region (222) that extends a predetermined lateral dimension. The device responds to an ESD event by effecting vertical breakdown between the base regions and the N-type epitaxial collector. The ESD response is controlled by the predetermined lateral dimension, S, which, in one embodiment, may be is determined by a single masking step. Consequently, operation of the ESD protection device is rendered relatively insensitive to the tolerances of a fabrication process, and to variations between processes.

Abstract: The invention provides an ESD protection circuit compatible with the high voltage device manufacturing processes by using parasitic bipolar junction transistor punch characteristics. The design of the present invention takes advantage of bipolar punch characteristics of the parasitic NPN or PNP bipolar structure to bypass the ESD current, thus significantly increasing the ESD level. In addition, the ESD protection circuit of the present invention can greatly reduce the ESD cell areas by eliminating certain prior art diode structure.

Abstract: The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.

Abstract: A semiconductor device has a surge protection circuit electrically connected to a signal input terminal and including a diode and a transistor. The diode has its cathode region constituted of an n+ diffusion layer, an n− epitaxial layer, an n-type diffusion layer and an n+ diffusion layer. The n+ diffusion layer is electrically connected to a conductive layer and formed at a main surface of a semiconductor substrate. The n+ diffusion layer constitutes, together with a p-type diffusion layer, a pn junction where Zener breakdown occurs, and the pn junction with the Zener breakdown occurring therein is distant from a field oxide film. Then, the semiconductor device with the surge protection circuit without suffering from current leakage and thus normally operating can be achieved.

Abstract: The protecting element includes an NPN transistor having an emitter connected to an input/output terminal and a collector and a base connected to a ground terminal. The input/output terminal has the possibility of receiving a surge voltage. The input/output terminal, which may be referred to as a pad, is connected to a semiconductor integrated circuit IC to be protected against the surge voltage. The arrangement of the semiconductor integrated circuit IC is not limited to a specific one.

Abstract: An ESD protection structure for use with bipolar or BiCMOS ICs that is relatively immune to thermal overheating and, thus, stable during an ESD event. This immunity is achieved by employing a heat sink region adjacent to a polysilicon emitter within a distance of less than 2 microns. Such a heat sink region provides temporal heat capacity to locally dissipate the heat generated during an ESD event. Bipolar transistor-based ESD protection structures according to the present invention include a semiconductor substrate and a bipolar transistor in and on the semiconductor. The bipolar transistor includes a base region, a collection region and a polysilicon emitter. The bipolar transistor-based ESD protection structures also include a heat sink region disposed above the semiconductor substrate adjacent to the polysilicon emitter.

Abstract: A semiconductor integrated circuit device includes an external connection pad, an electrostatic discharge protection circuit, an output circuit, an output pre-buffer circuit, an output-signal-fixing circuit and an internal circuit. The output-signal-fixing circuit includes a first capacitor and a second capacitor and fixes an output signal from a second pre-buffer circuit at an “L” level (low voltage) even when an output from the internal circuit is in a floating state. During an ESD test, since an output signal from the second pre-buffer circuit is fixed at an “L” level (low voltage) by the output-signal-fixing circuit, the NMIS transistor is in an OFF state. In this manner, a surge current is prevented from flowing locally into the NMIS transistor.

Abstract: An electrostatic discharge (ESD) protection device having a silicon controlled rectifier (SCR) for protecting circuitry of an integrated circuit (IC). The SCR includes a N-doped layer disposed over a substrate and a first P doped region disposed over the N-doped layer. At least one first N+ doped region forming a cathode is disposed over the P-doped region and coupled to ground. The at least one first N+ doped region, first P-doped region, and N-doped layer form a vertical NPN transistor of the SCR. A second P doped region forming an anode is coupled to a protected pad. The second P doped region is disposed over the N-doped layer, and is laterally positioned and electrically isolated with respect to the first P doped region. The second P doped region, N-doped layer, and first P doped region form a lateral PNP transistor of the SCR.

Abstract: An ESD protection device is provided for an integrated circuit. The ESD protection device includes a power supply clamp device formed from a diode and coupled between a first power supply VCC and a second power supply VSS. An input protection device is also provided which is formed from a diode coupled between an input pad and the first power supply and a second diode coupled between the input pad and a second power supply. The diodes have an adjusted reverse breakdown voltage that is higher than the voltage supply VCC used to power the peripheral circuitry that drives circuitry within a core of the integrated circuit. The adjusted reverse breakdown voltage is also lower than the breakdown voltage of gate oxide layers used within the peripheral circuitry.

Abstract: The protecting element includes an NPN transistor having an emitter connected to an input/output terminal and a collector and a base connected to a ground terminal. The input/output terminal has the possibility of receiving a surge voltage. The input/output terminal, which may be referred to as a pad, is connected to a semiconductor integrated circuit IC to be protected against the surge voltage. The arrangement of the semiconductor integrated circuit IC is not limited to a specific one.

Abstract: A protection circuit including a power supply terminal supplied with a power supply potential, a reference terminal supplied with a reference potential, and a first p-channel MOS transistor having a first gate, a first source, a first drain and a first back gate. The first gate, the first source and the first back gate are connected to the power supply terminal. Also included is a second p-channel MOS transistor having a second gate, a second source, a second drain and the first back gate, in which the second source of the second p-channel MOS transistor is connected to the first drain of the first p-channel MOS transistor, and the second gate and the second drain of the second p-channel MOS transistor is connected to the reference terminal.

Abstract: A structure of protection of an area of a semiconductor wafer including a lightly-doped substrate of a first conductivity type against high-frequency noise likely to be injected from components formed in the upper portion of a second area of the wafer. The structure includes a very heavily-doped wall of the first conductivity type having substantially the depth of the upper portion. The wall is divided into segments, each of which is connected to a ground plane.

Abstract: An arrangement (200) and method for scalable ESD protection of a semiconductor structure (140), a protection structure (120) providing a discharge transistor (110) path from an input/output node (130) to ground or another node if a threshold voltage is reached, wherein the discharge transistor is a self-triggered transistor having collector/drain (220) and emitter/source (210) regions, and a base/bulk region (260) having one or more floating regions (240) between the collector/drain (220) and emitter/source (210) regions. The floating region (N or P) modulates the threshold voltage Vt1 for ESD protection. Vt1 can be adjusted by shifting the floating region location. Splitting of the electric field into two parts reduces the maximum of the electric field. Vt1 can be adjusted volt-by-volt to suit application needs. ESD capability is increased by better current distribution in the silicon. This provides the advantages of reduced die size, faster time-to-market, less redesign cost, and better ESD performance.

Abstract: A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates an SCR device with all SCR elements essentially contained within the same active area without STI elements being interposed between the device anode and cathode elements. This enhances ESD performance by eliminating thermal degradation effects caused by interposing STI structures, and enhances the parasitic bipolar characteristics essential to ESD event turn on. Enabling this unique design is the use of an insulation oxide surface feature which prevents the formation of contact salicides in unwanted areas. This design is especially suited to silicon-on-insulator design, as well as conventional SCR and LVTSCR designs.

Abstract: A vertical bipolar transistor having low breakdown voltage, low ESD clamping voltage and high beta is fabricated in a semiconductor 301 of a first conductivity type, which has a buried layer 360 of the opposite conductivity type with sharp junctions, suitable as collector. This layer extends laterally to deep wells 371 of the opposite conductivity type, thus isolating the subsurface band 301a of the semiconductor of the first conductivity type. This band is suitable as the base and has a width 301c controlled by the proximity of the buried layer junction 360a. The emitter 310 is supplied by a surface region of the opposite conductivity type. The photomask, which is needed for implanting the low energy ions to create the extended emitter, is also used for the process step of implanting, at high energy and high dose, the ions needed (opposite conductivity type) to create the buried layer.

Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.

Abstract: In a Bi-CM0S ESD protection structure, the holding voltage is increased by a desired amount by including a NBL of chosen length. The positioning of the NBL may be adjusted to adjust the I-V characteristics of the structure. Dual voltage capabilities may be achieved by providing two laterally spaced p-regions in a n-material and defining a n+ region and a p+ region in each of the p-regions to define I-V characteristics that are similar to those defined by a SCR device in a positive direction, but, in this case, having those characteristics in both directions. Over and above the NBL position being adjusted relative to the p-regions, the two p-regions may vary in doping level, and dimensions to achieve different I-V characteristics for the device in the positive and negative directions.

Abstract: An ESD guard structure includes a self-aligned lateral p+/n+ diode serving as the trigger diode. This lateral trigger diode is largely independent of alignment precisions. The n+ and p+ regions are implanted on opposite sides of a gate electrode. The edges of the resist masks of the respective process diffusions are placed onto this gate electrode such that they always rest on the gate electrode, within the limits of the alignment capabilities. This way, the spacing between the n+ region and the p+ region is defined solely by the length or width of the gate electrode, which can be closely controlled. This technique is limited only by the requirement that the minimum gate electrode length must be no less than twice the maximum alignment precision.

Abstract: An N well is formed in a surface of a P+ substrate and a P well is formed in such a way as to surround the N well. Then, a trigger tap (P+ diffusion region) is formed in the surface of the P well and two cathodes (N+ diffusion regions) are formed in such a way as to hold the trigger tap. Then, an anode (P+ diffusion region) is formed in the surface of the N well in a position facing the trigger tap and the cathode, and an N well pick-up diffusion (N+ diffusion region) is formed in such a way as to surround that side edge of the anode which does not face the cathode. Accordingly, the resistance between the end portion of the anode and the N well pick-up diffusion (N+ diffusion region) becomes lower than the resistance between the center portion of the anode and the N well pick-up diffusion.

Abstract: An ESD protection device for an integrated circuit, which is integrated in a semiconductor substrate of the integrated circuit, has a heavily doped p-region provided with a first connection electrode, a heavily doped n-region provided with a second connection electrode, a lightly doped p-region bordering on the heavily doped p-region, and a lightly doped n-region bordering on the heavily doped n-region and the lightly doped p-region in such a way that the lightly doped regions are arranged at least between the heavily doped regions. The distance which exists between the lightly doped p-region and the heavily doped n-region and which is determined by the lightly doped n-region is dimensioned in such a way that the depletion zone in the lightly doped n-region, which becomes larger as the blocking voltage applied to the connection electrodes increases, reaches the heavily doped n-region before the breakthrough voltage between the lightly doped n-region and the lightly doped p-region has been reached.

Abstract: An IGBT is formed in a thin (less than 250 microns thick) float zone silicon wafer using a hydrogen implant to form an N+ buffer layer at the bottom of the wafer. A weak anode is formed on the bottom of the wafer. A single hydrogen implant, or a plurality of hydrogen implants of progressively shallower depth and increasing dose can be used to form the implant in a diffused float zone wafer. The process may also be used to form an N+ contact region in silicon to permit a good ohmic contact to the silicon for any type device.

Abstract: Electrostatic discharge protection device comprising a first highly p-doped region with a base contact, a first highly n-doped region with a collector contact, a second highly n-doped region with an emitter contact and located between the first highly p-doped region and the second highly n-doped region, the first highly p-doped region and the second highly n-doped region being applied in a weakly p-doped region which a has a lateral overlap extending towards the first highly n-doped region, the lateral overlap having a width, the first highly n-doped region being applied in a weakly n-doped region, the weakly p-doped region and the weakly n-doped region being applied in a more weakly n-doped region, and a highly n-doped buried layer located underneath the more weakly n-doped region and extending below at least a portion of the weakly n-doped region and at least a portion of the weakly p-doped region.

Abstract: A diode-triggered NPN ESD protection device includes a P-Base region enclosing the emitter region of the NPN transistor for enhancing the reliability of the ESD protection device. The incorporation of the P-Base region encourages bulk transistor action and inhibits surface transistor action such that the reliability of the protection device is enhanced. In another aspect of the present invention, a trigger voltage control method is applied to a diode-triggered ESD protection device to extend the periphery length of the p-n junction of the trigger diode without increasing the size of the protection device. By extending the periphery length of the p-n junction, the trigger current generated by the trigger diode is increased so that the trigger voltage for the ESD protection device can be lowered, providing effective ESD protection. The periphery length is extended by using a shaped periphery, such as a corrugated periphery or a perforated periphery.

Abstract: An electrostatic discharge protection device is provided at an input or output of a semiconductor integrated circuit for protecting an internal circuit from an electrostatic surge flowing into or out of the integrated circuit. The electrostatic discharge protection device may include a thyristor, and a trigger diode for triggering the thyristor (e.g., with a low voltage). The trigger diode may include an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the cathode region from another silicide layer formed on a surface of the anode region.

Abstract: A semiconductor device includes a plurality of diodes including a substrate of a first conductivity type biased to a reference potential, a well region of a second conductivity type formed in a surface region of the substrate, and a first diffusion region of the first conductivity type formed in a surface region of the well region, wherein the plurality of diodes have sizes of at least two kinds and are cascade-connected to each other.

Abstract: In an ESD protection device using a SCR-like structure, a vertical device is provided that is highly robust and easily allows the triggering voltage to be adjusted during manufacture. Furthermore it is implementable in complementary form based on PNP and NPN BJT structures, to provide both positive and negative pulse protection.

Abstract: A semiconductor method for reducing charge damage during plasma etch processing is disclosed. Structures (22, 26, 28) for accumulating charge during plasma etch processing are provided on a semiconductor wafer (10), the structures (22, 26, 28) being electrically connected to device structures (30, 32).

Abstract: A diode-triggered NPN ESD protection device includes a P-Base region enclosing the emitter region of the NPN transistor for enhancing the reliability of the ESD protection device. The incorporation of the P-Base region encourages bulk transistor action and inhibits surface transistor action such that the reliability of the protection device is enhanced. In another aspect of the present invention, a trigger voltage control method is applied to a diode-triggered ESD protection device to extend the periphery length of the p-n junction of the trigger diode without increasing the size of the protection device. By extending the periphery length of the p-n junction, the trigger current generated by the trigger diode is increased so that the trigger voltage for the ESD protection device can be lowered, providing effective ESD protection. The periphery length is extended by using a shaped periphery, such as a corrugated periphery or a perforated periphery.

Abstract: A protective circuit for protecting an IGBT from a stress due to application of an overvoltage which is induced by a surge such as static electricity is provided. The protective circuit allows for improvement in a voltage tolerance to a stress due to application of an overvoltage induced by a surge while ensuring a current tolerance to flow of a direct current from an external power supply when the external power supply is improperly connected in a direction contrary to a normal direction. The protective circuit includes a resistor having one end connected to a terminal for connecting to the external power supply and the other end connected to a semiconductor element, and a first zener diode including a cathode connected to the other end of the resistor. The protective circuit further includes a plurality of second zener diodes connected in series between the one end of the resistor and a generator of a constant potential such as a ground.

Abstract: An ESD diode protects a circuit against electrostatic discharge (ESD). The ESD diode has four adjacent regions. The first and third regions are formed by doping a semiconductor substrate so that it has a P-type conductivity. The second and fourth regions are formed by doping the semiconductor substrate so that it has an N-type conductivity. The first region is for connection to a signal terminal of the circuit being protected when the fourth region is connected to a positive power line of the circuit. The fourth region is for connection to the signal terminal when the first region is connected to the ground line or a negative power line of the circuit.

Abstract: A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground.

Abstract: A semiconductor device is provided with an electrostatic protection circuit that causes rapid breakdown of a Zener diode immediately after a static charge is applied, to discharge the static charge by a high-gain thyristor with good response characteristics, and that has a small surface area. When a static charge is applied, a Zener diode breaks down, which acts as a trigger to turn on a thyristor formed of an NPN bipolar transistor and a PNP bipolar transistor. The PNP bipolar transistor is formed of p-type, n-type, and p-type impurity diffusion regions formed in the thickness direction of the substrate and the Zener diode is formed of n-type and p-type impurity diffusion regions. An n-type impurity diffusion region is provided adjacent to a surface-layer p-type impurity diffusion region, and these p-type and n-type impurity diffusion regions are connected to a signal terminal through a silicide layer formed on the surfaces thereof.

Abstract: The invention concerns an integrated circuit, comprising a substrate (SBSTR) with sub-circuits provided with a number of terminals, including a substrate terminal or earthing point (GND), a Vcc power supply terminal, an input point (in) and an output point (out). At least one of the Vcc power supply terminal, the input point or the output point is connected via an overvoltage protection circuit to the substrate terminal or earthing point, wherein the overvoltage protection circuit comprises means with diode action formed in the substrate between the relevant terminal and the substrate terminal or earthing point. The means comprise two or more diode elements of the Zener type connected in series. The substrate of a first conductivity type is provided with a well (WLL) of a second, opposed conductivity type formed in the substrate.

Abstract: A semiconductor device comprises a first base layer for providing a PT-IGBT or IEGT structure, which includes a buffer layer and a collector layer provided in the buffer layer. A first activation rate, defined by an activated first conductivity type impurity density [cm−2] in the buffer layer due to SR analysis/a first conductivity type impurity density [cm−2] in the buffer layer due to SIMS analysis is given by 25% or more, and a second activation rate, defined by an activated second conductivity type impurity density [cm−2] in the collector layer due to SR analysis/a second conductivity type impurity density [cm−2] in the collector layer duet to SIMS analysis is given by more than 0% and 10% or less.

Abstract: A structure of a 2-bit mask ROM device and a fabrication method thereof are provided. The memory structure includes a substrate, a gate structure, a 2-bit coding implantation region, a spacer, a buried drain region, an isolation structure and a word line. The gate structure is disposed on the substrate, while the coding implantation region is located in the substrate under the side of the gate structure. Further, at least one spacer is arranged beside the side of the gate structure and a buried drain region is disposed in the substrate beside the side of the spacer. Moreover, the buried drain region and the coding implantation region further comprise a buffer region in between. Additionally, an insulation structure is arranged on the substrate that is above the buried drain region, while the word lien is disposed on the gate structure.

Abstract: A semiconductor device with substrate-triggered ESD protection technique includes a guard ring, a first MOS transistor array, a second MOS transistor array and a substrate-triggered portion. The first MOS transistor array, the second MOS transistor array and the substrate-triggered portion are formed in a region surrounded by the guard ring, and the substrate-triggered portion is located between the first MOS transistor array and the second MOS transistor array. Therefore, when the ESD event occurs, the substrate-triggered portion can be used for biasing a base of at least one parasitic BJT in the first MOS transistor array and a base of at least one parasitic BJT in the second MOS transistor array to achieve uniform turn-on among the multiple fingers of MOS transistor array. By using this layout design, the MOS transistor array can have a high ESD robustness.

Abstract: A protective circuit for limiting a voltage at a pad of an integrated circuit includes a threshold selector connected between the pad and ground. The input voltage to the threshold selector is the pad voltage. The threshold detector includes a first transistor where load path is connected to the pad. The central terminal of the first transistor is maintained at a threshold voltage derived from the pad voltage. A second transistor has its control terminal connected to a second terminal of the load path of the first transistor. The load path of this second transistor is connected between the pad and ground.

Abstract: An all-mode, bonding pad-oriented ESD (electrostatic discharge) protection structure, protects ICs against ESD pulses of all modes in all directions. A unique quasi-symmetrical layout design is devised to improve ESD structure. Physical symmetry and rounded layout provide uniform current and thermal distribution as well as symmetrical electrical operation characteristics. The ESD structure allows tunable triggering voltage, low holding voltage, low impedance, low leakage, fast response time and low parasitic effect. The ESD structure can easily be placed under or surrounding a bonding pad and consumes little extra silicon. The ESD structure can be implemented in commercial BiCMOS processes and is suitable for multiple-supply, mixed-signal, parasitic-sensitive RF and high-pin-count ICs.

Abstract: An ESD robust bipolar transistor (200) that includes first and second bipolar elements (210, 220), wherein a first trigger voltage of the first bipolar element (210) is proximate a second sustaining voltage of the second bipolar element (220). The first and second bipolar elements (210, 220) include first and second bases (214, 224), emitters (216, 226) and collectors (212, 222), respectively. The first and second bases (214, 224) are coupled and the first and second collectors (212, 222) are coupled. The ESD robust bipolar transistor (200) also includes an emitter resistor (250) and a base resistor (260), wherein the emitter resistor (250) couples the first and second emitters (216, 226) and the base resistor (260) couples the second emitter (226) and the first and second bases (214, 224).

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p− region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm−3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p− layer should be between about 0.5E14 cm−3 and about 1.OE17 cm−3. The junction depth of the fourth (n+) region should be greater than about 0.3 &mgr;m. The thickness of the third (p+) region should be between about 0.3 &mgr;m and about 2.