Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

Abstract: An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. in one embodiment of the present invention, the protection device includes a semiconductor substrate having a first conductivity type. A well region formed with a second conductivity type in the semiconductor substrate. A first region formed in the well region. A second region formed having a portion in the weil region and another portion outside the well region, but still within the semiconductor substrate. Moreover, a third region formed within the well region and in between the first; region and the second region. A fourth region formed within the semiconductor substrate and outside the well region. A fifth region formed within the semiconductor substrate and in between the second region and the fourth region.

Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.

Abstract: An IC package substrate having integral ESD protection features and elements and a method for construction of the same are disclosed

Abstract: A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.

Abstract: A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structure are n-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.

Abstract: Methods and apparatus are provided an electrostatic discharge (ESD) protection device having a first terminal and a second terminal. The ESD protection device comprises a vertical transistor having a collector coupled to the first terminal, a base, and an emitter coupled to the second terminal. A zener diode has a first terminal coupled to the first terminal of the ESD protection device and a second terminal coupled to the base of the vertical transistor. Subsurface current paths are provided to redistribute current from a surface of the vertical transistor in an ESD event. The method comprises generating an ionization current when a zener diode breaks down during an ESD event. The ionization current density from a surface zener diode region is reduced. The ionization current enables a transistor to dissipate the ESD event.

Abstract: A circuit and a method for the electrostatic discharge protection of integrated circuits. The electrostatic discharge protection circuit, including: an electrostatic discharge protection circuit, comprising: a first bipolar transistor coupled between a first circuit node and a second circuit node, the first bipolar transistor having a non-uniform subcollector region geometry, the first bipolar transistor having a different value for collector to emitter breakdown voltage than a value for collector to emitter breakdown voltage of an otherwise identical bipolar transistor having a uniform subcollector region geometry.

Abstract: A DMOSFET and a method of fabricating the same, capable of keeping a desirable level of drain voltage resistance and, at the same time, of reducing the drain resistance. In a DMOSFET configured as having a drain region composed of an epitaxial layer formed on a P-type semiconductor substrate while placing an N-type buried layer in between, and as having, in the drain region, a P-type body region having an N-type source region nested therein and a drain extraction region, formation of N-type, heavily-doped buried layers prior to the epitaxial growth is proceeded so as not to form them at least in the region under the P-type body region, and so as to make an impurity concentration in the region under the P-type body region smaller than that in the region under a drift region when viewed after the impurity is diffused by the succeeding annealing.

Abstract: A diode structure that facilitates tuning the breakdown voltage of the diode structure, and a method for forming and operating the diode structure. In a P? substrate, a N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N? layer is implanted in the substrate. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value.

Abstract: In a triggering ESD protection structure, the triggering voltage is reduced by introducing one or more corners or spikes into the p-n breakdown junction. This may be done by providing a polygate with a zig-zag pattern to define triangular corners in the drain or anode of the structure.

Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.

Abstract: A semiconductor device that permits an increase in static destruction resistance while preventing an increase in the chip size includes a protective element formed by a polysilicon layer in which JFETs are serially connected in three stages and which is inserted between a gate electrode and source electrode of a power-MOSFET or IGBT semiconductor device. The gate insulation film of a semiconductor active element portion of the semiconductor device is protected regardless of whether the polarity of static electricity or another high voltage is positive or negative.

Abstract: There is provided an electrostatic discharge protection device comprising a P conductive type first P well region 101 formed in a P type epitaxial layer 31 being deposited on a surface of a P+ substrate 30 having a prescribed thickness, an N conductive type first N well 101 a periphery thereof being brought into direct contact with and surrounded by a first P well region 101, P conductive type first P diffusion regions 121a and 121b, a P conductive type third P diffusion region 125, and an N conductive type second N diffusion region 223 arranged within a first P well region 101, and a P conductive type second P diffusion region 123 and an N conductive type first N diffusion region 221 arranged within a first N well 201.

Abstract: In one embodiment, a concentric ring ESD structure includes a first p-type region and a second p-type region are formed in a layer of semiconductor material. The two p-type regions are coupled together with a floating n-type buried layer. The first and second p-type regions form a back-to-back diode structure with the floating n-type buried layer. A pair of shorted n-type and p-type contact regions is formed in each of the first and second regions. An isolation region is formed between the first and second p-type regions.

Abstract: Electrostatic discharge (ESD) devices for protection of integrated circuits are described. ESD devices may be configured to provide uniform breakdown of finger regions extending through a first region of a substrate having a first conductivity type and into a second region of the substrate more lightly doped with impurities of the first conductivity type. Such an EDS device may include a collector region having a middle region highly doped with impurities of the first conductivity type. The middle region may be proximate to a layer that is lightly doped with impurities of the first conductivity type and a layer that is doped with impurities of the second conductivity type. The collector region may decrease the breakdown voltage of the EDS device. The lightly doped region may be eliminated in the collector region and an interlayer insulating layer is formed in contact with the top side regions and the middle region.

Abstract: A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of ?2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.

Abstract: A high voltage device for an electrostatic discharge protection circuit is provided. A silicon layer is disposed in a substrate. A first type well and a second type well are disposed in the silicon layer. A lightly doped region of a second type well is located next to the first type well. A heavily doped region of the second type well is located underneath a portion of the first type well and the lightly doped region. A gate structure is disposed over a portion of the first type well and the lightly doped region. A second type first doped region and a second type second doped region are disposed in the lightly doped region and the first type well on each side of the gate structure. An isolation structure is disposed in the lightly doped region. A first type doped region is disposed in the first type well.

Abstract: A method and structure alters an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.

Abstract: A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates an SCR device with all SCR elements essentially contained within the same active area without STI elements being interposed between the device anode and cathode elements. This enhances ESD performance by eliminating thermal degradation effects caused by interposing STI structures, and enhances the parasitic bipolar characteristics essential to ESD event turn on. Enabling this unique design is the use of an insulation oxide surface feature which prevents the formation of contact salicides in unwanted areas. This design is especially suited to silicon-on-insulator design, as well as conventional SCR and LVTSCR designs.

Abstract: A MOS device for an electrostatic discharge protection circuit provided. A gate structure is disposed on the substrate. A source region and a drain region are formed in the substrate beside the gate structure. A doped layer is disposed underneath the source region and the drain region within the substrate but apart from the source region and the drain region. An extended doped region is disposed within the substrate adjacent to the doped layer and the source region. Two parasitic bipolar junction transistors (BJT) are formed in the MOS device. One BJT includes the drain region, the substrate and the source region. Another BJT includes the drain region, the substrate and the doped layer. A discharge current flowing into the drain region is channeled to a common voltage terminal via these two parasitic bipolar junction transistors.

Abstract: A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

Abstract: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.

Abstract: The present invention relates to a monolithic component of protection of a line against overvoltages than a determined positive threshold or smaller than a determined negative threshold, including in antiparallel a cathode-gate thyristor (Th1) and an anode-gate thyristor (Th2), the gate of the cathode-gate thyristor being connected to a negative threshold voltage (?V) via a gate current amplification transistor (T1), the gate of the anode-gate thyristor being connected to a positive threshold voltage (+V). The monolithic component is made in a substrate divided into wells separated by isolating walls (3, 4), the smaller surfaces of which are coated with insulating layers (5, 6), the smaller surface of the substrate being uniformly coated with a metallization (M1).

Abstract: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

Abstract: A monolithically integratable semiconductor structure serves for over-voltage protection in an integrated circuit or as a normal diode. The structure includes an insulating layer between a substrate and a semiconductor layer of first conductivity type, and several layers formed in the semiconductor layer. First and second layers of second conductivity type are spaced apart from one another. A third layer of first conductivity type contacts the second layer. A fourth layer of first conductivity type directly contacts and surrounds the second and third layers. A fifth layer of first conductivity type and higher dopant concentration than the semiconductor layer is disposed under the first layer. The first layer surrounds the second, third and fourth layers essentially in a ring-shape. A first electrode contacts the first layer. A second electrode contacts the second and third layers.

Abstract: An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection structure under the bond pad eliminates parasitic substrate capacitance and utilizes a parasitic PNP transistor formed from the inserted forward biased diode. The ESD-protection structure includes adjacent alternating P+ and N+ diffusions located substantially under a bond pad to be ESD protected. The P+ diffusions are connected to the bond pad metal with metal vias through an insulating layer. The N+ diffusions are adjacent to the P+ diffusions. An N+ diffusion surrounds the N+ and P+ diffusions, and ties together the N+ diffusions so as to form a continuous N+ diffusion completely around each of the P+ diffusions. An N? well is located substantially under the N+ and P+ diffusions.

Abstract: An electrostatic discharge device may provide better protection of an integrated circuit by more uniform breakdown of a plurality of finger regions. The plurality of finger regions may extend through a first region of a substrate having a first conductivity type and into a second region of the substrate more lightly doped with impurities of the first conductivity type. An electrostatic discharge device may include a collector region having a middle region that may be highly doped with impurities of the first conductivity type. The middle region may be proximate to a layer that is lightly doped with impurities of the first conductivity type and a layer that is doped with impurities of the second conductivity type. The collector region may decrease the breakdown voltage of the electrostatic discharge device.

Abstract: An integrated device in emitter-switching configuration is described. The device is integrated in a chip of semiconductor material of a first conductivity type which has a first surface and a second surface opposite to each other. The device comprises a first transistor having a base region, an emitter region and a collector region, a second transistor having a not drivable terminal for collecting charges which is connected with the emitter terminal of the first transistor, a quenching element of the first transistor which discharges current therefrom when the second transistor is turned off. The quenching element comprises at least one Zener diode made in polysilicon which is coupled with the base terminal of the first transistor and with the other not drivable terminal of the second transistor.

Abstract: A described embodiment of the present invention includes an integrated circuit having a plurality of I/O modules. The I/O modules include a bond pad formed on a substrate. The I/O modules also include an electrostatic discharge device formed in the substrate. The electrostatic discharge device is at least partially formed beneath the bond pad. The I/O module also includes an I/O buffer formed in the substrate. The I/O buffer is connected to the bond pad. The I/O buffer provides communication between the bond pad and circuitry formed in the substrate. The circuitry is positioned substantially adjacent to both the electrostatic discharge device and the I/O buffer.

Abstract: Metal oxide semiconductor transistors and devices with such transistors and methods of fabricating such transistors and devices are provided. Such transistors may have a silicon well region having a first surface and having spaced apart source and drain regions therein. A gate insulator is provided on the first surface of the silicon well region and disposed between the source and drain regions and a gate electrode is provided on the gate insulator. A region of insulating material is disposed between a first surface of the drain region and the silicon well region. The region of insulating material extends toward but not to the source region. A source electrode is provided that contacts the source region. A drain electrode contacts the drain region and the region of insulating material.

Abstract: A pMOS transistor (601) is located in an n-well (602) and has at least one gate (603). Transistor (601) is connected between power pad Vdd or I/O pad (604) and ground potential Vss (605). Gate (603) is connected to power pad (604). The n-well (602) is capacitively (620) coupled to ground (605), decoupled from the transistor source (606) and floating under normal operating conditions. Under an ESD event, the diode formed by the source (606) and the n-well (602) is forward biased (n-well negatively biased) to turn on the lateral pnp transistor to discharge the ESD current. The well voltage keeps increasing up to the value that triggers the lateral bipolar pnp transistor. The ESD protection is scalable with the width of gate (603), improving with shrinking gate width.

Abstract: A semiconductor structure including a substrate, a device layer and a contact arranged on the substrate, comprises an ESD protective means, arranged between the substrate and the contact, such, that in the ESD case a breakthrough from the ESD protective means to the contact occurs.

Abstract: A cascaded diode structure with a deep N-well for effectively reducing the leakage current of the P-type substrate by floating the base of a parasitic transistor in the cascaded diode structure. The cascaded diode structure includes a P-type substrate, a deep N-well formed on the P-type substrate, a plurality of elemental diodes formed on the deep N-well, and a plurality of connecting parts for cascading the elemental diodes. Each elemental diode includes a P-well formed on the deep N-well, a heavily doped P-type region formed on the P-well, and a heavily doped N-type region formed on the P-well.

Abstract: In a NPN transistor electrostatic discharge (ESD) protection structure, certain parameters, including maximum lattice temperature, are improved by introducing certain process changes to provide for SCR-like characteristics during ESD events. A p+region is formed adjacent the collector to define a SCR-like emitter and with a common contact with the collector of the BJT. The p+ region is spaced from the n-emitter of the transistor by a n-epitaxial region, and the collector is preferably spaced further from the n-emitter than is the case in a regular BJT.

Abstract: An electrostatic discharge (ESD) protection device formed in the semiconductor layer of a semiconductor-on-insulator device, wherein the semiconductor layer has first and second wells. A discharge circuit is formed in the first well, operable to discharge the ESD pulse to ground. A pump circuit is formed in the second well, operable to use a portion of an ESD pulse's voltage to pump current into the first well for allowing the discharge circuit to turn on uniformly. The discharge circuit has a plurality of body nodes to the first well. The pump circuit comprises an input pad for receiving a portion of the ESD pulse's voltage; an MOS transistor having source, gate and drain; a capacitor connected between the input pad and the gate, whereby a rising input voltage pulls the gate transiently high for pumping current into the first well; the source is connected to the body nodes of the discharge circuit, and the drain connected to the input pad.

Abstract: When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the emitter of one transistor adjacent to the tails of the sinker down region of the other transistor.

Abstract: The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.

Abstract: An electrostatic discharge (ESD) protection structure for protecting against ESD events between signal terminals is disclosed. ESD protection is provided in a first polarity, by a bipolar transistor (4C) formed in an n-well (64; 164), having a collector contact (72; 172) to one signal terminal (PIN1) and its emitter region (68; 168) and base (66; 166) connected to a second signal terminal (PIN2). For reverse polarity ESD protection, a diode (25) is formed in the same n-well (64; 164) by a p+ region (78; 178) connected to the second signal terminal (PIN2), serving as the anode. The cathode can correspond to the n-well (64; 164) itself, as contacted by the collector contact (72; 172). By using the same n-well (64; 164) for both devices, the integrated circuit chip area required to implement this pin-to-pin protection is much reduced.

Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, a first and a second doped region formed in the substrate. The first and second doped regions are separated from each other by only the substrate region. The ESD protection device includes no gate above the first and second doped regions. Furthermore, the distance separating the first and second doped regions is defined by a length of a resist during a process of forming the ESD protection device.

Abstract: An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that respective first and second channels of the first and second MOS transistors are laterally displaced with respect to one another. The output circuit further includes an isolation region in the substrate, disposed between the first and second MOS transistors. A first conductor connects the source region of the first MOS transistor to a power supply node. A second conductor connects the drain region of the first MOS transistor to the source region of the second MOS transistor. A third conductor connects the drain region of the second MOS transistor to an external signal pad of the integrated circuit device. The isolation region may comprise first and second insulation regions surrounding respective ones of the first and second MOS transistors, and a guard ring surrounding and separating the insulation regions.

Abstract: According to one exemplary embodiment, a bipolar transistor includes a base having a top surface. The bipolar transistor further includes a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further includes a sacrificial post situated between the first and second link spacers, where the first and second link spacers have a height that is substantially less than a height of the sacrificial post. The bipolar transistor also includes a conformal layer situated over the sacrificial post and the first and second link spacers. According to this exemplary embodiment, the bipolar transistor further includes a sacrificial planarizing layer situated over the conformal layer, the first and second link spacers, the sacrificial post, and the base. The sacrificial planarizing layer may include, for example, an organic material such as an organic BARC (“bottom anti-reflective coating”).

Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.

Abstract: To protect against electrostatic discharges in monolithic integrated circuits in CMOS technology, a lateral thyristor structure is presented which has a much lower firing voltage compared to conventional thyristor structures.

Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: A ESD protective device is proposed, including a vertical bipolar transistor connected as a diode, in which the contacting of the collector layer is designed highly resistive. The arrangement, while having a space-saving construction, has an increased snap-back voltage.

Abstract: An ESD protection device encompassing a vertical bipolar transistor that is connected as a diode and has an additional displaced base area. The assemblage has a space-saving configuration and a decreased difference between snapback voltage and breakdown voltage.

Abstract: ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: A semiconductor device for ESD protection of an input/output pad (301) of an integrated circuit built in a substrate of a first conductivity type comprising a multi-finger MOS transistor (304), its source (304b) and its gate (304c) connected to ground potential and its drain (304a) connected to the I/O pad. A well of the opposite conductivity type, partially separated from the substrate by shallow trench isolations, has a diode (302), its anode (302b) connected to the pad and also to the transistor drain, and its cathode (302a) connected to power 303). These transistor and diode connections create a parasitic silicon controlled rectifier (SCR) with the SCR-anode (310a) formed by the diode anode, the first base region formed by the well, the second base region formed by the substrate, and the SCR-cathode (311a) formed by the transistor source. The SCR structure provides a significantly lower clamping voltage and an about two times higher failure current than a substrate-pumped MOS transistor.