Abstract: An improved process and integrated-circuit having CMOS (NMOS and/or PMOS) devices formed on a substrate and a NMOS electro static discharge circuit formed in a P well on the substrate. The improvement includes an electro static discharge NMOS circuit having an undoped polysilicon gate electrode, and the NMOS FET devices having n-type doped gate electrodes. The undoped gate polysilicon electrode of the electro static discharge transistor increases the gate oxide breakdown voltage thus making the ESD transistor able to withstand a greater voltage discharge and therefore providing better protection to the product devices.

Abstract: The present invention is a diamond electrode with high efficiency, a small overvoltage, and a long lifetime, which is reusable, and which can measure the temperature of the electrode. The diamond electrode is at least partially composed of a semiconducting diamond film, whose surface is chemically modified. Another embodiment of the present invention carbon is used as a bare electrode material, diamond crystals are fixed to the bare electrode material, the surface of the undoped diamond crystals are covered with semiconducting diamond film, or semiconducting diamond crystals are fixed to said bare electrode material, and the surfaces of diamond films or crystals are chemically modified. Furthermore, wires may be connected to the diamond electrode to measure the electrical resistance, and hence the temperature.

Abstract: A polysilicon gate electrode of an integrated circuit field effect transistor is formed in two portions which are isolated from one another. The first portion is formed on the gate insulating region. The second portion is formed on the semiconductor substrate outside the gate insulating region and is electrically insulated from the first portion. Since the first and second portions of the polysilicon gate electrode are isolated from one another, only the charge which is on the first polysilicon portion contributes to gate insulating region degradation during plasma etching. After polysilicon gate electrode formation, the first and second portions may be electrically connected by a link. Field effect transistor performance and/or reliability are thereby increased.

Abstract: In a semiconductor integrated circuit device, particularly in a switch circuit, a first and a second FETs are connected in series with respect to the signal path, and a third FET is connected between the node of these first and second FETs and the ground region. Thereby, low insertion loss, high isolation, and miniaturization of the entire circuit can be realized simultaneously.

Abstract: A semiconductor body is covered by a polysilicon layer having a gate electrode and a contact surface for fastening a gate lead. An integrated ohmic resistor connects the gate electrode to the contact surface.

Abstract: A variable operation speed MOS transistor having a source, a drain and a gate with a plurality of contacts formed thereon. One end of the gate of the variable operation speed MOS transistor is connected to drains/sources of first MOS transistors, while the plurality of the contacts formed on the gate of the variable operation speed MOS transistor are connected to the drains/sources of second MOS transistors, which are of an opposite type to that of the first MOS transistors, and the source or drains of which are connected to Vcc. Input signals are supplied to the respective gates of the first and second MOS transistors in such a manner as to adjust the turn-on and turn-off speeds of the variable operation speed MOS transistor.

Abstract: An N-type HIGFET (10) utilizes two etch layers (17,18) to form a gate insulator (16) to be shorter that the gate electrode (21). This T-shaped gate structure facilitates forming source (23) and drain (24) regions that are separated from the gate insulator (16) by a distance (22) in order to reduce leakage current and increase the breakdown voltage.

Abstract: An insulated gate field-effect transistor or similar semiconductor-insulator-semiconductor structure has an increased time-dependent dielectric failure lifetime due to a reduction in the field across the gate insulator. The electric field in the gate insulator is reduced without degrading device performance by limiting the field only when the gate voltage exceeds its nominal range. The field is limited by lowering the impurity concentration in a polysilicon gate electrode so that the voltage drop across the gate insulator is reduced. In order to avoid degrading the device performance when the device is operating with nominal voltage levels, a fixed charge is imposed at the interface between the gate electrode and the gate insulator, so at a gate voltage of about the supply voltage level the response changes to exhibit less increase in the drop across the gate insulator for higher voltages.

Abstract: A semiconductor device has a semiconductor element comprising polycrystal silicon and into which high-concentration donors and high-concentration acceptors have been introduced in substantially the same amounts, and enables control of a work function of a semiconductor element by adjustment of the concentrations of the donor and acceptor. This semiconductor device is manufactured by the formation of a heat oxide film on a semiconductor substrate, the use of a low-pressure CVD method to form a polysilicon thin film to a required thickness, the implantation in the same high-concentrations of the donor and acceptor into the polysilicon thin film, and heat processing in a required atmosphere, for a required time and at a required temperature to diffuse and activate the injected donor and acceptor.

Abstract: In a semiconductor device, a signal delay element is configured by using resistance and capacitance components included in a region except regions where logic elements for a gate array exist, and the signal delay element is inserted between a logic element for outputting signals and logic elements for receiving the signals and connected to these logic elements. A placing and wiring apparatus for producing the semiconductor device is disclosed.

Abstract: The invention relates to a semiconductor device having an electrode formed on an region ranging from its thin insulating film in an element forming region to its thick insulating film in an isolation region, and it is an object of the invention to provide a semiconductor device capable of improving dielectric strength of a thin insulating film under a electrode in the boundary region between a thin insulating film and a thick insulating film as well as improving the film quality of the thin insulating film.

Abstract: An MOS transistor has a source region, a drain region, first gate electrode with a first channel zone allocated to it, second gate electrodes having a second channel zone allocated to it, and a third gate electrode with a corresponding third channel zone. The second channel zone is more highly doped than the base material in which the MOS transistor is formed, while the third channel zone is more lightly doped than the second channel zone. The second and third gate electrodes are conductively connected so that higher drain voltages are accommodated at high-frequencies while avoiding tunnel punch-through.

Abstract: A semiconductor device has a semiconductor element comprising polycrystal silicon and into which high-concentration donors and high-concentration acceptors have been introduced in substantially the same amounts, and enables control of a work function of a semiconductor element by adjustment of the concentrations of the donor and acceptor. This semiconductor device is manufactured by the formation of a heat oxide film on a semiconductor substrate, the use of a low-pressure CVD method to form a polysilicon thin film to a required thickness, the implantation in the same high-concentrations of the donor and acceptor into the polysilicon thin film, and heat processing in a required atmosphere, for a required time and at a required temperature to diffuse and activate the injected donor and acceptor.

Abstract: A thin film transistor gate structure with a three-dimensional multichannel structure is disclosed.The thin film transistor gate structure according to the present invention comprises source/drain electrodes formed so as to be spaced from and opposite to each other on a substrate; semiconductive layers, comprised of a plurality of sub-semiconductive layers, each formed in a row, each end of the sub-semiconductive layers being in ohmic-contact with the source/drain electrodes; gate insulating layers surrounding each of the semiconductive layers; and gate electrodes surrounding each of the gate insulating layers.Accordingly, the whole outerlayers of each sub-semiconductive layer surrounded by the gate electrodes serve as channel regions. As a result, the effective channel area increases, thereby improving the channel conductance and current driving ability.

Abstract: In a bipolar static induction transistor (BSIT) with increased input impedance, gate-voltage control is used for switching operations. The BSIT includes a collector region, a base region, an emitter region, and a source region in the base region. For enhanced turn-off, an auxiliary base region is included; alternatively, a drain region is provided in the base region.

Abstract: There is provided a power semiconductor integrated circuit device without lowering a breakdown voltage of a pn junction located below a wiring layer to which a high voltage is applied. The device includes an N.sup.- -type semiconductor substrate which is provided with an N.sup.+ -type region and a P.sup.+ -type region to form, for example, a lateral diode. An insulating film is formed over the substrate surface, on which a wiring layer is provided so as to be connected to the N.sup.+ -type region and to pass over the P.sup.+ -type region. A film resistor connected between the N.sup.+ -type region and the P.sup.+ -type region is formed in the insulating film so as to be crossed by the wiring layer at least once.

Abstract: The channel resistance of a MOSFET is made independent of V.sub.S -V.sub.D by maintaining the ends of the gate electrode adjacent the source and drain regions at an offset voltage with respect to the source and drain regions, respectively, and by maintaining the portions of the body region adjacent to the source and drain regions at another offset voltage with respect to the source and drain regions, respectively. In this manner, V.sub.S -V.sub.D appears across the channel, across the gate, and across the body region beneath the channel. The resulting linear voltage drops along each of the three causes the channel-to-gate and channel-to-body potentials to be constant along the entire length of the channel, thereby avoiding variations in the number of carriers, mobility variations and body effect in the channel.

Abstract: A PROM cell allows improved, lower voltage programming and reduced leakage of the charge from the floating gate to the substrate (channel) region. The inventive cell uses a thin gate oxide layer along with a floating gate which is lightly doped except on one edge. This edge, for example near the drain region, is heavily doped with an angled implant. The thin gate oxide functions as thick oxide under the lightly doped region, thereby preventing the leakage and high coupling between the substrate and floating gate of a conventional thin oxide layer. The thin oxide under the heavily doped areas of the floating gate functions as thin oxide, thereby allowing improved, lower voltage programming.

Abstract: An electromechanical sensor is provided which comprises an n-type semiconductor region which defines a flexible member surrounded by a thicker base portion; at least one piezoresistor formed in the semiconductor region; an n+ region formed in the thicker base portion; a first insulative layer which overlays the piezoresistor and which extends at least from the piezoresistor to the first n+ doped region; a guard layer which overlays at least a portion of the first insulative layer such that the guard layer overlays the piezoresistor and extends at least from the piezoresistor to a point adjacent to the n+ region; and a first bias contact which electrically interconnects the n+ region and the guard layer.