Abstract: The present invention facilitates memory devices and operation of dual bit and single bit memory devices by providing systems and methods that employ a salicide block to vary and equalize the resistance of a memory array during fabrication. The present invention includes utilizing a common charge dissipation region to mitigate charge-loss by providing protection against charging up of the various lines as a result of further plasma etching processes. The salicide block equalizes the charge dissipation in the memory array by providing each wordline path with a varied amount of resistance in addition to the total path resistance. Because the charge protection provided to each wordline otherwise varies depending on the resistance path to a common discharge element, a salicide block for resistance equalization provides greater reliability and predictability during processing. Other such shapes conducive for any desired resistance path fall within the scope of the invention.

Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.

Abstract: A semiconductor device includes a first MIS transistor of a non-salicide structure and a second MIS transistor of a salicide structure which are both formed on a substrate of silicon. The first MIS transistor includes a first gate electrode of silicon, first sidewalls, a first source and drain, and plasma reaction films grown in a plasma atmosphere to cover the top surfaces of the first gate electrode and first source and drain, wherein the plasma reaction film prevents silicide formation on the first MIS transistor.

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.

Abstract: A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.

Abstract: A method of forming a silicon germanium conduction channel under a gate stack of a semiconductor device, the gate stack being formed on a silicon layer on an insulating layer, the method including growing a silicon germanium layer over said silicon layer and heating the device such that germanium condenses in the silicon layer such that a silicon germanium channel is formed between the gate stack and the insulating layer.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor.

Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

Abstract: Threshold variability in advanced transistor elements, as well as increased leakage currents, may be reduced by incorporating a barrier material in a polysilicon gate electrode. The barrier material results in a well-controllable and well-defined metal silicide in the polysilicon gate electrode during the silicidation sequence and during the further processing by significantly reducing the diffusion of a metal species, such as nickel, into the vicinity of the gate dielectric material.

Abstract: A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.

Abstract: A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.

Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region in the semiconductor substrate; a gate insulating film formed on the active region; and a gate electrode formed across the boundary between the active region and the isolation region adjacent to the active region. The gate electrode includes a first portion which is located above the active region with the gate insulating film interposed therebetween and is entirely made of a silicide in a thickness direction and a second portion which is located above the isolation region and is made of a silicon region and the silicide region covering the silicon region.

Abstract: A method for fabricating a semiconductor integrated circuit and resulting structure. The method includes providing a semiconductor substrate with an overlying dielectric layer and forming a polysilicon gate layer and an overlying capping layer. The gate layer is overlying the dielectric layer. The method also includes patterning the polysilicon gate layer to form a gate structure and a local interconnect structure. The gate structure and the local interconnect structure include a contact region defined therebetween. The gate structure also includes the overlying capping layer. The method includes forming sidewall spacers on the gate structure and the local interconnect structure and removing the sidewall spacer on the local interconnect structure. The method also includes forming contact polysilicon on the contact region and implanting a dopant impurity into the contact polysilicon.

Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

Abstract: A semiconductor device comprising a substrate having a transistor that includes a metal gate structure; a first oxide layer formed over the substrate; a silane layer formed on the first oxide layer; and a non-conductive metal oxide layer grown on the metal gate structure, wherein the silane layer inhibits nucleation and growth of the non-conductive metal oxide layer.

Abstract: A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer

Abstract: A trench metal oxide semiconductor field effect transistor (MOSFET) with a terraced trench gate. An epitaxial layer with a plurality of trenches is provided and a gate oxide layer is covered the sidewalls and bottoms of the trenches. A polysilicon layer is filled in the trenches, wherein the polysilicon layer is higher than the sidewalls of the trenches to be used as a gate of the MOSFET. A plurality of sources and bodies are formed in the epitaxial layer, and the bodies at both sides of the trenches. An insulating layer is covered on the substrate, wherein a plurality of metal contact windows are provided. Metal plugs are filled in the metal contact windows to form metal connections for the MOSFET.

Abstract: The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack.

Abstract: An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region. A conductive contact is in contact with the internal portion and the outer portion of the metal silicide layer.

Abstract: Provided is an integrated circuit including a transistor with a gate electrode. The gate electrode includes a polysilicon layer in contact with a gate dielectric layer separating the gate electrode and a semiconductor substrate that comprises an active region of the transistor. The gate electrode includes sidewall structures extending along lower portions of opposing sidewalls of the polysilicon layer, the lower portion being oriented to the semiconductor substrate. The gate electrode also includes a barrier layer. A first section of the barrier layer extends along an upper portion of the sidewall of the polysilicon layer, the upper portion being adjacent to the lower portion and facing away from the semiconductor substrate.

Abstract: A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy (i.e., metal silicide) layer. The stressed layer is self-aligned to the gate conductor. The inventive structure also has a reduced external parasitic S/D resistance as a result of having a metallic contact located atop source/drain regions that include a surface region comprised of a metal semiconductor alloy. The metallic contact is self-aligned to the gate conductor.

Abstract: A transistor includes a gate insulating layer over a semiconductor substrate; a first insulating layer on both sides of the gate insulating layer; first spacers over the first insulating layer and being spaced apart from each other; and a gate conductive plug between the first spacers. A method for manufacturing a transistor includes sequentially depositing a first insulating layer and a second insulating layer over a semiconductor substrate; etching the second insulating layer; implanting impurity ions; depositing and etching a layer of spacer material to form first spacers; removing a first portion of the first insulating layer between the first spacers; depositing a gate insulating layer the place of the first portion of the first insulating layer; forming a gate conductive plug on the gate insulating layer; forming second spacers on sidewalls of the gate conductive plug; and forming a silicide on an upper surface of the gate conductive plug.

Abstract: Disclosed is a method of fabricating a semiconductor device that includes field effect transistors each having a gate electrode formed only of a metal silicide which overcomes the problem of depletion of the gate and makes adjustment of a work function easier, and that has a high integration with the existing process and a high cost performance. The method fabricates a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate insulating layer, and a source and a drain having an elevated structure with the gate electrode in between, and includes a step at which the gate electrode is silicidized to form a metal silicide.

Abstract: A semiconductor device includes a semiconductor substrate having a resistor region, an isolation layer disposed in the resistor region, the isolation layer defining active regions, first conductive layer patterns disposed on the active regions, a second conductive layer pattern covering the first conductive layer patterns and disposed on the isolation layer, the second conductive layer pattern and the first conductive layer patterns constituting a load resistor pattern, an upper insulating layer disposed over the load resistor pattern, and resistor contact plugs disposed over the active regions, the resistor contact plugs penetrating the upper insulating layer to contact the load resistor pattern.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate insulating film; a first silicide layer formed on the gate electrode; a channel region formed in the semiconductor substrate below the gate electrode; source/drain regions formed in regions in the semiconductor substrate, the regions sandwiching the channel region; and second silicide layers formed on the source/drain regions and having an average grain size smaller than that of the first silicide layer or an average number of compositional boundaries in a crystal grain larger than that of the first silicide layer.

Abstract: The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 ?m.

Abstract: The present invention in one embodiment provides a method of producing a device including providing a semiconducting device including a gate structure including a silicon containing gate conductor atop a substrate; forming a metal layer on at least the silicon containing gate conductor; and directing chemically inert ions to impact the metal layer, wherein momentum transfer from of the chemically inert ions force metal atoms from the metal layer into the silicon containing gate conductor to provide a silicide gate conductor.

Abstract: Embodiments relate to a method of fabricating a semiconductor device. In embodiments, a gate pattern may be formed on a semiconductor substrate, and sidewalls having a lower height than a height of the gate pattern may be formed at both sides of the gate pattern using a photoresist pattern. A silicide layer may be formed on exposed upper surface and side surfaces of the gate pattern and a portion of the semiconductor substrate at both sides of the sidewalls. Therefore, the silicide layer formed on a gate may be enlarged, and may reduce gate resistance.

Abstract: In accordance with one or more embodiments, a semiconductor structure includes a semiconductor substrate, a first semiconductor material over the semiconductor substrate, and a second semiconductor material over a portion the first semiconductor material, wherein the second semiconductor material comprises silicon-germanium-carbon (SiGeC) and wherein the first semiconductor material is a silicon epitaxial layer. The semiconductor structure further includes an active device, wherein a portion of the active device is formed in the second semiconductor material and a dielectric structure extending from the first surface of the first semiconductor material into the semiconductor substrate through the first semiconductor material.

Abstract: A gate is silicided through its sides while limiting silicidation through the top of the gate. A blocking layer may be formed over the gate layer, and the sidewalls of the gate layer are exposed. A layer of metal is formed on the sidewalls of the gate and thermally treated to silicide the gate layer. The sidewalls of the gate maybe exposed through an etching process in which a silicide layer formed over the blocking layer is used as an etch mask.

Abstract: Semiconductor devices and manufacturing methods thereof are provided. A semiconductor device can include a gate dielectric, a gate electrode, sidewall spacers, and source and drain regions. The gate electrode can include an electrode seed layer and an electrode metal layer. In another embodiment, the gate electrode can be formed of a deposited metal silicon layer.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a gate electrode that includes a body part disposed on the semiconductor substrate and a projecting part projecting downward from the body part; and source/drain regions at opposite sides of the gate electrode.

Abstract: A method for manufacturing a semiconductor device includes a gate dielectric film formed over an active area of a semiconductor substrate, and a gate electrode formed over the gate dielectric film and formed of a silicidation film having a polysilicon area at the bottom of the gate electrode. Therefore, with embodiments, a work function can variously controlled and the gate pattern having different work function can be applied to the transistors by using a non-silicided polysilicon region due to the formation a partially silicided gate pattern, such that the resistance of the gate electrode and junction can be reduced, making it possible to maximize the device characteristics.

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat.

Abstract: A element isolation insulating film is formed around the device regions in the silicon substrate. The device regions are formed an n-type diffusion layer region, a p-type diffusion layer region, a p-type extension region, an n-type extension region, a p-type source/drain region, an n-type source/drain region, and a nickel silicide film. Each gate dielectric film is made up of a silicon oxide film and a hafnium silicon oxynitride film. The n-type gate electrode is made up of an n-type silicon film and a nickel silicide film, and the p-type gate electrode is made up of a nickel silicide film. The hafnium silicon oxynitride films are not formed on the sidewalls of the gate electrodes.

Abstract: By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectivity may be achieved during the contact etch stop layer opening. Hence, undue etching of the highly doped silicon material of the active region would be suppressed. Additionally or alternatively, an appropriately designed test structure is disclosed, which may enable the detection of electrical characteristics of contact structures formed in accordance with a specified manufacturing sequence and on the basis of specific design criteria.

Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.

Abstract: A semiconductor device capable of preventing a bridge generation during performing an etching process to form a plurality of gate structures on a substrate divided into an active region and a field region and an electrical short between a contact plug and the individual gate structure in the field region and a method for fabricating the same are provided. The semiconductor device includes: a substrate provided with an active region and a field region; a field oxide layer formed in the field region in such a way that the field oxide layer is recessed to be lower than a surface of the substrate disposed in the active region; and a plurality of gate structures formed on the field oxide layer and the substrate in the active region.

Abstract: A semiconductor device with an increased channel length and a method for fabricating the same are provided. The semiconductor device includes: a substrate with an active region including a planar active region and a prominence active region formed on the planar active region; a gate insulation layer formed over the active region; and a gate structure including at least one gate lining layer encompassing the prominence active region on the gate insulation layer.

Abstract: Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less.

Abstract: A CMOS image sensor and a method for forming the same are provided. According to the method, a gate insulating layer and a doped polysilicon layer which are sequentially stacked on a substrate are patterned to form a transfer gate and a reset gate set apart from each other. A floating diffusion layer between the transfer gate and the reset gate, a light receiving element at a side of the transfer gate away from and opposite to the floating diffusion layer and a source/drain region at a side of the reset gate away from and opposite to the floating diffusion layer are formed. An insulation layer and a mold layer are sequentially formed on an entire surface of the substrate, and the mold layer is planarized until the insulation layer is exposed. The exposed insulation layer is removed to further expose an upper surface of the gates. A selective silicidation process is carried out using a metal gate layer to form a metal gate silicide on the exposed gate.

Abstract: A semiconductor structure includes a semiconductor substrate having a first device area and a second device area. A gate layer is formed across the first device area and the second device area on the semiconductor substrate, wherein a first portion of the gate layer running across the first device area is doped with impurities of a type different from that of a second portion of the gate layer running across the second device area. A cap layer is formed on the gate layer for protecting the same covered thereunder from forming a silicide structure, having at least one opening at a junction of the first and second portions of the gate layer. A silicide layer is formed on the gate layer that is exposed by the opening for reducing resistance at the junction between the first and second portions.

Abstract: A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.

Abstract: A semiconductor device provided with a semiconductor silicon substrate and gate wiring provided on the semiconductor silicon substrate via a gate oxide film, where the gate wiring has a gate electrode, a gate wiring upper structure provided in contact with the gate electrode, and a side wall spacer, the side wall spacer is comprised of one kind or two or more kinds of inorganic compound insulating layers, and at least one kind of the inorganic compound insulating layer is comprised of silicon oxynitride with a nitrogen content ranging from 30 to 70%.

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

Abstract: A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, a first conductive layer over the gate insulation layer, and a second conductive layer over the first conductive layer, etching the second conductive layer to form a second gate electrode using a first mask pattern having a first width, forming an insulation layer over a resultant where the second gate electrode is formed, and etching the insulation layer, the first conductive layer and the gate insulation layer sequentially to form a gate using a second mask pattern having a second width greater than the first width, the gate including an etched gate insulation layer, a first gate electrode, the second gate electrode, and a gate hard mask, which are stacked in sequence, wherein both sidewalls and a top surface of the second gate electrode are covered with the gate hard mask.

Abstract: A semiconductor memory device has a memory region which is formed on a semiconductor substrate and in which a plurality of memory cells each including a memory transistor are arranged as a matrix using a plurality of impurity diffusion layers (bit lines) and a plurality of gate electrodes (word lines) intersecting each other. The gate electrode of each of the memory transistors has an upper surface thereof formed into a protruding portion which is higher in level at the middle portion than at the edge portions. A silicide layer is formed on the upper surface of the protruding portion of the gate electrode of each of the memory transistors.

Abstract: A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located over the substrate adjacent the recess. Among the advantages: the gate structure lowers overall gate resistance and reduces the short channel effect.

Abstract: A semiconductor device with higher reliability and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor layer overlapping with a gate electrode and having an impurity region outside a region which overlaps with the gate electrode; a first conductive layer which is provided on a side provided with the gate electrode of the semiconductor layer and partially in contact with the impurity region; an insulating layer provided over the gate electrode and the first conductive layer; and a second conductive layer which is formed in the insulating layer and in contact with the first conductive layer through an opening at least part of which overlaps with the first conductive layer.