Abstract: Some spin tunnel transistors with a larger current transmittance and a higher MR ratio are described. One of the spin tunnel transistor comprises a collector; an emitter; a base formed between the collector and the emitter, including a first ferromagnetic metal layer variable in its magnetization under an external magnetic field; a barrier layer formed between the first ferromagnetic metal layer and one of the collector and the emitter, the other of the collector and the emitter including a semiconductor crystal layer; and a transition metal silicide crystal layer between the semiconductor crystal layer and the base. The transition metal silicide crystal layer may be replaced with a palladium layer, a transition metal nitride layer, or a transition metal carbide layer.

Abstract: A magnetic field sensor includes a transistor device having a base region, an emitter region, and a collector region. A barrier region disposed between the emitter region and the collector region to hamper charge carriers injected into the base region from the emitter region from reaching at least a portion of the collector region. The magnetic field sensor further includes a first voltage source to bias the collector region with respect to the base region to form a space-charge layer associated with the collector region.

Abstract: A memory includes an array of magnetic memory cells, each magnetic memory cell being adapted to store a bit of information, interconnects in communication with the magnetic memory cells, and conductors in communication with the magnetic memory cells and the interconnects, the conductors filling spaces between adjacent magnetic memory cells of the array.

Abstract: The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor itself formed within a trench of an insulating layer. The present invention protects the MTJ from the voltages created by the write conductor by isolating the write conductor and enabling the reduction of current necessary to write a bit of information.

Abstract: A spin transistor (10) comprises a spin injector (50) formed of a ferromagnetic material and constituting the emitter (20) of a three-terminal device, a spin filter (70) also formed of a ferromagnetic material and constituting a collector (40), and a semiconductor base (30) region. A tunnelling barrier (60) is formed of an insulating metal oxide such as aluminium oxide between the emitter (20) and the base (30). The tunnelling barrier (60) reduces the degree of spin depolarization as carriers are injected into the base (30), and permits selection of spin injection energy. In preferred embodiments, a second tunnelling barrier (80) may be formed between the base (30) and the collector (40). A method of manufacture is also provided.

Abstract: A magnetic sensor device formed using SOI CMOS techniques includes a substrate, a silicon oxide layer and in some cases a plurality of gated regions. A first terminal is located between two innermost gated regions and supplies a supply voltage. A second and a third terminal, each of which is located between two adjacent gated regions other than the two innermost gated regions, output positive and negative Hall voltages. By appropriately controlling a bias voltage to the gated regions, small changes in a magnetic field induces larger currents in channel regions under the gated regions, which, in turn, results in detectable Hall voltages.

Abstract: A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.

Abstract: A semiconductor slider including an integral spin valve transistor (SVT) having a read width of 250 nm or less disposed on a monolithic semiconductor substrate, useful in magnetic data storage applications. The monolithic slider may also include other magnetic and semiconductor transistor structures and is fabricated in a single process using standard thin-film processing steps. The SVT includes a sensor stack having a top surface and including a first ferromagnetic (FM) layer in contact with and forming a Schottky barrier at the monolithic semiconductor substrate, a FM shield layer disposed over the sensor stack and in electrical contact with the top surface thereof, a SVT emitter terminal coupled to the FM shield, a SVT collector terminal coupled to the substrate and a SVT base terminal coupled to the first FM layer. The sensor stack may include a spin valve (SV) stack or a tunnel valve (TV) stack, for example.

Abstract: A spin valve transistor, magnetic reproducing head including a spin valve transistor and a magnetic information storage system having the spin valve transistor. The spin valve transistor has a collector, a base formed on the collector, a tunnel barrier layer formed on the base and an emitter formed on the tunnel barrier layer. In one embodiment, the collector may have a first semiconductor layer of first composition and a second semiconductor layer of a different composition epitaxially grown. The base of the first spin valve transistor may be formed on the second semiconductor layer and have a magnetization pinned layer having a magnetization substantially fixed in an applied magnetic field, a nonmagnetic layer and a magnetization free layer having a magnetization free to rotate under the applied magnetic field. The emitter of a spin valve transistor of a second embodiment may include a semiconductor layer containing an oxide of transitional metal and contacting the tunnel barrier layer.

Abstract: A semiconductor magnetic sensor includes a semiconductor substrate, a source, a drain, a gate, and a carrier condensing means. The source and the drain are located in a surface of the substrate. One of the source and the drain includes adjoining two regions. The gate is located between the source and the drain for drawing minority carriers of the substrate to induce a channel, through which the carriers flow between the source and the drain to form a channel carrier current. The carriers flow into the two regions to form two regional carrier currents. The magnitude of a magnetic field where the sensor is placed is measured using the difference in quantity between the two regional carrier currents. The carrier condensing means locally increases carrier density in the channel carrier current in the proximity of an axis that passes between the two regions in order to increase the difference.

Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer, an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 &mgr;m deep and 5 to 6 &mgr;wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

Abstract: Proposed are a device, a magnetic-field sensor and a current sensor, the device having the feature that provision is made for a first magnetic-field sensing means, for a second magnetic-field sensing means, and for a third magnetic-field sensing means, a first output variable of the first magnetic-field sensing means being provided as a first input variable, a second output variable of the first magnetic-field sensing means being provided as a second input variable, the first input variable being provided as input variable for the second magnetic-field sensing means, and the second input variable being provided as input variable for the third magnetic-field sensing means.

Abstract: A dual polysilicon emitter, complementary output is provided which utilizes a buried power buss. While providing these advantages, the process is not complicated. The process has the speed performance of the ASSET technology with an easier process to produce. In addition, the process described in the present invention provides additional advantages that the ASSET process does not have.

Abstract: The present invention provides a thin magnetoelectric transducer which has a projected size substantially equal to that of a pellet and which can be subjected to an inspection test nondestructively. The magnetoelectric transducer has a semiconductor device provided on the upper surface of a projecting portion of a projecting nonmagnetic insulating substrate 9 and comprising a magnetosensitive section 3 and inner electrodes 2 made of metal. A conductive resin layer 4 is formed on the internal electrodes 2 and on part of the side surfaces of the projecting portion. A strain buffering layer 5 is formed at least on the magnetosensitive section 3. Furthermore, at least the strain buffering layer 5 on the magnetosensitive section 3 is coated with a protective layer 6.

Abstract: Wafer-level stage testing of semiconductor lasers can be facilitated by directing a light beam emitted from the semiconductor laser toward a direction different from a path of the light beam as originally emitted from the laser. A test structure can be coupled to a back facet of the laser and can include a first region separated from a second region by an inclined interface. When a light beam is emitted from the laser, the light beam can be received on the inclined interface and then directed toward a light detector for detection and evaluation.

Abstract: The unipolar spin transistor includes a first semiconductor region having a conductivity type and a first spin polarization, and a second semiconductor region having a conductivity type that is the same conductivity type of the first semiconductor region and a second spin polarization that is different from the first spin polarization of the first semiconductor region, and a third semiconductor region having a conductivity type that is the same conductivity type of the first semiconductor region and the first spin polarization. The unipolar spin transistor can also include a magnetic semiconductor wherein the semiconductor material is in a high-resistance state when the second spin polarization of the second region is opposite to the first spin polarization of the first and third regions, and wherein the semiconductor material is in a low-resistance state when the second spin polarization of the second region is aligned to the first spin polarization of the first and third regions.

Abstract: A Hall effect device comprising: (a) an electrically-conductive layer or plate having a top surface: and (b) a ferromagnetic multilayer, where the conductive film or layer is composed of high mobility semiconductors. Also, a Hall effect device can be a device in which the Hall plate comprises an indium compound, germanium or mixtures thereof. The devices are useful for a variety of applications such as a memory element in a nonvolatile random access memory array (NRAM) and as a logic gate.

Abstract: A magnetic random access memory (MRAM) is disclosed. The MRAM may include a semiconductor substrate serving as a base of a bipolar junction transistor; an emitter and a collector of the bipolar junction transistor provided at an active region of the semiconductor substrate; an MTJ cell positioned at the active region between the emitter and the collector, separately from the emitter and the collector by a predetermined distance; and a word line provided on the MTJ cell. The MRAM may also include a bit line contacting the collector; and a reference voltage line contacting the emitter. As a result, the constitution and fabrication process of the MRAM are simplified to improve productivity and properties of the device.

Abstract: A magnetic random access memory (MRAM) array includes a plurality of magnetic tunnel junction (MTJ) memory cells and a plurality of non-electronic switching elements, each MTJ memory cell and an associated switching element being in electrical series connection and located between the bit and word lines of the array. The switching element is a layer of vanadium dioxide, a material that exhibits a first order phase transition at a transition temperature of approximately 65° C. from a low-temperature monoclinic (semiconducting) to a high-temperature tetragonal (metallic) crystalline structure. This phase transition is accompanied by a change in electrical resistance from high resistance at room temperature to low resistance above the transition temperature. To read a memory cell, the vanadium dioxide switching element associated with that cell is heated to lower the resistance of the switching element to allow sense current to pass through the cell, thereby enabling the memory state of the cell to be read.

Abstract: A Hall effect device comprising: (a) an electrically-conductive layer or plate having a top surface; and (b) a ferromagnetic layer, where the conductive film or layer is composed of high mobility semiconductors. Also, a Hall effect device can have a ferromagnetic element that is a multilayer (e.g., a bilayer), and a device in which the Hall plate comprises an indium compound, germanium or mixtures thereof. The devices are useful for a variety of applications such as a memory element in a nonvolatile random access memory array (NRAM) and as a logic gate.

Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5 to 6 um wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

Abstract: A microelectromechanical system (MEMS) device is disclosed for determining the position of a mover. The MEMS device has a bottom layer connected to a mover layer. The mover layer is connected to a mover by flexures. The mover moves relative to the mover layer and the bottom layer. The flexures urge the mover back to an initial position of mechanical equilibrium. The flexures include coupling blocks to control movement of the mover. The MEMS device determines the location of the mover by determining the capacitance between mover electrodes located on the coupling blocks of the flexures and counter electrodes located on an adjacent layer. The coupling block moves according to a determinable relationship with the mover. As the coupling block moves, the capacitance between the mover electrode and the counter electrode changes. A capacitance detector analyzes the capacitance between the electrodes and determines the position of the mover.

Abstract: A magnetic memory element has a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer disposed between these ferromagnetic layers. The non-magnetic layer has an electrical characteristic that is changeable depending on an external magnetic field applied to the non-magnetic layer.

Abstract: A structure of a new active pixel sensor cell formed in a semiconductor substrate is disclosed. An n-type region is formed in the substrate extending to the surface. Two p+ regions are formed in the n-type region, both extending to the surface and covering almost all the active area of the new active pixel sensor cell. The p+ region forming the p+ node of the photodiode has a substantially larger surface area than the p+ region forming the p+ node of the output diode. Isolation regions are formed over those portions of the new active pixel cell periphery that will not be adjacent to other new active pixel sensor cells. A polysilicon floating gate is disposed over a dielectric layer formed over the surface. The floating gate overlaps portions of both p+ regions and the floating gate is connected to photodiode p+ region by a conducting region passing through the dielectric layer.

Abstract: A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its deflected state. In one embodiment, the cantilever is deflected by an electrostatic attraction arising from a voltage potential between the cantilever and a control electrode. In another embodiment, the cantilever is formed of a material with high magnetic permeability, and is deflected in response to complementary magnetic fields induced in the cantilever and in an adjacent electrode. The nanomechanical switch can be fabricated using well known semiconductor fabrication techniques, although semiconductor materials are not necessary for fabrication. The switch can rely upon physical contact between the cantilever and the adjacent electrode for current flow, or can rely upon sufficient proximity between the cantilever and the adjacent electrode to allow for tunneling current flow.

Abstract: A magnetic random access memory (MRAM) is disclosed. The MRAM may include a semiconductor substrate serving as a base of a bipolar junction transistor; an emitter and a collector of the bipolar junction transistor provided at an active region of the semiconductor substrate; an MTJ cell positioned at the active region between the emitter and the collector, separately from the emitter and the collector by a predetermined distance; and a word line provided on the MTJ cell. The MRAM may also include a bit line contacting the collector; and a reference voltage line contacting the emitter. As a result, the constitution and fabrication process of the MRAM are simplified to improve productivity and properties of the device.

Abstract: A radio module (10) suitable for RF applications, especially for Bluetooth, comprises a substrate (1) with a semiconductor device (11), a shield (21), and an antenna (31). The shield (21) is located between the antenna (31) and the semiconductor device (11), and is present on the same side (2) of the substrate (1) as the semiconductor device (11) and the antenna (31). By preference, the antenna (31) and the shield (21) are connected to one another by support means (32, 42).

Abstract: A personal appliance integrated with a biometric security system which includes a CMOS image sensor, a signal processor, and memory, and wherein the biometric security system restricts access to the appliance to authorized individuals, and may be programmed to disable or destroy designated data or other information of a confidential or proprietary nature within the appliance when certain conditions are satisfied.

Abstract: The present invention relates to a power MOS transistor that permits a large current to flow without a broad gate width being employed. A power MOS transistor of this kind comprises a substrate of a first conductivity type; a well region of a second conductivity type; a first electrode region whose impurity concentration is higher than that of the well region; a region of a first conductivity type; and a second electrode region. The first electrode region, first-conductivity-type region and second electrode region are respectively arranged in this order so as to be spaced apart from one another in a first direction. The first-conductivity-type region is constituted by a plurality of first-conductivity-type sub-regions, which are provided so as to be spaced apart from one another in a second direction that is orthogonal to the first direction. A surface channel region is formed between adjacent first-conductivity-type sub-regions.

Abstract: There is provided a transmission circuit which can certainly perform transmission of data of digital form between two circuits operating in synchronization with two clock signals having the same frequency even if phase shift is generated between the two clock signals. According to a phase difference between a clock signal CK1 and a clock signal CK2, the transmission circuit performs either one of an operation of outputting pre-transmission digital data inputted to the transmission circuit as it is or after it is inverted, and an operation of sampling it in synchronization with the clock signal CK2 and outputting it as it is or after it is inverted.

Abstract: A spin transistor is a hybrid magnetic/semiconductor transistor in which a magnetically controllable barrier is provided between a semiconductor base and collector to control the diffusion of charge carriers to the collector. With the spin transistor, the charge carrier populations are distinguished by the direction of the spin or magnetic moment of the carriers instead of the electronic charge. A spin injector is used to spin polarize the charge carrier population so that the population has a selected magnetic moment which population may or may not be enabled to flow to the collector via the magnetic barrier. The spin transistor utilizes the electronic characteristics of a conventional semiconductor transistor in combination with a carrier flow controlled by magnetic moment to maximize gain.

Abstract: The invention provides a zener zap diode having a high reliability and a method of manufacturing the same that can remove the problems accompanied with the zener zap trimming. In order to attain the object, the zener zap diode according to the invention is constructed such that, in an area adjacent to the surface of a semiconductor substrate, an active base region, an outer base region, and an emitter region are formed. Furthermore, a base lead electrode (one polysilicon layer) is formed to overlay the outer base region, and an emitter lead electrode (another polysilicon layer) is formed above the active base region. A contact between the one polysilicon layer and a metal interconnecting layer is disposed right above the outer base region. Since the insulation film that hinders the filament from being formed is not disposed under the one polysilicon layer, a filament is widely formed into an N-type well region when a PN junction is zapped by the zener zap trimming method.

Abstract: A magnetic tunnel junction (MTJ) memory cell uses a biasing ferromagnetic layer in the MTJ stack of layers that is magnetostatically coupled with the free ferromagnetic layer in the MTJ stack to provide transverse and/or longitudinal bias fields to the free ferromagnetic layer. The MTJ is formed on an electrical lead on a substrate and is made up of a stack of layers.

Abstract: A magnetoresistive element comprises an n-type emitter layer, a p-type base layer, and an n-type collector layer, the three layers being so arranged as to form a pn-junction with each other, an emitter ferromagnetic layer formed in contact with the n-type emitter layer, a base ferromagnetic layer formed in contact with the p-type base layer, a power source for applying, by way of the emitter ferromagnetic layer, a forward bias voltage between the n-type emitter layer and the p-type base layer, a power source for applying a backward bias voltage to the n-type collector layer and the p-type base layer and a power source for applying, by way of the base ferromagnetic layer, a bias voltage so as to inject minority carriers into the p-type base layer.

Abstract: A substantially concentric lateral bipolar transistor having a base region that is disposed about a periphery of an emitter region, and a collector region that is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants.

Abstract: A micro-switch having a flexible conductive membrane which is moved by an external force, such as pressure from an air flow, to establish a connection between contact pads. The conductive membrane is stretched over one or more spacer pads to introduce deformation in the conductive membrane, thereby improving the accuracy and repeatability of the micro-switch. The spacing between the contact pads and the conductive membrane is precisely controlled by controlling the height difference between the spacer pads and the conductive pads. This height difference is determined by one or more precisely controlled etch operations.

Abstract: A lateral Hall element includes a substrate, a first-conductivity type active layer formed on the substrate, a first second-conductivity type semiconductor layer formed to surround the first-conductivity type active layer and formed to a depth to reach the substrate, a pair of first first-conductivity type semiconductor layers of high impurity concentration selectively formed with a preset distance apart from each other on the surface of the first-conductivity type active layer, current supply electrodes respectively formed on the pair of first first-conductivity type semiconductor layers, a pair of second first-conductivity type semiconductor layers of high impurity concentration formed with a preset distance apart from each other on the surface of the first-conductivity type active layer in position different from the first first-conductivity type semiconductor layers, sensor electrodes respectively formed on the pair of second first-conductivity type semiconductor layers, and a plurality of second second-c

Abstract: A vertical Hall element is formed within the epitaxial layer of a semiconductor and isolated from other components by a P type isolation diffusion. A position defining diffusion is used to accurately locate a plurality of openings within the position defining diffusion where contact diffusions are made. The position defining diffusion is made simultaneously with the base diffusion for transistors within the integrated circuit and the contact diffusions are made simultaneously with the emitter diffusion of transistors within the integrated circuit. Five contact diffusions are provided on the upper surface of the epitaxial layer and generally aligned within the region defined as the Hall element by the isolation diffusions. The center contact is used to provide electrical current flowing through the Hall effect element. Electrical current is split and flows to the two end contact diffusions.

Abstract: A magnetometer or magnetic field sensor includes semiconductor material deposited laterally on an insulating substrate. The semiconductor material is alternating regions of n- and p-type silicon provided with two cathodes, an anode and a triggering node. Upon application of a triggering pulse to a switch on the sensor, a carrier domain is formed. In the presence of a magnetic field this carrier domain is deflected to one side thus causing an imbalance in the current collected at the two cathodes.

Abstract: A pyramid shaped etch is made in an n or p type silicon substrate, or any symmetric etch with slanted edges, with p or n type implants in the slanted edges of the etch to form a PN junction. On this structure, an emitter and two collectors are formed by further implanting n+ regions in the PN junction region. To complete the device, ohmic contacts are formed to establish a base region. In operation, an appropriate bias is applied to the emitter through to the base and collectors. By so biasing the device, the device operates as a standard bipolar transistor. The currents of both the minority and majority carriers in the base region will respond to the component of the magnetic field perpendicular to the face of the slanted etch. As a result, there will be a difference in the currents in the collectors. These currents can then be simply calibrated to measure the magnetic field component.

Abstract: A collector arrangement for a magnetotransistor (10, 25, 30) and a method for making the magnetotransistor (10, 25, 30). A portion of a semiconductor substrate (11) is doped to form a base region (13). The base region is doped to form an emitter region (16, 26, 36) and a collector region (17, 27, 37) such that the collector region (17, 27, 37) surrounds and is spaced apart from the emitter region (16, 26, 36). Collector contacts (C.sub.1 -C.sub.8 and C.sub.5 '-C.sub.8 ', C.sub.13 -C.sub.16) are symmetrically formed in the collector region (17, 27, 37). In a three-dimensional magnetotransistor (10, 25) the collector contacts include split-collector contacts (C.sub.5 -C.sub.8 and C.sub.5 '-C.sub.8 ').

Abstract: An infrared detector comprises a thin film of photo-responsive material on transparent dielectric material with an array of planar antennae adjacent to the film surface. The antennae are separate from ohmic contacts arranged to connect the film to an external circuit. The antennae concentrate radiation in fringe fields at antenna edges and extremities interacting with the photo-responsive material. The detectors may be photovoltaic or photoconductive. The antennae may be rectangular, bow-tie, cruciform, elliptic, circular or square, and are dimensioned for resonance (preferably half-wavelength resonance) at frequencies within the photo-responsive material absorption band. Half-wavelength resonant antennae are best matched by F/0.7 optics. The detector may be a reticulated array. The dielectric material may be formed as a lens.

Abstract: A magnetic field sensor is provided by a lateral bipolar transistor having a base region formed of a first conductivity type, an emitter region formed of a second conductivity type disposed in the base region for emitting charge carriers, and a collector region of the second conductivity type disposed in the base region for receiving charge carriers from the emitter region. A first and second metallic contact are connected to the collector region for splitting the collector current into first and second collector contact currents. In the presence of a magnetic field, a number of the charge carriers are deflected toward the first or the second metallic contact, depending on the orientation of the magnetic field, causing an imbalance in the first and second collector contact currents. The noise at the metallic contacts is the same as the noise of a single collector transistor which effectively correlates the noise with itself and cancels any distortion associated with the noise.

Abstract: An electronic component especially a permeable base transister is provided as a composite of homoepitaxially grown layers so that space-charge zones defined by the permeable base are formed as pn-junctions between an n-conducting layer and a p-conducting layer.